| commit | c20fb887b61d2d2bacc8a836dfa766e190f6d95b | [log] [tgz] |
|---|---|---|
| author | roy zang <tie-fei.zang@freescale.com> | Mon Dec 04 17:54:21 2006 +0800 |
| committer | Zang Tiefei <roy@bus.ap.freescale.net> | Mon Dec 04 17:54:21 2006 +0800 |
| tree | f14a1b9562b8a71f77855e748716c373cf1749c6 | |
| parent | 10c4ce9682f2b0abc718dc2bc4ad9723b9678f2b [diff] |
Introduce PLL_CFG[0:4] table for processor 7448/7447A/7455/7457. The original multiplier table can not refect the real PLL clock behavior of these processors. Please refer to the hardware specification for detailed information of the corresponding processors. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>