board: colibri-imx6ull: fix detecting ethernet phy
Now that it is possible to use regulator-fixed-clock make use
of it. This makes U-Boot detect the PHY on first cold-boot.
This commit also adjusts the code in setup_fec and follows
how it is done in mx6ullevk.c
This commit also slows down the boot-process by about 150ms
as it now waits for the regulator-fixed-clock voltage that
drives the PHY to go up.
If you rely on very fast boot-speeds and don't need ethernet
for your boot-process you can safely revert the changes on
imx6ull-colibri.dtsi
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
diff --git a/arch/arm/dts/imx6ull-colibri.dtsi b/arch/arm/dts/imx6ull-colibri.dtsi
index 56ee289..88d5e15 100644
--- a/arch/arm/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/dts/imx6ull-colibri.dtsi
@@ -64,6 +64,18 @@
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
vin-supply = <®_5v0>;
};
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed-clock";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_phy";
+ regulator-type = "voltage";
+ vin-supply = <®_module_3v3>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ startup-delay-us = <150000>;
+ };
};
&adc1 {
@@ -84,6 +96,7 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
+ phy-supply = <®_eth_phy>;
status = "okay";
mdio {
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index 3244184..ba4e0df 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -100,26 +100,19 @@
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
- /* provide the PHY clock from the i.MX 6 */
+ /*
+ * Use 50MHz anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
if (ret)
return ret;
- /* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
- clrsetbits_le32(&iomuxc_regs->gpr[1],
- IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
- IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
-
- /* give new Ethernet PHY power save mode circuitry time to settle */
- mdelay(300);
-
- return 0;
-}
+ enable_enet_clk(1);
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
return 0;
}
#endif /* CONFIG_FEC_MXC */