diff --git a/doc/README.dk1c20 b/doc/README.dk1c20
index bf3b699..3c0e41b 100644
--- a/doc/README.dk1c20
+++ b/doc/README.dk1c20
@@ -24,7 +24,7 @@
 
 1. Files
 =========
-	board/dk1c20/*
+	board/altera/dk1c20/*
 	include/configs/DK1C20.h
 
 2. Memory Organization
@@ -73,11 +73,7 @@
 2. Quit nios-run and start your terminal application (e.g. start
 Hyperterminal or minicom).
 
-3. From the U-Boot command prompt, erase flash 0x40000 to 0x 5ffff:
-
-    ==> erase 1:4-5
-
-4. Download the u-boot code to RAM. When using Hyperterminal, do the
+3. Download the u-boot code to RAM. When using Hyperterminal, do the
 following:
 
    a.  From the u-boot command prompt start a binary download to SRAM:
@@ -86,6 +82,10 @@
 
     b. Download u-boot.bin using kermit.
 
+4. From the U-Boot command prompt, erase flash 0x40000 to 0x5ffff:
+
+    ==> erase 1:4-5
+
 5. Copy the binary image from SRAM to flash:
 
     ==> cp.b 800000 40000 10000
diff --git a/doc/README.dk1c20_std32 b/doc/README.dk1c20_std32
index 4822c6f..521fab7 100644
--- a/doc/README.dk1c20_std32
+++ b/doc/README.dk1c20_std32
@@ -91,10 +91,10 @@
   0x02000000 ---32-----------16|15------------0-
 	       |	       :	       | \
 	       |	       :	       | |
-  SDRAM	       |	       :	       |  > CFG_NIOS_CPU_SRAM_SIZE
+  SDRAM	       |	       :	       |  > CFG_NIOS_CPU_SDRAM_SIZE
 	       |	       :	       | |   = 0x01000000
 	       |	       :	       | /
-  0x01000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SRAM_BASE
+  0x01000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SDRAM_BASE
 	       |			       |
 	       :	      gap	       :
 	       :			       :
@@ -345,6 +345,7 @@
 	       |	       :	       | |
   0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
 	       |	       :	       | /
+  0x00000000   |- - - - - - - -:- - - - - - - -+- - u-boot environment
   0x00000000 ---8-------------4|3-------------0-
 
 
diff --git a/doc/README.dk1s10 b/doc/README.dk1s10
new file mode 100644
index 0000000..bb8375a
--- /dev/null
+++ b/doc/README.dk1s10
@@ -0,0 +1,131 @@
+
+			 Nios Development Kit
+			   Startix Editions
+
+		    Last Update: January 28, 2004
+====================================================================
+
+This file contains information regarding U-Boot and the Altera
+Nios Development Kit, Startix Edition (DK-1S10). For general Nios
+information see doc/README.nios.
+
+Most stuff of this file was borrowed and based on README.dk1c20,
+the DK-1C20 related information file.
+
+For those interested in contributing ... see HELP WANTED section
+in doc/README.nios.
+
+Contents:
+
+	1. Files
+	2. Memory Organization
+	3. CPU Variations
+	4. Examples
+	5. Programming U-Boot into FLASH with GERMS
+
+====================================================================
+
+1. Files
+=========
+	board/altera/dk1s10/*
+	include/configs/DK1S10.h
+
+2. Memory Organization
+=======================
+
+	-The heap is placed below the monitor (U-Boot code).
+	-Global data is placed below the heap.
+	-The stack is placed below global data (&grows down).
+
+3. CPU Variations
+=================
+
+There are more than one NIOS CPU variation for the DK-1S10. U-Boot
+supports the following CPU configurations:
+
+	- Altera Standard 32 (make DK1S10_standard_32_config)
+	- Microtronix LDK 2.0 (make DK1S10_mtx_ldk_20_config)
+
+4. Examples
+============
+
+The hello_world example was never tested on DK-1S10. Neverthelse
+it should work as far as possible, because the DK-1S10 port is
+more than ninetieth percents equal to the DK-1C20 port and at
+this platform the hello_world example was already tested
+successfully (see README.dk1c20).
+
+
+5. Programming U-Boot into FLASH with GERMS
+============================================
+The current version of the DK-1S10 port with the default
+configuration settings occupies about 78 KBytes of flash.
+A minimal configuration occupies less than 60 KByte
+(network support disabled).
+
+To program U-Boot into the DK-1S10 flash using GERMS do the
+following:
+
+1. From the command line, download U-Boot using the nios-run:
+
+	$ nios-run -r u-boot.srec
+
+This takes about 45 seconds (GERMS is not very speedy here).
+After u-boot is downloaded it will be executed. You should
+see the following:
+
+    U-Boot 1.0.2 (Jan 28 2004 - 19:02:30)
+
+    CPU: Nios-32 Rev. 3.3 (0x3038)
+    Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14
+    Board: Altera Nios 1S10 Development Kit
+    In:    serial
+    Out:   serial
+    Err:   serial
+    DK1S10 >
+
+
+2. Quit nios-run and start your terminal application (e.g. start
+   Hyperterminal or minicom).
+
+3. Download the u-boot code to RAM. When using Hyperterminal, do the
+   following:
+
+   a. From the u-boot command prompt start a binary download to
+      SRAM / SDRAM:
+
+      at the Altera Standard 32 to SRAM:
+
+	==> loadb 800000
+
+      at the Microtronix LDK 2.0 to SDRAM:
+
+	==> loadb 1010000
+
+   b. Download u-boot.bin using kermit.
+
+4. From the U-Boot command prompt, erase flash:
+
+   at the Altera Standard 32 from 0x40000 to 0x5ffff:
+
+	==> erase 1:4-5
+
+   at the Microtronix LDK 2.0 from 0x8000000 to 0x81ffff:
+
+	==> erase 1:0-1
+
+5. Copy the binary image from SRAM / SDRAM to flash:
+
+   at the Altera Standard 32 to SRAM:
+
+	==> cp.b 800000 40000 $(filesize)
+
+   at the Microtronix LDK 2.0 to SDRAM:
+
+	==> cp.b 1010000 8000000 $(filesize)
+
+U-Boot will now automatically start when the board is powered on or
+reset using the Standard-32 configuration. To start U-Boot with the
+Safe-32 configuration, enter the following GERMS command:
+
+    + g 40000
diff --git a/doc/README.dk1s10_mldk20 b/doc/README.dk1s10_mldk20
new file mode 100644
index 0000000..fcf8170
--- /dev/null
+++ b/doc/README.dk1s10_mldk20
@@ -0,0 +1,286 @@
+
+TODO:	specify IDE i/f
+
+
+===============================================================================
+	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
+===============================================================================
+see also [1]-[5]
+
+CPU:	"LDK2"
+	32 bit NIOS for 75 MHz
+	512 Byte for register file (30 levels)
+	with out instruction cache
+	with out data cache
+	2 KByte On Chip ROM with GERMS boot monitor
+	with out On Chip RAM
+	MSTEP multiplier
+	no Debug Core
+	no On Chip Instrumentation (OCI)
+
+	U-Boot CFG:	CFG_NIOS_CPU_CLK	     = 75000000
+			CFG_NIOS_CPU_ICACHE	     = (not present)
+			CFG_NIOS_CPU_DCACHE	     = (not present)
+			CFG_NIOS_CPU_REG_NUMS	     = 512
+			CFG_NIOS_CPU_MUL	     = 0
+			CFG_NIOS_CPU_MSTEP	     = 1
+			CFG_NIOS_CPU_DBG_CORE	     = 0
+
+IRQ:	 Nr.  | used by
+	------+--------------------------------------------------------
+	 16   | TIMER0	  |  CFG_NIOS_CPU_TIMER0_IRQ = 16
+	 17   | UART0	  |  CFG_NIOS_CPU_UART0_IRQ  = 17
+	 18   | UART1	  |  CFG_NIOS_CPU_UART1_IRQ  = 18
+	 20   | LAN91C111 |  CFG_NIOS_CPU_LAN0_IRQ   = 20
+	 25   | IDE0	  |  CFG_NIOS_CPU_IDE0_IRQ   = 25
+
+MEMORY:	 8 MByte Flash
+	16 MByte SDRAM
+
+Timer:	TIMER0: high priority programmable timer (IRQ16)
+
+	U-Boot CFG:	CFG_NIOS_CPU_TICK_TIMER	     = 0
+			CFG_NIOS_CPU_USER_TIMER	     = (not present)
+
+PIO:	 Nr.  | description
+	------+--------------------------------------------------------
+	 PIO0 | CFPOWER:    1 output to controll CF power supply
+	 PIO1 | BUTTON:	    4 inputs for user push buttons (no IRQ)
+	------+--------------------------------------------------------
+	 not  | LCD:	   11 in/outputs for ASCII LCD
+	 pres.| LED:	    8 outputs for user LEDs
+	      | SEVENSEG:  16 outputs for user seven segment display
+	      | RECONF:	    1 in/output for . . . . . . . . . . . .
+	      | CFPRESENT:  1 input for CF present event (IRQ35)
+	      | CFATASEL:   1 output to controll CF ATA card select
+
+	U-Boot CFG:	CFG_NIOS_CPU_BUTTON_PIO	     = 1
+			CFG_NIOS_CPU_LCD_PIO	     = (not present)
+			CFG_NIOS_CPU_LED_PIO	     = (not present)
+			CFG_NIOS_CPU_SEVENSEG_PIO    = (not present)
+			CFG_NIOS_CPU_RECONF_PIO	     = (not present)
+			CFG_NIOS_CPU_CFPRESENT_PIO   = (not present)
+			CFG_NIOS_CPU_CFPOWER_PIO     = 0
+			CFG_NIOS_CPU_CFATASEL_PIO    = (not present)
+
+UART:	UART0: fixed baudrate of 115200, fixed protocol 8N2,
+	       without handshake RTS/CTS (IRQ17)
+	UART1: fixed baudrate of 115200, fixed protocol 8N1,
+	       without handshake RTS/CTS (IRQ18)
+
+LAN:	SMsC LAN91C111 with:
+	  - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
+	  - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
+
+IDE:	(TODO)
+
+
+===============================================================================
+	M E M O R Y   M A P
+===============================================================================
+
+- - - - - - - - - - -   external memory   - - - - - - - - - - - - - - - - - - -
+
+  0x02000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_STACK
+  0x02000000 --+32-----------16|15------------0+
+	       |	       .	       | \ \
+	       |	       .	       | | |
+	       |	       .	       | |  > stack area
+	       |	       .	       | | |
+	       |	       .	       | | V
+	       |	       .	       | |
+	       |	       .	       | |
+  SDRAM	       |	       .	       |  > CFG_NIOS_CPU_SDRAM_SIZE
+	       |	       .	       | |   = 0x01000000
+	       |	       .	       | |
+  0x01000100   |- - - - - - - - - - - - - - - -+-|-
+	       |	       .	       | | \
+	       |	       .	       | | |
+	       |	       .	       | |  > CFG_NIOS_CPU_VEC_SIZE
+	       |	       .	       | | |   = 0x00000100
+	       |			       | / /
+  0x01000000   |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE
+  0x01000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SDRAM_BASE
+	       |  sector 127		       | \
+    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
+	       |	       :	       | |
+  Flash	       |-   -	-   -  :  -   -	  -   -|  > CFG_NIOS_CPU_FLASH_SIZE
+	       |  sector 1     :	       | |   = 0x00800000
+    + 0x010000 |- - - - - - - - - - - - - - - -| |
+	       |  sector 0 (size = 0x10000)    | /
+  0x00800000 ---8-------------4|3-------------0-    CFG_NIOS_CPU_FLASH_BASE
+	       |			       |
+	       :	      gap	       :
+	       :			       :
+
+- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -
+
+	       :			       :
+	       :	      gap	       :
+	       |			       |
+  0x00020000 ---32-----------16|15------------0-
+	       |	      gap	       | \
+  0x00010310 --+-------------------------------| |
+	       |			       | |
+	       |  register bank (size = 0x10)  | |
+	       | +--------.---.---.---	       | |
+	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
+	       | |---------------------------+ | |
+  LAN91C111    | | BANK	       | RESERVED    | | |
+	       | |- - - - - - -|- - - - - - -| |  > na_enet_size
+	       | | RPCR	       | MIR	     | | |   = 0x00010000
+	       | |- - - - - - -|- - - - - - -| | |
+	       | | COUNTER     | RCR	     | | |
+	       | |- - - - - - -|- - - - - - -| | |
+	       | | EPH STATUS  | TCR	     | | |
+	       | +---------------------------+ | |
+  0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| |
+	       |	      gap	       | /
+  0x00010000 ---32-----------16|15------------0-    CFG_NIOS_CPU_LAN0_BASE
+	       |			       |
+	       :	      gap	       :
+	       :			       :
+
+- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
+
+	       :			       :
+	       :	      gap	       :
+	       |			       |
+  0x00000980 ---32-----------16|15------------0-
+	       |	       |	       | \
+	       :  (real size   :	       : |
+  IDE i/f      :   and content :	       :  > 0x00000080
+  [5]	       :   unknown)    :	       : |
+	       |	       |	       | /
+  0x00000900 ---32-----------16|15------------0-    CFG_NIOS_CPU_IDE0
+	       |			       | \
+	       :	      gap	       :  > (space for PIO4..7)
+	       |			       | /
+  0x000008c0 ---32-----------16|15------------0-
+	       |		     (unused)  | \
+	+ 0x1c |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x18 |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x14 |- - - - - - - - - - - - - - - -| |
+  UART1	       |		     (unused)  |  > 0x00000020
+  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
+	       |  control (10 bit)	 (rw)  | |
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+	       |  status (10 bit)	 (rw)  | |
+	+ 0x08 |- - - - - - - - - - - - - - - -| |
+	       |  txdata (8 bit)	 (wo)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  rxdata (8 bit)	 (ro)  | /
+  0x000008a0 ---32-----------16|15------------0-    CFG_NIOS_CPU_UART1
+	       |			       | \
+	       :	      gap	       :  > (space for PIO2..3)
+	       |			       | /
+  0x00000880 ---32-----------16|15------------0-
+	       |  edgecapture (4 bit)	 (rw)  | \
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+  PIO1	       |  interruptmask (4 bit)	 (rw)  | |
+  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
+	       |		     (unused)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  data (4 bit)		 (ro)  | /
+  0x00000870 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO1
+	       |		     (unused)  | \
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+  PIO0	       |		     (unused)  | |
+  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
+	       |		     (unused)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  data (1 bit)		 (wo)  | /
+  0x00000860 ---32-----------16|15------------0-    CFG_NIOS_CPU_PIO0
+	       |		     (unused)  | \
+	+ 0x1c |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x18 |- - - - - - - - - - - - - - - -| |
+	       |  snaph (16 bit)	 (rw)  | |
+	+ 0x14 |- - - - - - - - - - - - - - - -| |
+  TIMER0       |  snapl (16 bit)	 (rw)  | |
+  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
+	       |  periodh (16 bit)	 (rw)  | |
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+	       |  periodl (16 bit)	 (rw)  | |
+	+ 0x08 |- - - - - - - - - - - - - - - -| |
+	       |  control (4 bit)	 (rw)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  status (2 bit)	 (rw)  | /
+  0x00000840 ---32-----------16|15------------0-    CFG_NIOS_CPU_TIMER0
+	       |			       | \
+	       :	      gap	       :  > (space for UART2)
+	       |			       | /
+  0x00000820 ---32-----------16|15------------0-
+	       |		     (unused)  | \
+	+ 0x1c |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x18 |- - - - - - - - - - - - - - - -| |
+	       |		     (unused)  | |
+	+ 0x14 |- - - - - - - - - - - - - - - -| |
+  UART0	       |		     (unused)  |  > 0x00000020
+  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
+	       |  control (10 bit)	 (rw)  | |
+	+ 0x0c |- - - - - - - - - - - - - - - -| |
+	       |  status (10 bit)	 (rw)  | |
+	+ 0x08 |- - - - - - - - - - - - - - - -| |
+	       |  txdata (8 bit)	 (wo)  | |
+	+ 0x04 |- - - - - - - - - - - - - - - -| |
+	       |  rxdata (8 bit)	 (ro)  | /
+  0x00000800 ---32-----------16|15------------0-    CFG_NIOS_CPU_UART0
+
+- - - - - - - - - - -  on chip memory 1	  - - - - - - - - - - -
+
+  0x00000800 ---32-----------16|15------------0-
+	       |	       :	       | \
+	       |	       :	       | |
+  GERMS	       |	       :	       |  > CFG_NIOS_CPU_ROM_SIZE
+	       |	       :	       | |   = 0x00000800
+	       |	       :	       | /
+  0x00000000   |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
+  0x00000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_ROM_BASE
+
+===============================================================================
+	F L A S H   M E M O R Y	  A L L O C A T I O N
+===============================================================================
+
+  0x01000000 ---8-------------4|3-------------0-
+	       |	       :	       | \
+  SAFE	       |	       :	       |  > 1 MByte
+  FPGA conf.   |	       :	       | /    (NOT usable by software)
+  0x00f00000 --+- - - - - - - -:- - - - - - - -+-
+	       |	       :	       | \
+  USER	       |	       :	       |  > 1 MByte
+  FPGA conf.   |	       :	       | /    (NOT usable by software)
+  0x00e00000 --+- - - - - - - -:- - - - - - - -+-
+	       |	       :	       | \
+	       |	       :	       | |
+  WEB pages    |	       :	       |  > 2 MByte
+	       |	       :	       | |    (provisory usable)
+	       |	       :	       | /
+  0x00c00000 --+- - - - - - - -:- - - - - - - -+-
+	       |	       :	       | \
+	       |	       :	       | |
+	       |	       :	       | |
+	       |	       :	       |  > 4 MByte free for use
+	       |	       :	       | |
+  0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
+	       |	       :	       | /
+  0x00800000   |- - - - - - - -:- - - - - - - -+- - u-boot _start()
+  0x00800000 ---8-------------4|3-------------0-
+
+
+===============================================================================
+	R E F E R E N C E S
+===============================================================================
+[1]	http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
+[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[5]	http://www.opencores.org/projects/ata/
+	http://www.t13.org/index.html
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk1s10_std32 b/doc/README.dk1s10_std32
index 33ae15e..d649eb3 100644
--- a/doc/README.dk1s10_std32
+++ b/doc/README.dk1s10_std32
@@ -87,10 +87,10 @@
   0x02000000 ---32-----------16|15------------0-
 	       |	       :	       | \
 	       |	       :	       | |
-  SDRAM	       |	       :	       |  > CFG_NIOS_CPU_SRAM_SIZE
+  SDRAM	       |	       :	       |  > CFG_NIOS_CPU_SDRAM_SIZE
 	       |	       :	       | |   = 0x01000000
 	       |	       :	       | /
-  0x01000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SRAM_BASE
+  0x01000000 ---32-----------16|15------------0-    CFG_NIOS_CPU_SDRAM_BASE
 	       |			       |
 	       :	      gap	       :
 	       :			       :
@@ -335,6 +335,7 @@
 	       |	       :	       | |
   0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
 	       |	       :	       | /
+  0x00000000   |- - - - - - - -:- - - - - - - -+- - u-boot environment
   0x00000000 ---8-------------4|3-------------0-
 
 
diff --git a/doc/README.dk20k200_std32 b/doc/README.dk20k200_std32
index 2c2b1d6..7b5d4d4 100644
--- a/doc/README.dk20k200_std32
+++ b/doc/README.dk20k200_std32
@@ -117,7 +117,7 @@
 	+ 0x18 |- - - - - - - - - - - - - - - -| |
 	       |		     (unused)  | |
 	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART0	       |		     (unused)  |  > 0x00000020
+  UART1	       |		     (unused)  |  > 0x00000020
   [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
 	       |  control (10 bit)	 (rw)  | |
 	+ 0x0c |- - - - - - - - - - - - - - - -| |
diff --git a/doc/README.nios b/doc/README.nios
index af21b3e..08f4e7e 100644
--- a/doc/README.nios
+++ b/doc/README.nios
@@ -1,7 +1,7 @@
 
 			   U-Boot for Nios-32
 
-		    Last Update: January 2, 2004
+		    Last Update: February 1, 2004
 ====================================================================
 
 This file contains information regarding U-Boot and the Altera
@@ -103,6 +103,13 @@
 CFG_NIOS_ASMIBASE -- the base address of the ASMI peripheral.
 	(standard-32: na_asmi_base).
 
+CFG_NIOS_SPIBASE -- the base address of the SPI master (!) peripheral.
+	(nasys_spi_0)
+
+CFG_NIOS_SPIBITS -- the amount of configured SPI data bits in PTF.
+	This value can be 8 or 16 only! (PTF: databits)
+
+
 2.2 Differences in U-Boot Options/Settings
 -------------------------------------------
 Some 'standard' U-Boot options/settings are treated differently in