Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Add base support for Marvell OcteonTX2 CN9130 CRB (mostly done
by Kostya)
- Sync Armada 3k/7k/8k SERDES code with Marvell version (misc Marvell
authors)
- pci-aardvark: Fix processing PIO transfers (Pali)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index b8ba00b..5d92257 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -91,9 +91,8 @@
}
#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
-static int dw_mdio_reset(struct mii_dev *bus)
+static int __dw_mdio_reset(struct udevice *dev)
{
- struct udevice *dev = bus->priv;
struct dw_eth_dev *priv = dev_get_priv(dev);
struct dw_eth_pdata *pdata = dev_get_plat(dev);
int ret;
@@ -122,6 +121,13 @@
return 0;
}
+
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+
+ return __dw_mdio_reset(dev);
+}
#endif
#if IS_ENABLED(CONFIG_DM_MDIO)
@@ -142,9 +148,10 @@
#if CONFIG_IS_ENABLED(DM_GPIO)
int designware_eth_mdio_reset(struct udevice *mdio_dev)
{
- struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+ struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
+ struct udevice *dev = mdio_pdata->mii_bus->priv;
- return dw_mdio_reset(pdata->mii_bus);
+ return __dw_mdio_reset(dev->parent);
}
#endif
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 7642a31..06be9de 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -265,6 +265,8 @@
}
#endif
+#if !defined(CONFIG_PHY)
+/* Should be done in the MXS PHY driver */
static void usb_oc_config(struct usbnc_regs *usbnc, int index)
{
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
@@ -285,6 +287,7 @@
clrbits_le32(ctrl, UCTRL_PWR_POL);
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(DM_USB)
/**
@@ -432,10 +435,12 @@
struct clk clk;
struct phy phy;
enum usb_init_type init_type;
+#if !defined(CONFIG_PHY)
int portnr;
void __iomem *phy_addr;
void __iomem *misc_addr;
void __iomem *anatop_addr;
+#endif
};
static int mx6_init_after_reset(struct ehci_ctrl *dev)
@@ -448,14 +453,14 @@
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
@@ -558,6 +563,7 @@
static int mx6_parse_dt_addrs(struct udevice *dev)
{
+#if !defined(CONFIG_PHY)
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
int phy_off, misc_off;
const void *blob = gd->fdt_blob;
@@ -594,7 +600,7 @@
priv->misc_addr = addr;
-#if !defined(CONFIG_PHY) && defined(CONFIG_MX6)
+#if defined(CONFIG_MX6)
int anatop_off;
/* Resolve ANATOP offset through USB PHY node */
@@ -608,6 +614,7 @@
priv->anatop_addr = addr;
#endif
+#endif
return 0;
}
@@ -661,14 +668,14 @@
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {