| commit | c04362fe68939b88ae4e4601c3c193b343ec709d | [log] [tgz] |
|---|---|---|
| author | Roy Zang <tie-fei.zang@freescale.com> | Mon Mar 25 07:33:15 2013 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Tue May 14 16:00:25 2013 -0500 |
| tree | 9538eddba53eddde5398ec18d4cbbcf339770094 | |
| parent | 5631c64fb9700d928faaa61388a96a6c085ea31d [diff] |
T4/serdes: fix the serdes clock frequency Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>