Merge branch 'master' of git://git.denx.de/u-boot-i2c
diff --git a/README b/README
index fe5cacb..55c3fcd 100644
--- a/README
+++ b/README
@@ -4676,6 +4676,33 @@
window->master inbound window->master LAW->the ucode address in
master's memory space.
+Freescale Layerscape Management Complex Firmware Support:
+---------------------------------------------------------
+The Freescale Layerscape Management Complex (MC) supports the loading of
+"firmware".
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_FSL_MC_ENET
+ Enable the MC driver for Layerscape SoCs.
+
+- CONFIG_SYS_LS_MC_FW_ADDR
+ The address in the storage device where the firmware is located. The
+ meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro
+ is also specified.
+
+- CONFIG_SYS_LS_MC_FW_LENGTH
+ The maximum possible size of the firmware. The firmware binary format
+ has a field that specifies the actual size of the firmware, but it
+ might not be possible to read any part of the firmware unless some
+ local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_LS_MC_FW_IN_NOR
+ Specifies that MC firmware is located in NOR flash, mapped as
+ normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
+ virtual address in NOR flash.
+
Building the Software:
======================
diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
index bf2fa2a..cfad206 100644
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -2,48 +2,457 @@
* Low-level initialization for EP93xx
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2013
+ * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ * Copyright (C) 2006 Cirrus Logic Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
+#include <config.h>
+#include <asm/arch-ep93xx/ep93xx.h>
+
+/*
+/* Configure the SDRAM based on the supplied settings.
+ *
+ * Input: r0 - SDRAM DEVCFG register
+ * r2 - configuration for SDRAM chips
+ * Output: none
+ * Modifies: r3, r4
+ */
+ep93xx_sdram_config:
+ /* Program the SDRAM device configuration register. */
+ ldr r3, =SDRAM_BASE
+#ifdef CONFIG_EDB93XX_SDCS0
+ str r0, [r3, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+ str r0, [r3, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+ str r0, [r3, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+ str r0, [r3, #SDRAM_OFF_DEVCFG3]
+#endif
+
+ /* Set the Initialize and MRS bits (issue continuous NOP commands
+ * (INIT & MRS set))
+ */
+ ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Delay for 200us. */
+ mov r4, #0x3000
+delay1:
+ subs r4, r4, #1
+ bne delay1
+
+ /* Clear the MRS bit to issue a precharge all. */
+ ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Temporarily set the refresh timer to 0x10. Make it really low so
+ * that refresh cycles are generated.
+ */
+ ldr r4, =0x10
+ str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+ /* Delay for at least 80 SDRAM clock cycles. */
+ mov r4, #80
+delay2:
+ subs r4, r4, #1
+ bne delay2
+
+ /* Set the refresh timer to the fastest required for any device
+ * that might be used. Set 9.6 ms refresh time.
+ */
+ ldr r4, =0x01e0
+ str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+ /* Select mode register update mode. */
+ ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
+ EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Program the mode register on the SDRAM by performing fake read */
+ ldr r4, [r2]
+
+ /* Select normal operating mode. */
+ ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
+ str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+ /* Return to the caller. */
+ mov pc, lr
+
+/*
+ * Test to see if the SDRAM has been configured in a usable mode.
+ *
+ * Input: r0 - Test address of SDRAM
+ * Output: r0 - 0 -- Test OK, -1 -- Failed
+ * Modifies: r0-r5
+ */
+ep93xx_sdram_test:
+ /* Load the test patterns to be written to SDRAM. */
+ ldr r1, =0xf00dface
+ ldr r2, =0xdeadbeef
+ ldr r3, =0x08675309
+ ldr r4, =0xdeafc0ed
+
+ /* Store the test patterns to SDRAM. */
+ stmia r0, {r1-r4}
+
+ /* Load the test patterns from SDRAM one at a time and compare them
+ * to the actual pattern.
+ */
+ ldr r5, [r0]
+ cmp r5, r1
+ ldreq r5, [r0, #0x0004]
+ cmpeq r5, r2
+ ldreq r5, [r0, #0x0008]
+ cmpeq r5, r3
+ ldreq r5, [r0, #0x000c]
+ cmpeq r5, r4
+
+ /* Return -1 if a mismatch was encountered, 0 otherwise. */
+ mvnne r0, #0xffffffff
+ moveq r0, #0x00000000
+
+ /* Return to the caller. */
+ mov pc, lr
+
+/*
+ * Determine the size of the SDRAM. Use data=address for the scan.
+ *
+ * Input: r0 - Start SDRAM address
+ * Return: r0 - Single block size
+ * r1 - Valid block mask
+ * r2 - Total block count
+ * Modifies: r0-r5
+ */
+ep93xx_sdram_size:
+ /* Store zero at offset zero. */
+ str r0, [r0]
+
+ /* Start checking for an alias at 1MB into SDRAM. */
+ ldr r1, =0x00100000
+
+ /* Store the offset at the current offset. */
+check_block_size:
+ str r1, [r0, r1]
+
+ /* Read back from zero. */
+ ldr r2, [r0]
+
+ /* Stop searching of an alias was found. */
+ cmp r1, r2
+ beq found_block_size
+
+ /* Advance to the next power of two boundary. */
+ mov r1, r1, lsl #1
+
+ /* Loop back if the size has not reached 256MB. */
+ cmp r1, #0x10000000
+ bne check_block_size
+
+ /* A full 256MB of memory was found, so return it now. */
+ ldr r0, =0x10000000
+ ldr r1, =0x00000000
+ ldr r2, =0x00000001
+ mov pc, lr
+
+ /* An alias was found. See if the first block is 128MB in size. */
+found_block_size:
+ cmp r1, #0x08000000
+
+ /* The first block is 128MB, so there is no further memory. Return it
+ * now.
+ */
+ ldreq r0, =0x08000000
+ ldreq r1, =0x00000000
+ ldreq r2, =0x00000001
+ moveq pc, lr
-#include <version.h>
-#include <asm/arch/ep93xx.h>
+ /* Save the block size, set the block address bits to zero, and
+ * initialize the block count to one.
+ */
+ mov r3, r1
+ ldr r4, =0x00000000
+ ldr r5, =0x00000001
+
+ /* Look for additional blocks of memory by searching for non-aliases. */
+find_blocks:
+ /* Store zero back to address zero. It may be overwritten. */
+ str r0, [r0]
+
+ /* Advance to the next power of two boundary. */
+ mov r1, r1, lsl #1
+
+ /* Store the offset at the current offset. */
+ str r1, [r0, r1]
+
+ /* Read back from zero. */
+ ldr r2, [r0]
+
+ /* See if a non-alias was found. */
+ cmp r1, r2
+
+ /* If a non-alias was found, then or in the block address bit and
+ * multiply the block count by two (since there are two unique
+ * blocks, one with this bit zero and one with it one).
+ */
+ orrne r4, r4, r1
+ movne r5, r5, lsl #1
+
+ /* Continue searching if there are more address bits to check. */
+ cmp r1, #0x08000000
+ bne find_blocks
+
+ /* Return the block size, address mask, and count. */
+ mov r0, r3
+ mov r1, r4
+ mov r2, r5
+
+ /* Return to the caller. */
+ mov pc, lr
+
.globl lowlevel_init
lowlevel_init:
- /* backup return address */
- ldr r1, =SYSCON_SCRATCH0
- str lr, [r1]
+
+ mov r6, lr
+
+ /* Make sure caches are off and invalidated. */
+ ldr r0, =0x00000000
+ mcr p15, 0, r0, c1, c0, 0
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* Turn off the green LED and turn on the red LED. If the red LED
+ * is left on for too long, the external reset circuit described
+ * by application note AN258 will cause the system to reset.
+ */
+ ldr r1, =EP93XX_LED_DATA
+ ldr r0, [r1]
+ bic r0, r0, #EP93XX_LED_GREEN_ON
+ orr r0, r0, #EP93XX_LED_RED_ON
+ str r0, [r1]
+
+ /* Undo the silly static memory controller programming performed
+ * by the boot rom.
+ */
+ ldr r0, =SMC_BASE
+
+ /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
+ ldr r1, =0x0000fbe0
+
+ /* Reset EP93XX_OFF_SMCBCR0 */
+ ldr r2, [r0]
+ orr r2, r2, r1
+ str r2, [r0]
+
+ ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
+ orr r2, r2, r1
+ str r2, [r0, #EP93XX_OFF_SMCBCR1]
- /* Turn on both LEDs */
- bl red_led_on
- bl green_led_on
+ ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
+ orr r2, r2, r1
+ str r2, [r0, #EP93XX_OFF_SMCBCR2]
- /* Configure flash wait states before we switch to the PLL */
- bl flash_cfg
+ ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
+ orr r2, r2, r1
+ str r2, [r0, #EP93XX_OFF_SMCBCR3]
- /* Set up PLL */
- bl pll_cfg
+ ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
+ orr r2, r2, r1
+ str r2, [r0, #EP93XX_OFF_SMCBCR6]
- /* Turn off the Green LED and leave the Red LED on */
- bl green_led_off
+ ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
+ orr r2, r2, r1
+ str r2, [r0, #EP93XX_OFF_SMCBCR7]
- /* Setup SDRAM */
- bl sdram_cfg
+ /* Set the PLL1 and processor clock. */
+ ldr r0, =SYSCON_BASE
+#ifdef CONFIG_EDB9301
+ /* 332MHz, giving a 166MHz processor clock. */
+ ldr r1, = 0x02b49907
+#else
- /* Turn on Green LED, Turn off the Red LED */
- bl green_led_on
- bl red_led_off
+#ifdef CONFIG_EDB93XX_INDUSTRIAL
+ /* 384MHz, giving a 196MHz processor clock. */
+ ldr r1, =0x02a4bb38
+#else
+ /* 400MHz, giving a 200MHz processor clock. */
+ ldr r1, =0x02a4e39e
+#endif
+#endif
+ str r1, [r0, #SYSCON_OFF_CLKSET1]
- /* FIXME: we use async mode for now */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0xc0000000
- mcr p15, 0, r0, c1, c0, 0
+ nop
+ nop
+ nop
+ nop
+ nop
- /* restore return address */
- ldr r1, =SYSCON_SCRATCH0
- ldr lr, [r1]
+ /* Need to make sure that SDRAM is configured correctly before
+ * coping the code into it.
+ */
+
+#ifdef CONFIG_EDB93XX_SDCS0
+ mov r11, #SDRAM_DEVCFG0_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+ mov r11, #SDRAM_DEVCFG1_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+ mov r11, #SDRAM_DEVCFG2_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+ ldr r0, =SYSCON_BASE
+ ldr r0, [r0, #SYSCON_OFF_SYSCFG]
+ ands r0, r0, #SYSCON_SYSCFG_LASDO
+ moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
+ movne r11, #SDRAM_DEVCFG3_ASD1_BASE
+#endif
+ /* See Table 13-5 in EP93xx datasheet for more info about DRAM
+ * register mapping */
+
+ /* Try a 32-bit wide configuration of SDRAM. */
+ ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+ EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+ EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+ EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
+
+ /* Set burst count: 4 and CAS: 2
+ * Burst mode [A11:A10]; CAS [A16:A14]
+ */
+ orr r2, r11, #0x00008800
+ bl ep93xx_sdram_config
+
+ /* Test the SDRAM. */
+ mov r0, r11
+ bl ep93xx_sdram_test
+ cmp r0, #0x00000000
+ beq ep93xx_sdram_done
+
+ /* Try a 16-bit wide configuration of SDRAM. */
+ ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+ EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+ EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+ EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
+ EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
+
+ /* Set burst count: 8, CAS: 2, sequential burst
+ * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
+ * Burst mode [A10:A9]; CAS [A15:A13]
+ */
+ orr r2, r11, #0x00004600
+ bl ep93xx_sdram_config
+
+ /* Test the SDRAM. */
+ mov r0, r11
+ bl ep93xx_sdram_test
+ cmp r0, #0x00000000
+ beq ep93xx_sdram_done
+
+ /* Turn off the red LED. */
+ ldr r0, =EP93XX_LED_DATA
+ ldr r1, [r0]
+ bic r1, r1, #EP93XX_LED_RED_ON
+ str r1, [r0]
+
+ /* There is no SDRAM so flash the green LED. */
+flash_green:
+ orr r1, r1, #EP93XX_LED_GREEN_ON
+ str r1, [r0]
+ ldr r2, =0x00010000
+flash_green_delay_1:
+ subs r2, r2, #1
+ bne flash_green_delay_1
+ bic r1, r1, #EP93XX_LED_GREEN_ON
+ str r1, [r0]
+ ldr r2, =0x00010000
+flash_green_delay_2:
+ subs r2, r2, #1
+ bne flash_green_delay_2
+ orr r1, r1, #EP93XX_LED_GREEN_ON
+ str r1, [r0]
+ ldr r2, =0x00010000
+flash_green_delay_3:
+ subs r2, r2, #1
+ bne flash_green_delay_3
+ bic r1, r1, #EP93XX_LED_GREEN_ON
+ str r1, [r0]
+ ldr r2, =0x00050000
+flash_green_delay_4:
+ subs r2, r2, #1
+ bne flash_green_delay_4
+ b flash_green
+
+
+ep93xx_sdram_done:
+ ldr r1, =EP93XX_LED_DATA
+ ldr r0, [r1]
+ bic r0, r0, #EP93XX_LED_RED_ON
+ str r0, [r1]
+
+ /* Determine the size of the SDRAM. */
+ mov r0, r11
+ bl ep93xx_sdram_size
+
+ /* Save the SDRAM characteristics. */
+ mov r8, r0
+ mov r9, r1
+ mov r10, r2
+
+ /* Compute total memory size into r1 */
+ mul r1, r8, r10
+#ifdef CONFIG_EDB93XX_SDCS0
+ ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+ ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+ ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+ ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
+#endif
+
+ /* Consider small DRAM size as:
+ * < 32Mb for 32bit bus
+ * < 64Mb for 16bit bus
+ */
+ tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
+ moveq r1, r1, lsr #1
+ cmp r1, #0x02000000
+
+#if defined(CONFIG_EDB9301)
+ /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
+ movlt r1, #0x03f0
+ movge r1, #0x01e0
+#else
+ /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
+ movlt r1, #0x0600
+ movge r1, #0x2f0
+#endif
+ str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
+
+ /* Save the memory configuration information. */
+ orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
+ stmia r0, {r8-r11}
- mov pc, lr
+ mov lr, r6
+ mov pc, lr
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index bc5fc42..a2c4032 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -354,41 +354,10 @@
}
#endif
-/*
- * Stub implementations for outer cache operations
- */
-void __v7_outer_cache_enable(void)
-{
-}
-void v7_outer_cache_enable(void)
- __attribute__((weak, alias("__v7_outer_cache_enable")));
-
-void __v7_outer_cache_disable(void)
-{
-}
-void v7_outer_cache_disable(void)
- __attribute__((weak, alias("__v7_outer_cache_disable")));
-
-void __v7_outer_cache_flush_all(void)
-{
-}
-void v7_outer_cache_flush_all(void)
- __attribute__((weak, alias("__v7_outer_cache_flush_all")));
-
-void __v7_outer_cache_inval_all(void)
-{
-}
-void v7_outer_cache_inval_all(void)
- __attribute__((weak, alias("__v7_outer_cache_inval_all")));
-
-void __v7_outer_cache_flush_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_flush_range(u32 start, u32 end)
- __attribute__((weak, alias("__v7_outer_cache_flush_range")));
-
-void __v7_outer_cache_inval_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_inval_range(u32 start, u32 end)
- __attribute__((weak, alias("__v7_outer_cache_inval_range")));
+/* Stub implementations for outer cache operations */
+__weak void v7_outer_cache_enable(void) {}
+__weak void v7_outer_cache_disable(void) {}
+__weak void v7_outer_cache_flush_all(void) {}
+__weak void v7_outer_cache_inval_all(void) {}
+__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
+__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index cbe1d40..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 2f1c716..5268f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -14,3 +14,27 @@
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ puts("CPU : Altera SOCFPGA Platform\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
+defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+ return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 0000000..a820b1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/scan_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(&scan_manager_base->stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+ (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+ max_iter--;
+ if (max_iter > 0)
+ scanmgr_status = readl(&scan_manager_base->stat);
+ else
+ return 0;
+ }
+ return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+ * De-assert reinit if the IO scan chain is intended for HIO. In
+ * this, its the chain 3.
+ */
+ if (io_scan_chain_id == 3)
+ clrbits_le32(&freeze_controller_base->hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+ * Check if the scan chain engine is inactive and the
+ * WFIFO is empty before enabling the IO scan chain
+ */
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ return 1;
+
+ /*
+ * Enable IO Scan chain based on scan chain id
+ * Note: only one chain can be enabled at a time
+ */
+ setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+ /*
+ * Calculate number of iteration needed for full 128-bit (4 x32-bits)
+ * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+ */
+ io_program_iter = io_scan_chain_len_in_bits >>
+ IO_SCAN_CHAIN_128BIT_SHIFT;
+ io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+ IO_SCAN_CHAIN_128BIT_MASK;
+
+ /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
+ (TDI_TDO_MAX_PAYLOAD << TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+ /* Program IO scan chain in 128-bit iteration */
+ for (i = 0; i < io_program_iter; i++) {
+ /* write TDI_TDO packet header to scan manager */
+ writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte);
+
+ /* calculate array index. Multiply by 4 as write 4 x 32bits */
+ index = i * 4;
+
+ /* write 4 successive 32-bit IO scan chain data into WFIFO */
+ writel(iocsr_scan_chain[index],
+ &scan_manager_base->fifo_quad_byte);
+ writel(iocsr_scan_chain[index + 1],
+ &scan_manager_base->fifo_quad_byte);
+ writel(iocsr_scan_chain[index + 2],
+ &scan_manager_base->fifo_quad_byte);
+ writel(iocsr_scan_chain[index + 3],
+ &scan_manager_base->fifo_quad_byte);
+
+ /*
+ * Check if the scan chain engine has completed the
+ * IO scan chain data shifting
+ */
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ goto error;
+ }
+
+ /* Calculate array index for final TDI_TDO packet */
+ index = io_program_iter * 4;
+
+ /* Final TDI_TDO packet if any */
+ if (io_scan_chain_data_residual) {
+ /*
+ * Calculate number of quad bytes FIFO write
+ * needed for the final TDI_TDO packet
+ */
+ io_program_iter = io_scan_chain_data_residual >>
+ IO_SCAN_CHAIN_32BIT_SHIFT;
+
+ /*
+ * Construct TDI_TDO packet for remaining IO
+ * scan chain (2 bytes)
+ */
+ tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
+ ((io_scan_chain_data_residual - 1) <<
+ TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+ /*
+ * Program the last part of IO scan chain write TDI_TDO packet
+ * header (2 bytes) to scan manager
+ */
+ writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte);
+
+ for (i = 0; i < io_program_iter; i++) {
+ /*
+ * write remaining scan chain data into scan
+ * manager WFIFO with 4 bytes write
+ */
+ writel(iocsr_scan_chain[index + i],
+ &scan_manager_base->fifo_quad_byte);
+ }
+
+ index += io_program_iter;
+ residual = io_scan_chain_data_residual &
+ IO_SCAN_CHAIN_32BIT_MASK;
+
+ if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) {
+ /*
+ * write the last 4B scan chain data
+ * into scan manager WFIFO
+ */
+ writel(iocsr_scan_chain[index],
+ &scan_manager_base->fifo_quad_byte);
+ } else {
+ /*
+ * write the remaining 1 - 3 bytes scan chain
+ * data into scan manager WFIFO byte by byte
+ * to prevent JTAG engine shifting unused data
+ * from the FIFO and mistaken the data as a
+ * valid command (even though unused bits are
+ * set to 0, but just to prevent hardware
+ * glitch)
+ */
+ for (i = 0; i < residual; i += 8) {
+ writel(((iocsr_scan_chain[index] >> i)
+ & IO_SCAN_CHAIN_BYTE_MASK),
+ &scan_manager_base->fifo_single_byte);
+ }
+ }
+
+ /*
+ * Check if the scan chain engine has completed the
+ * IO scan chain data shifting
+ */
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ goto error;
+ }
+
+ /* Disable IO Scan chain when configuration done*/
+ clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+ return 0;
+
+error:
+ /* Disable IO Scan chain when error detected */
+ clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+ return 1;
+}
+
+int scan_mgr_configure_iocsr(void)
+{
+ int status = 0;
+
+ /* configure the IOCSR through scan chain */
+ status |= scan_mgr_io_scan_chain_prg(0,
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table);
+ status |= scan_mgr_io_scan_chain_prg(1,
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table);
+ status |= scan_mgr_io_scan_chain_prg(2,
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table);
+ status |= scan_mgr_io_scan_chain_prg(3,
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table);
+ return status;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 2ae88bb..4bed19d 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -121,6 +121,10 @@
/* reconfigure the PLLs */
cm_basic_init(&cm_default_cfg);
+ /* configure the IOCSR / IO buffer settings */
+ if (scan_mgr_configure_iocsr())
+ hang();
+
/* configure the pin muxing through system manager */
sysmgr_pinmux_init();
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index a96ecda..9dbcdf2 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,15 +12,14 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u64 memory_type)
{
- u64 *page_table = (u64 *)gd->arch.tlb_addr;
u64 value;
- value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
+ value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
- page_table[section] = value;
+ page_table[index] = value;
}
/* to activate the MMU we need to set up virtual memory */
@@ -28,10 +27,13 @@
{
int i, j, el;
bd_t *bd = gd->bd;
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
/* Setup an identity-mapping for all spaces */
- for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
- set_pgtable_section(i, MT_DEVICE_NGNRNE);
+ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
+ set_pgtable_section(page_table, i, i << SECTION_SHIFT,
+ MT_DEVICE_NGNRNE);
+ }
/* Setup an identity-mapping for all RAM space */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
@@ -39,38 +41,26 @@
ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
for (j = start >> SECTION_SHIFT;
j < end >> SECTION_SHIFT; j++) {
- set_pgtable_section(j, MT_NORMAL);
+ set_pgtable_section(page_table, j, j << SECTION_SHIFT,
+ MT_NORMAL);
}
}
/* load TTBR0 */
el = current_el();
if (el == 1) {
- asm volatile("msr ttbr0_el1, %0"
- : : "r" (gd->arch.tlb_addr) : "memory");
- asm volatile("msr tcr_el1, %0"
- : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
- : "memory");
- asm volatile("msr mair_el1, %0"
- : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+ TCR_FLAGS | TCR_EL1_IPS_BITS,
+ MEMORY_ATTRIBUTES);
} else if (el == 2) {
- asm volatile("msr ttbr0_el2, %0"
- : : "r" (gd->arch.tlb_addr) : "memory");
- asm volatile("msr tcr_el2, %0"
- : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
- : "memory");
- asm volatile("msr mair_el2, %0"
- : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+ TCR_FLAGS | TCR_EL2_IPS_BITS,
+ MEMORY_ATTRIBUTES);
} else {
- asm volatile("msr ttbr0_el3, %0"
- : : "r" (gd->arch.tlb_addr) : "memory");
- asm volatile("msr tcr_el3, %0"
- : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
- : "memory");
- asm volatile("msr mair_el3, %0"
- : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+ TCR_FLAGS | TCR_EL3_IPS_BITS,
+ MEMORY_ATTRIBUTES);
}
-
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
}
@@ -83,12 +73,17 @@
__asm_invalidate_dcache_all();
}
+void __weak flush_l3_cache(void)
+{
+}
+
/*
* Performs a clean & invalidation of the entire data cache at all levels
*/
void flush_dcache_all(void)
{
__asm_flush_dcache_all();
+ flush_l3_cache();
}
/*
@@ -221,7 +216,7 @@
* Enable dCache & iCache, whether cache is actually enabled
* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
*/
-void enable_caches(void)
+void __weak enable_caches(void)
{
icache_enable();
dcache_enable();
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
new file mode 100644
index 0000000..9249537
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2014, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += speed.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
new file mode 100644
index 0000000..cc47466
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -0,0 +1,10 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 3
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
+for example LS2085A.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
new file mode 100644
index 0000000..c129d03
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include "cpu.h"
+#include "speed.h"
+#include <fsl_mc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * To start MMU before DDR is available, we create MMU table in SRAM.
+ * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * levels of translation tables here to cover 40-bit address space.
+ * We use 4KB granule size, with 40 bits physical address, T0SZ=24
+ * Level 0 IA[39], table address @0
+ * Level 1 IA[31:30], table address @01000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000
+ */
+
+#define SECTION_SHIFT_L0 39UL
+#define SECTION_SHIFT_L1 30UL
+#define SECTION_SHIFT_L2 21UL
+#define BLOCK_SIZE_L0 0x8000000000UL
+#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
+#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
+#define CONFIG_SYS_IFC_BASE 0x30000000
+#define CONFIG_SYS_IFC_SIZE 0x10000000
+#define CONFIG_SYS_IFC_BASE2 0x500000000
+#define CONFIG_SYS_IFC_SIZE2 0x100000000
+#define TCR_EL2_PS_40BIT (2 << 16)
+#define LSCH3_VA_BITS (40)
+#define LSCH3_TCR (TCR_TG0_4K | \
+ TCR_EL2_PS_40BIT | \
+ TCR_SHARED_NON | \
+ TCR_ORGN_NC | \
+ TCR_IRGN_NC | \
+ TCR_T0SZ(LSCH3_VA_BITS))
+
+/*
+ * Final MMU
+ * Let's start from the same layout as early MMU and modify as needed.
+ * IFC regions will be cache-inhibit.
+ */
+#define FINAL_QBMAN_CACHED_MEM 0x818000000UL
+#define FINAL_QBMAN_CACHED_SIZE 0x4000000
+
+
+static inline void early_mmu_setup(void)
+{
+ int el;
+ u64 i;
+ u64 section_l1t0, section_l1t1, section_l2;
+ u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
+ u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
+ u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
+ u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+
+
+ level0_table[0] =
+ (u64)level1_table_0 | PMD_TYPE_TABLE;
+ level0_table[1] =
+ (u64)level1_table_1 | PMD_TYPE_TABLE;
+
+ /*
+ * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
+ * set level 1 table 1 to cache enabled, covering 512GB to 1TB
+ * set level 2 table to cache-inhibit, covering 0 to 1GB
+ */
+ section_l1t0 = 0;
+ section_l1t1 = BLOCK_SIZE_L0;
+ section_l2 = 0;
+ for (i = 0; i < 512; i++) {
+ set_pgtable_section(level1_table_0, i, section_l1t0,
+ MT_DEVICE_NGNRNE);
+ set_pgtable_section(level1_table_1, i, section_l1t1,
+ MT_NORMAL);
+ set_pgtable_section(level2_table, i, section_l2,
+ MT_DEVICE_NGNRNE);
+ section_l1t0 += BLOCK_SIZE_L1;
+ section_l1t1 += BLOCK_SIZE_L1;
+ section_l2 += BLOCK_SIZE_L2;
+ }
+
+ level1_table_0[0] =
+ (u64)level2_table | PMD_TYPE_TABLE;
+ level1_table_0[1] =
+ 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+ PMD_ATTRINDX(MT_DEVICE_NGNRNE);
+ level1_table_0[2] =
+ 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+ PMD_ATTRINDX(MT_NORMAL);
+ level1_table_0[3] =
+ 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+ PMD_ATTRINDX(MT_NORMAL);
+
+ /* Rewrite table to enable cache */
+ set_pgtable_section(level2_table,
+ CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
+ CONFIG_SYS_FSL_OCRAM_BASE,
+ MT_NORMAL);
+ for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
+ i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
+ >> SECTION_SHIFT_L2; i++) {
+ section_l2 = i << SECTION_SHIFT_L2;
+ set_pgtable_section(level2_table, i,
+ section_l2, MT_NORMAL);
+ }
+
+ el = current_el();
+ set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
+ set_sctlr(get_sctlr() | CR_M);
+}
+
+/*
+ * This final tale looks similar to early table, but different in detail.
+ * These tables are in regular memory. Cache on IFC is disabled. One sub table
+ * is added to enable cache for QBMan.
+ */
+static inline void final_mmu_setup(void)
+{
+ int el;
+ u64 i, tbl_base, tbl_limit, section_base;
+ u64 section_l1t0, section_l1t1, section_l2;
+ u64 *level0_table = (u64 *)gd->arch.tlb_addr;
+ u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
+ u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
+ u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
+ u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+
+
+ level0_table[0] =
+ (u64)level1_table_0 | PMD_TYPE_TABLE;
+ level0_table[1] =
+ (u64)level1_table_1 | PMD_TYPE_TABLE;
+
+ /*
+ * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
+ * set level 1 table 1 to cache enabled, covering 512GB to 1TB
+ * set level 2 table 0 to cache-inhibit, covering 0 to 1GB
+ */
+ section_l1t0 = 0;
+ section_l1t1 = BLOCK_SIZE_L0;
+ section_l2 = 0;
+ for (i = 0; i < 512; i++) {
+ set_pgtable_section(level1_table_0, i, section_l1t0,
+ MT_DEVICE_NGNRNE);
+ set_pgtable_section(level1_table_1, i, section_l1t1,
+ MT_NORMAL);
+ set_pgtable_section(level2_table_0, i, section_l2,
+ MT_DEVICE_NGNRNE);
+ section_l1t0 += BLOCK_SIZE_L1;
+ section_l1t1 += BLOCK_SIZE_L1;
+ section_l2 += BLOCK_SIZE_L2;
+ }
+
+ level1_table_0[0] =
+ (u64)level2_table_0 | PMD_TYPE_TABLE;
+ level1_table_0[2] =
+ 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+ PMD_ATTRINDX(MT_NORMAL);
+ level1_table_0[3] =
+ 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+ PMD_ATTRINDX(MT_NORMAL);
+
+ /* Rewrite table to enable cache */
+ set_pgtable_section(level2_table_0,
+ CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
+ CONFIG_SYS_FSL_OCRAM_BASE,
+ MT_NORMAL);
+
+ /*
+ * Fill in other part of tables if cache is needed
+ * If finer granularity than 1GB is needed, sub table
+ * should be created.
+ */
+ section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1);
+ i = section_base >> SECTION_SHIFT_L1;
+ level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE;
+ section_l2 = section_base;
+ for (i = 0; i < 512; i++) {
+ set_pgtable_section(level2_table_1, i, section_l2,
+ MT_DEVICE_NGNRNE);
+ section_l2 += BLOCK_SIZE_L2;
+ }
+ tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1);
+ tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) &
+ (BLOCK_SIZE_L1 - 1);
+ for (i = tbl_base >> SECTION_SHIFT_L2;
+ i < tbl_limit >> SECTION_SHIFT_L2; i++) {
+ section_l2 = section_base + (i << SECTION_SHIFT_L2);
+ set_pgtable_section(level2_table_1, i,
+ section_l2, MT_NORMAL);
+ }
+
+ /* flush new MMU table */
+ flush_dcache_range(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+
+ /* point TTBR to the new table */
+ el = current_el();
+ asm volatile("dsb sy");
+ if (el == 1) {
+ asm volatile("msr ttbr0_el1, %0"
+ : : "r" ((u64)level0_table) : "memory");
+ } else if (el == 2) {
+ asm volatile("msr ttbr0_el2, %0"
+ : : "r" ((u64)level0_table) : "memory");
+ } else if (el == 3) {
+ asm volatile("msr ttbr0_el3, %0"
+ : : "r" ((u64)level0_table) : "memory");
+ } else {
+ hang();
+ }
+ asm volatile("isb");
+
+ /*
+ * MMU is already enabled, just need to invalidate TLB to load the
+ * new table. The new table is compatible with the current table, if
+ * MMU somehow walks through the new table before invalidation TLB,
+ * it still works. So we don't need to turn off MMU here.
+ */
+}
+
+int arch_cpu_init(void)
+{
+ icache_enable();
+ __asm_invalidate_dcache_all();
+ __asm_invalidate_tlb_all();
+ early_mmu_setup();
+ set_sctlr(get_sctlr() | CR_C);
+ return 0;
+}
+
+/*
+ * flush_l3_cache
+ * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
+ * state, by writing to HP-F P-state request register.
+ * Fixme: This function should moved to a common file if other SoCs also use
+ * the same Dickens.
+ */
+#define HNF0_PSTATE_REQ 0x04200010
+#define HNF1_PSTATE_REQ 0x04210010
+#define HNF2_PSTATE_REQ 0x04220010
+#define HNF3_PSTATE_REQ 0x04230010
+#define HNF4_PSTATE_REQ 0x04240010
+#define HNF5_PSTATE_REQ 0x04250010
+#define HNF6_PSTATE_REQ 0x04260010
+#define HNF7_PSTATE_REQ 0x04270010
+#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
+#define HNFPSTAT_FAM 0x3
+#define HNFPSTAT_SFONLY 0x01
+
+static void hnf_pstate_req(u64 *ptr, u64 state)
+{
+ int timeout = 1000;
+ out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
+ ptr++;
+ /* checking if the transition is completed */
+ while (timeout > 0) {
+ if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
+ break;
+ udelay(100);
+ timeout--;
+ }
+}
+
+void flush_l3_cache(void)
+{
+ hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
+ hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
+ hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
+ hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
+ hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
+ hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
+ hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
+ hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
+ hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
+}
+
+/*
+ * This function is called from lib/board.c.
+ * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
+ * There is no need to disable d-cache for this operation.
+ */
+void enable_caches(void)
+{
+ final_mmu_setup();
+ __asm_invalidate_tlb_all();
+}
+#endif
+
+static inline u32 initiator_type(u32 cluster, int init_id)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
+ u32 type = in_le32(&gur->tp_ityp[idx]);
+
+ if (type & TP_ITYP_AV)
+ return type;
+
+ return 0;
+}
+
+u32 cpu_mask(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int i = 0, count = 0;
+ u32 cluster, type, mask = 0;
+
+ do {
+ int j;
+ cluster = in_le32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = initiator_type(cluster, j);
+ if (type) {
+ if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+ mask |= 1 << count;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+ return hweight32(cpu_mask());
+}
+
+int fsl_qoriq_core_to_cluster(unsigned int core)
+{
+ struct ccsr_gur __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int i = 0, count = 0;
+ u32 cluster;
+
+ do {
+ int j;
+ cluster = in_le32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ if (initiator_type(cluster, j)) {
+ if (count == core)
+ return i;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return -1; /* cannot identify the cluster */
+}
+
+u32 fsl_qoriq_core_to_type(unsigned int core)
+{
+ struct ccsr_gur __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ int i = 0, count = 0;
+ u32 cluster, type;
+
+ do {
+ int j;
+ cluster = in_le32(&gur->tp_cluster[i].lower);
+ for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+ type = initiator_type(cluster, j);
+ if (type) {
+ if (count == core)
+ return type;
+ count++;
+ }
+ }
+ i++;
+ } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+ return -1; /* cannot identify the cluster */
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ struct sys_info sysinfo;
+ char buf[32];
+ unsigned int i, core;
+ u32 type;
+
+ get_sys_info(&sysinfo);
+ puts("Clock Configuration:");
+ for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
+ if (!(i % 3))
+ puts("\n ");
+ type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
+ printf("CPU%d(%s):%-4s MHz ", core,
+ type == TY_ITYP_VER_A7 ? "A7 " :
+ (type == TY_ITYP_VER_A53 ? "A53" :
+ (type == TY_ITYP_VER_A57 ? "A57" : " ")),
+ strmhz(buf, sysinfo.freq_processor[core]));
+ }
+ printf("\n Bus: %-4s MHz ",
+ strmhz(buf, sysinfo.freq_systembus));
+ printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
+ puts("\n");
+
+ return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int error = 0;
+
+#ifdef CONFIG_FSL_MC_ENET
+ error = mc_init(bis);
+#endif
+ return error;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
new file mode 100644
index 0000000..28544d7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
new file mode 100644
index 0000000..ad32b6c
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Extracted from armv8/start.S
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+ /* Set the SMMU page size in the sACR register */
+ ldr x1, =SMMU_BASE
+ ldr w0, [x1, #0x10]
+ orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
+ str w0, [x1, #0x10]
+
+ /* Initialize GIC Secure Bank Status */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+ branch_if_slave x0, 1f
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+1:
+#ifdef CONFIG_GICV3
+ ldr x0, =GICR_BASE
+ bl gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+ ldr x0, =GICD_BASE
+ ldr x1, =GICC_BASE
+ bl gic_init_secure_percpu
+#endif
+#endif
+
+ branch_if_master x0, x1, 1f
+
+ /*
+ * Slave should wait for master clearing spin table.
+ * This sync prevent salves observing incorrect
+ * value of spin table and jumping to wrong place.
+ */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+ ldr x0, =GICC_BASE
+#endif
+ bl gic_wait_for_interrupt
+#endif
+
+ /*
+ * All processors will enter EL2 and optionally EL1.
+ */
+ bl armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ bl armv8_switch_to_el1
+#endif
+ b 2f
+
+1:
+2:
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
new file mode 100644
index 0000000..dc4a34b
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2014, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Derived from arch/power/cpu/mpc85xx/speed.c
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <fsl_ifc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/clock.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
+#endif
+
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
+ struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
+ (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
+ (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
+ };
+ struct ccsr_clk_ctrl __iomem *clk_ctrl =
+ (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[16] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+ [2] = 0, /* CC1 PPL / 4 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 1, /* CC2 PPL / 2 */
+ [6] = 1, /* CC2 PPL / 4 */
+ [8] = 2, /* CC3 PPL / 1 */
+ [9] = 2, /* CC3 PPL / 2 */
+ [10] = 2, /* CC3 PPL / 4 */
+ [12] = 3, /* CC4 PPL / 1 */
+ [13] = 3, /* CC4 PPL / 2 */
+ [14] = 3, /* CC4 PPL / 4 */
+ };
+
+ const u8 core_cplx_pll_div[16] = {
+ [0] = 1, /* CC1 PPL / 1 */
+ [1] = 2, /* CC1 PPL / 2 */
+ [2] = 4, /* CC1 PPL / 4 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 2, /* CC2 PPL / 2 */
+ [6] = 4, /* CC2 PPL / 4 */
+ [8] = 1, /* CC3 PPL / 1 */
+ [9] = 2, /* CC3 PPL / 2 */
+ [10] = 4, /* CC3 PPL / 4 */
+ [12] = 1, /* CC4 PPL / 1 */
+ [13] = 2, /* CC4 PPL / 2 */
+ [14] = 4, /* CC4 PPL / 4 */
+ };
+
+ uint i, cluster;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ u32 c_pll_sel, cplx_pll;
+ void *offset;
+
+ sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info->freq_ddrbus = sysclk;
+#endif
+
+ sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
+ sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+ /*
+ * fixme: prefer to combine the following into one line, but
+ * cannot pass compiling without warning about in_le32.
+ */
+ offset = (void *)((size_t)clk_grp[i/3] +
+ offsetof(struct ccsr_clk_cluster_group,
+ pllngsr[i%3].gsr));
+ ratio[i] = (in_le32(offset) >> 1) & 0x3f;
+ if (ratio[i] > 4)
+ freq_c_pll[i] = sysclk * ratio[i];
+ else
+ freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+ }
+
+ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+ cluster = fsl_qoriq_core_to_cluster(cpu);
+ c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
+ & 0xf;
+ cplx_pll = core_cplx_pll[c_pll_sel];
+ cplx_pll += cc_group[cluster] - 1;
+ sys_info->freq_processor[cpu] =
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+
+#if defined(CONFIG_FSL_IFC)
+ ccr = in_le32(&ifc_regs->ifc_ccr);
+ ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+ sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#endif
+}
+
+
+int get_clocks(void)
+{
+ struct sys_info sys_info;
+ get_sys_info(&sys_info);
+ gd->cpu_clk = sys_info.freq_processor[0];
+ gd->bus_clk = sys_info.freq_systembus;
+ gd->mem_clk = sys_info.freq_ddrbus;
+
+#if defined(CONFIG_FSL_ESDHC)
+ gd->arch.sdhc_clk = gd->bus_clk / 2;
+#endif /* defined(CONFIG_FSL_ESDHC) */
+
+ if (gd->cpu_clk != 0)
+ return 0;
+ else
+ return 1;
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq(ulong dummy)
+{
+ if (!gd->bus_clk)
+ get_clocks();
+
+ return gd->bus_clk;
+}
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq(ulong dummy)
+{
+ if (!gd->mem_clk)
+ get_clocks();
+
+ return gd->mem_clk;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_I2C_CLK:
+ return get_bus_freq(0) / 2;
+ default:
+ printf("Unsupported clock\n");
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h
new file mode 100644
index 0000000..15af5b9
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright 2014, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+void get_sys_info(struct sys_info *sys_info);
diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
index 9e7f2f3..330493b 100644
--- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h
+++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
@@ -1,6 +1,9 @@
/*
* Cirrus Logic EP93xx register definitions.
*
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
* Copyright (C) 2009
* Matthias Kaehlcke <matthias@kaehlcke.net>
*
@@ -287,6 +290,20 @@
#define SDRAM_DEVCFG_CASLAT_2 0x00010000
#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
+#define SDRAM_OFF_GLCONFIG 0x0004
+#define SDRAM_OFF_REFRSHTIMR 0x0008
+
+#define SDRAM_OFF_DEVCFG0 0x0010
+#define SDRAM_OFF_DEVCFG1 0x0014
+#define SDRAM_OFF_DEVCFG2 0x0018
+#define SDRAM_OFF_DEVCFG3 0x001C
+
+#define SDRAM_DEVCFG0_BASE 0xC0000000
+#define SDRAM_DEVCFG1_BASE 0xD0000000
+#define SDRAM_DEVCFG2_BASE 0xE0000000
+#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
+#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
+
#define GLCONFIG_INIT (1 << 0)
#define GLCONFIG_MRS (1 << 1)
#define GLCONFIG_SMEMBUSY (1 << 5)
@@ -295,6 +312,43 @@
#define GLCONFIG_CLKSHUTDOWN (1 << 30)
#define GLCONFIG_CKE (1 << 31)
+#define EP93XX_SDRAMCTRL 0x80060000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
+#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
+#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
+#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
+#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
+
+#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
+
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
+
+#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
+#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
+#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
+#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
+#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
+#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
+
/*
* 0x80070000 - 0x8007FFFF: Reserved
*/
@@ -324,6 +378,13 @@
};
#endif
+#define EP93XX_OFF_SMCBCR0 0x00
+#define EP93XX_OFF_SMCBCR1 0x04
+#define EP93XX_OFF_SMCBCR2 0x08
+#define EP93XX_OFF_SMCBCR3 0x0C
+#define EP93XX_OFF_SMCBCR6 0x18
+#define EP93XX_OFF_SMCBCR7 0x1C
+
#define SMC_BCR_IDCY_SHIFT 0
#define SMC_BCR_WST1_SHIFT 5
#define SMC_BCR_BLE (1 << 10)
@@ -445,6 +506,14 @@
};
#endif
+#define EP93XX_LED_DATA 0x80840020
+#define EP93XX_LED_GREEN_ON 0x0001
+#define EP93XX_LED_RED_ON 0x0002
+
+#define EP93XX_LED_DDR 0x80840024
+#define EP93XX_LED_GREEN_ENABLE 0x0001
+#define EP93XX_LED_RED_ENABLE 0x00020000
+
/*
* 0x80850000 - 0x8087FFFF: Reserved
*/
@@ -519,6 +588,9 @@
#define SYSCON_OFFSET 0x930000
#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
+/* Security */
+#define SECURITY_EXTENSIONID 0x80832714
+
#ifndef __ASSEMBLY__
struct syscon_regs {
uint32_t pwrsts;
@@ -553,7 +625,11 @@
#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
#endif
+#define SYSCON_OFF_CLKSET1 0x0020
+#define SYSCON_OFF_SYSCFG 0x009c
+
#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
+#define SYSCON_PWRCNT_USH_EN (1 << 28)
#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
@@ -571,6 +647,8 @@
#define SYSCON_CHIPID_REV_MASK 0xF0000000
#define SYSCON_DEVICECFG_SWRST (1 << 31)
+#define SYSCON_SYSCFG_LASDO 0x00000020
+
/*
* 0x80930000 - 0x8093FFFF: Watchdog Timer
*/
@@ -580,3 +658,10 @@
/*
* 0x80950000 - 0x9000FFFF: Reserved
*/
+
+/*
+ * During low_level init we store memory layout in memory at specific location
+ */
+#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
+#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
+#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-lsch3/clock.h
new file mode 100644
index 0000000..831af0b
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/clock.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_BUS_CLK,
+ MXC_UART_CLK,
+ MXC_ESDHC_CLK,
+ MXC_I2C_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
new file mode 100644
index 0000000..c1c718e
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
+#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
+
+#include <fsl_ddrc_version.h>
+
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
+#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
+#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
+#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
+#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
+ 0x18A0)
+
+#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
+#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
+#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
+#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x06000000
+#define GICR_BASE 0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_FSL_DDR_LE
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
+#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
+#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+
+
+/* IFC */
+#define CONFIG_SYS_FSL_IFC_LE
+
+#ifdef CONFIG_LS2085A
+#define CONFIG_MAX_CPUS 16
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
+#else
+#error SoC not defined
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
new file mode 100644
index 0000000..f23a78c
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
+#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
+#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
new file mode 100644
index 0000000..18e66bd
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -0,0 +1,116 @@
+/*
+ * LayerScape Internal Memory Map
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H
+#define __ARCH_FSL_LSCH3_IMMAP_H_
+
+/* This is chassis generation 3 */
+
+struct sys_info {
+ unsigned long freq_processor[CONFIG_MAX_CPUS];
+ unsigned long freq_systembus;
+ unsigned long freq_ddrbus;
+ unsigned long freq_localbus;
+ unsigned long freq_qe;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ unsigned long freq_qman;
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ unsigned long freq_pme;
+#endif
+};
+
+/* Global Utilities Block */
+struct ccsr_gur {
+ u32 porsr1; /* POR status 1 */
+ u32 porsr2; /* POR status 2 */
+ u8 res_008[0x20-0x8];
+ u32 gpporcr1; /* General-purpose POR configuration */
+ u32 gpporcr2; /* General-purpose POR configuration 2 */
+ u32 dcfg_fusesr; /* Fuse status register */
+ u32 gpporcr3;
+ u32 gpporcr4;
+ u8 res_034[0x70-0x34];
+ u32 devdisr; /* Device disable control */
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+ u32 devdisr5; /* Device disable control 5 */
+ u32 devdisr6; /* Device disable control 6 */
+ u32 devdisr7; /* Device disable control 7 */
+ u8 res_08c[0x90-0x8c];
+ u32 coredisru; /* uppper portion for support of 64 cores */
+ u32 coredisrl; /* lower portion for support of 64 cores */
+ u8 res_098[0xa0-0x98];
+ u32 pvr; /* Processor version */
+ u32 svr; /* System version */
+ u32 mvr; /* Manufacturing version */
+ u8 res_0ac[0x100-0xac];
+ u32 rcwsr[32]; /* Reset control word status */
+
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+ u8 res_180[0x200-0x180];
+ u32 scratchrw[32]; /* Scratch Read/Write */
+ u8 res_280[0x300-0x280];
+ u32 scratchw1r[4]; /* Scratch Read (Write once) */
+ u8 res_310[0x400-0x310];
+ u32 bootlocptrl; /* Boot location pointer low-order addr */
+ u32 bootlocptrh; /* Boot location pointer high-order addr */
+ u8 res_408[0x500-0x408];
+ u8 res_500[0x740-0x500]; /* add more registers when needed */
+ u32 tp_ityp[64]; /* Topology Initiator Type Register */
+ struct {
+ u32 upper;
+ u32 lower;
+ } tp_cluster[3]; /* Core Cluster n Topology Register */
+ u8 res_858[0x1000-0x858];
+};
+
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TY_ITYP_VER_A7 0x1
+#define TY_ITYP_VER_A53 0x2
+#define TY_ITYP_VER_A57 0x3
+
+#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+struct ccsr_clk_cluster_group {
+ struct {
+ u8 res_00[0x10];
+ u32 csr;
+ u8 res_14[0x20-0x14];
+ } hwncsr[3];
+ u8 res_60[0x80-0x60];
+ struct {
+ u32 gsr;
+ u8 res_84[0xa0-0x84];
+ } pllngsr[3];
+ u8 res_e0[0x100-0xe0];
+};
+
+struct ccsr_clk_ctrl {
+ struct {
+ u32 csr; /* core cluster n clock control status */
+ u8 res_04[0x20-0x04];
+ } clkcncsr[8];
+};
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
new file mode 100644
index 0000000..8f00535
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
+#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
+
+#define I2C_QUIRK_REG /* enable 8-bit driver */
+
+#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h
index 7012ea7..a7102d5 100644
--- a/arch/arm/include/asm/arch-keystone/spl.h
+++ b/arch/arm/include/asm/arch-keystone/spl.h
@@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_SPL_H_
+#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_SPI 2
diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h
new file mode 100644
index 0000000..f9be621
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SCAN_MANAGER_H_
+#define _SCAN_MANAGER_H_
+
+struct socfpga_scan_manager {
+ u32 stat;
+ u32 en;
+ u32 padding[2];
+ u32 fifo_single_byte;
+ u32 fifo_double_byte;
+ u32 fifo_quad_byte;
+};
+
+/*
+ * Shift count to get number of IO scan chain data in granularity
+ * of 128-bit ( N / 128 )
+ */
+#define IO_SCAN_CHAIN_128BIT_SHIFT 7
+
+/*
+ * Mask to get residual IO scan chain data in
+ * granularity of 128-bit ( N mod 128 )
+ */
+#define IO_SCAN_CHAIN_128BIT_MASK 0x7F
+
+/*
+ * Shift count to get number of IO scan chain
+ * data in granularity of 32-bit ( N / 32 )
+ */
+#define IO_SCAN_CHAIN_32BIT_SHIFT 5
+
+/*
+ * Mask to get residual IO scan chain data in
+ * granularity of 32-bit ( N mod 32 )
+ */
+#define IO_SCAN_CHAIN_32BIT_MASK 0x1F
+
+/* Byte mask */
+#define IO_SCAN_CHAIN_BYTE_MASK 0xFF
+
+/* 24-bits (3 bytes) IO scan chain payload definition */
+#define IO_SCAN_CHAIN_PAYLOAD_24BIT 24
+
+/*
+ * Maximum length of TDI_TDO packet payload is 128 bits,
+ * represented by (length - 1) in TDI_TDO header
+ */
+#define TDI_TDO_MAX_PAYLOAD 127
+
+/* TDI_TDO packet header for IO scan chain program */
+#define TDI_TDO_HEADER_FIRST_BYTE 0x80
+
+/* Position of second command byte for TDI_TDO packet */
+#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT 8
+
+/*
+ * Maximum polling loop to wait for IO scan chain engine
+ * becomes idle to prevent infinite loop
+ */
+#define SCAN_MAX_DELAY 100
+
+#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31)
+#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28)
+
+/*
+ * Program HPS IO Scan Chain
+ * io_scan_chain_id - IO scan chain ID
+ * io_scan_chain_len_in_bits - IO scan chain length in bits
+ * iocsr_scan_chain - IO scan chain table
+ */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain);
+
+extern const uint32_t iocsr_scan_chain0_table[
+ ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)];
+extern const uint32_t iocsr_scan_chain1_table[
+ ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)];
+extern const uint32_t iocsr_scan_chain2_table[
+ ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)];
+extern const uint32_t iocsr_scan_chain3_table[
+ ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)];
+
+#endif /* _SCAN_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f564046..5f73824 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -11,8 +11,10 @@
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index ff871bc..acbec46 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_SPL_H_
+#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 1193e76..4b7b67b 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -108,4 +108,28 @@
TCR_IRGN_WBWA | \
TCR_T0SZ(VA_BITS))
+#ifndef __ASSEMBLY__
+void set_pgtable_section(u64 *page_table, u64 index,
+ u64 section, u64 memory_type);
+static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
+{
+ asm volatile("dsb sy");
+ if (el == 1) {
+ asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
+ asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
+ asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
+ } else if (el == 2) {
+ asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
+ asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
+ asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
+ } else if (el == 3) {
+ asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
+ asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
+ asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
+ } else {
+ hang();
+ }
+ asm volatile("isb");
+}
+#endif
#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index ddebbc8..a836e9f 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -29,6 +29,9 @@
void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
+void arm_init_before_mmu(void);
+void arm_init_domains(void);
+void cpu_cache_initialization(void);
void dram_bank_mmu_setup(int bank);
#endif
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 2a20a77..d3433da 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -17,4 +17,8 @@
#define CONFIG_STATIC_RELA
#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch-fsl-lsch3/config.h>
+#endif
+
#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9f35fd6..214f3ea 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -70,10 +70,12 @@
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getq(a) (*(volatile unsigned long long *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v))
extern inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
@@ -123,10 +125,12 @@
#define __raw_writeb(v,a) __arch_putb(v,a)
#define __raw_writew(v,a) __arch_putw(v,a)
#define __raw_writel(v,a) __arch_putl(v,a)
+#define __raw_writeq(v,a) __arch_putq(v,a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
+#define __raw_readq(a) __arch_getq(a)
/*
* TODO: The kernel offers some more advanced versions of barriers, it might
@@ -139,10 +143,12 @@
#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
+#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; })
#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
/*
* The compiler seems to be incapable of optimising constants
@@ -168,9 +174,11 @@
#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
+#define out_le64(a,v) out_arch(q,le64,a,v)
#define out_le32(a,v) out_arch(l,le32,a,v)
#define out_le16(a,v) out_arch(w,le16,a,v)
+#define in_le64(a) in_arch(q,le64,a)
#define in_le32(a) in_arch(l,le32,a)
#define in_le16(a) in_arch(w,le16,a)
diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h
index 693d1f4..c61374e 100644
--- a/arch/arm/include/asm/proc-armv/system.h
+++ b/arch/arm/include/asm/proc-armv/system.h
@@ -22,7 +22,7 @@
#define local_irq_save(flags) \
({ \
asm volatile( \
- "mrs %0, daif" \
+ "mrs %0, daif\n" \
"msr daifset, #3" \
: "=r" (flags) \
: \
diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h
new file mode 100644
index 0000000..74111dc
--- /dev/null
+++ b/arch/arm/include/asm/semihosting.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2014 Broadcom Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SEMIHOSTING_H__
+#define __SEMIHOSTING_H__
+
+/*
+ * ARM semihosting functions for loading images to memory. See the source
+ * code for more information.
+ */
+int smh_load(const char *fname, void *memp, int avail, int verbose);
+int smh_read(int fd, void *memp, int len);
+int smh_open(const char *fname, char *modestr);
+int smh_close(int fd);
+int smh_len_fd(int fd);
+int smh_len(const char *fname);
+
+#endif /* __SEMIHOSTING_H__ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 74ee9a4..d51ba66 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -78,6 +78,8 @@
void wait_for_wakeup(void);
void smp_kick_all_cpus(void);
+void flush_l3_cache(void);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 585f1f7..1ef2400 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -32,6 +32,7 @@
else
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
endif
+obj-$(CONFIG_SEMIHOSTING) += semihosting.o
obj-y += sections.o
ifdef CONFIG_ARM64
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 8642010..5fdfdbf 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -14,11 +14,9 @@
DECLARE_GLOBAL_DATA_PTR;
-void __arm_init_before_mmu(void)
+__weak void arm_init_before_mmu(void)
{
}
-void arm_init_before_mmu(void)
- __attribute__((weak, alias("__arm_init_before_mmu")));
__weak void arm_init_domains(void)
{
@@ -44,14 +42,11 @@
page_table[section] = value;
}
-void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
debug("%s: Warning: not implemented\n", __func__);
}
-void mmu_page_table_flush(unsigned long start, unsigned long stop)
- __attribute__((weak, alias("__mmu_page_table_flush")));
-
void mmu_set_region_dcache_behaviour(u32 start, int size,
enum dcache_option option)
{
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 4f6b9f0..4e597a4 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -9,7 +9,7 @@
#include <common.h>
-void __flush_cache(unsigned long start, unsigned long size)
+__weak void flush_cache(unsigned long start, unsigned long size)
{
#if defined(CONFIG_ARM1136)
@@ -31,28 +31,21 @@
#endif /* CONFIG_ARM926EJS */
return;
}
-void flush_cache(unsigned long start, unsigned long size)
- __attribute__((weak, alias("__flush_cache")));
/*
* Default implementation:
* do a range flush for the entire range
*/
-void __flush_dcache_all(void)
+__weak void flush_dcache_all(void)
{
flush_cache(0, ~0);
}
-void flush_dcache_all(void)
- __attribute__((weak, alias("__flush_dcache_all")));
-
/*
* Default implementation of enable_caches()
* Real implementation should be in platform code
*/
-void __enable_caches(void)
+__weak void enable_caches(void)
{
puts("WARNING: Caches not enabled\n");
}
-void enable_caches(void)
- __attribute__((weak, alias("__enable_caches")));
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
new file mode 100644
index 0000000..cb5dc26
--- /dev/null
+++ b/arch/arm/lib/semihosting.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2014 Broadcom Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Minimal semihosting implementation for reading files into memory. If more
+ * features like writing files or console output are required they can be
+ * added later. This code has been tested on arm64/aarch64 fastmodel only.
+ * An untested placeholder exists for armv7 architectures, but since they
+ * are commonly available in silicon now, fastmodel usage makes less sense
+ * for them.
+ */
+#include <common.h>
+#include <asm/semihosting.h>
+
+#define SYSOPEN 0x01
+#define SYSCLOSE 0x02
+#define SYSREAD 0x06
+#define SYSFLEN 0x0C
+
+#define MODE_READ 0x0
+#define MODE_READBIN 0x1
+
+/*
+ * Call the handler
+ */
+static int smh_trap(unsigned int sysnum, void *addr)
+{
+ register int result asm("r0");
+#if defined(CONFIG_ARM64)
+ asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
+#else
+ /* Note - untested placeholder */
+ asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
+#endif
+ return result;
+}
+
+/*
+ * Open, load a file into memory, and close it. Check that the available space
+ * is sufficient to store the entire file. Return the bytes actually read from
+ * the file as seen by the read function. The verbose flag enables some extra
+ * printing of successful read status.
+ */
+int smh_load(const char *fname, void *memp, int avail, int verbose)
+{
+ int ret, fd, len;
+
+ ret = -1;
+
+ debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
+ avail, memp);
+
+ /* Open the file */
+ fd = smh_open(fname, "rb");
+ if (fd == -1)
+ return ret;
+
+ /* Get the file length */
+ ret = smh_len_fd(fd);
+ if (ret == -1) {
+ smh_close(fd);
+ return ret;
+ }
+
+ /* Check that the file will fit in the supplied buffer */
+ if (ret > avail) {
+ printf("%s: ERROR ret %d, avail %u\n", __func__, ret,
+ avail);
+ smh_close(fd);
+ return ret;
+ }
+
+ len = ret;
+
+ /* Read the file into the buffer */
+ ret = smh_read(fd, memp, len);
+ if (ret == 0) {
+ /* Print successful load information if requested */
+ if (verbose) {
+ printf("\n%s\n", fname);
+ printf(" 0x%8p dest\n", memp);
+ printf(" 0x%08x size\n", len);
+ printf(" 0x%08x avail\n", avail);
+ }
+ }
+
+ /* Close the file */
+ smh_close(fd);
+
+ return ret;
+}
+
+/*
+ * Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure
+ */
+int smh_read(int fd, void *memp, int len)
+{
+ int ret;
+ struct smh_read_s {
+ int fd;
+ void *memp;
+ int len;
+ } read;
+
+ debug("%s: fd %d, memp %p, len %d\n", __func__, fd, memp, len);
+
+ read.fd = fd;
+ read.memp = memp;
+ read.len = len;
+
+ ret = smh_trap(SYSREAD, &read);
+ if (ret == 0) {
+ return 0;
+ } else {
+ /*
+ * The ARM handler allows for returning partial lengths,
+ * but in practice this never happens so rather than create
+ * hard to maintain partial read loops and such, just fail
+ * with an error message.
+ */
+ printf("%s: ERROR ret %d, fd %d, len %u memp %p\n",
+ __func__, ret, fd, len, memp);
+ }
+ return ret;
+}
+
+/*
+ * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
+ * descriptor or -1 on error.
+ */
+int smh_open(const char *fname, char *modestr)
+{
+ int ret, fd, mode;
+ struct smh_open_s {
+ const char *fname;
+ unsigned int mode;
+ unsigned int len;
+ } open;
+
+ debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
+
+ ret = -1;
+
+ /* Check the file mode */
+ if (!(strcmp(modestr, "r"))) {
+ mode = MODE_READ;
+ } else if (!(strcmp(modestr, "rb"))) {
+ mode = MODE_READBIN;
+ } else {
+ printf("%s: ERROR mode \'%s\' not supported\n", __func__,
+ modestr);
+ return ret;
+ }
+
+ open.fname = fname;
+ open.len = strlen(fname);
+ open.mode = mode;
+
+ /* Open the file on the host */
+ fd = smh_trap(SYSOPEN, &open);
+ if (fd == -1)
+ printf("%s: ERROR fd %d for file \'%s\'\n", __func__, fd,
+ fname);
+
+ return fd;
+}
+
+/*
+ * Close the file using the file descriptor
+ */
+int smh_close(int fd)
+{
+ int ret;
+ long fdlong;
+
+ debug("%s: fd %d\n", __func__, fd);
+
+ fdlong = (long)fd;
+ ret = smh_trap(SYSCLOSE, &fdlong);
+ if (ret == -1)
+ printf("%s: ERROR fd %d\n", __func__, fd);
+
+ return ret;
+}
+
+/*
+ * Get the file length from the file descriptor
+ */
+int smh_len_fd(int fd)
+{
+ int ret;
+ long fdlong;
+
+ debug("%s: fd %d\n", __func__, fd);
+
+ fdlong = (long)fd;
+ ret = smh_trap(SYSFLEN, &fdlong);
+ if (ret == -1)
+ printf("%s: ERROR ret %d\n", __func__, ret);
+
+ return ret;
+}
+
+/*
+ * Get the file length from the filename
+ */
+int smh_len(const char *fname)
+{
+ int ret, fd, len;
+
+ debug("%s: file \'%s\'\n", __func__, fname);
+
+ /* Open the file */
+ fd = smh_open(fname, "rb");
+ if (fd == -1)
+ return fd;
+
+ /* Get the file length */
+ len = smh_len_fd(fd);
+
+ /* Close the file */
+ ret = smh_close(fd);
+ if (ret == -1)
+ return ret;
+
+ debug("%s: returning len %d\n", __func__, len);
+
+ /* Return the file length (or -1 error indication) */
+ return len;
+}
diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c
new file mode 100644
index 0000000..b4b5ff8
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.c
@@ -0,0 +1,657 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#include <iocsr_config.h>
+
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00020080,
+ 0x08020000,
+ 0x08000000,
+ 0x00018020,
+ 0x00000000,
+ 0x00004000,
+ 0x00010040,
+ 0x04010000,
+ 0x04000000,
+ 0x00000010,
+ 0x00004010,
+ 0x00002000,
+ 0x00020000,
+ 0x02008000,
+ 0x02000000,
+ 0x00000008,
+ 0x00002008,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x000C0300,
+ 0x10040000,
+ 0x100000C0,
+ 0x00000040,
+ 0x00010040,
+ 0x00008000,
+ 0x00080000,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x00010040,
+ 0x10000000,
+ 0x04000000,
+ 0x00000010,
+ 0x00004010,
+ 0x00002000,
+ 0x06008020,
+ 0x02008000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x00004010,
+ 0x01004000,
+ 0x01000000,
+ 0x00003004,
+ 0x00001004,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x00800000,
+ 0x00000002,
+ 0x00002000,
+ 0x00000400,
+ 0x00000000,
+ 0x00401000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00600802,
+ 0x00000000,
+ 0x80200000,
+ 0x80000600,
+ 0x00000200,
+ 0x00000100,
+ 0x00300401,
+ 0xC0100400,
+ 0x40100000,
+ 0x40000300,
+ 0x000C0100,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x80040100,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C010040,
+ 0x00008000,
+ 0x18020080,
+ 0x00000000,
+ 0x08000000,
+ 0x00040020,
+ 0x06018060,
+ 0x00004000,
+ 0x0C010040,
+ 0x04010000,
+ 0x00000030,
+ 0x00000000,
+ 0x03004010,
+ 0x00002000,
+ 0x06008020,
+ 0x02008000,
+ 0x02000018,
+ 0x00006008,
+ 0x01802008,
+ 0x00001000,
+ 0x03004010,
+ 0x01004000,
+ 0x0100000C,
+ 0x00003004,
+ 0x00C01004,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000070,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D0000,
+ 0x24906808,
+ 0x00A28340,
+ 0xD000001A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000070,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00040,
+ 0xA20D0002,
+ 0x24906808,
+ 0x00A28340,
+ 0xD005141A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x000001C1,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x04510680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x8341D348,
+ 0x821A0124,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x40120800,
+ 0x00000070,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x001A1A1A,
+ 0x085506A0,
+ 0x0000E1D4,
+ 0x045506A0,
+ 0x0000E1D4,
+ 0x085506A0,
+ 0x8000E1D4,
+ 0x00000200,
+ 0x00000004,
+ 0x04000000,
+ 0x00000009,
+ 0x00002410,
+ 0x00000040,
+ 0x41000000,
+ 0x00002082,
+ 0x00000350,
+ 0x000000DA,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x022A8350,
+ 0x000070EA,
+ 0x86000000,
+ 0x08000004,
+ 0x00000000,
+ 0x00482000,
+ 0x21800000,
+ 0x00101061,
+ 0x021541A8,
+ 0x00003875,
+ 0x011541A8,
+ 0x00003875,
+ 0x021541A8,
+ 0x20003875,
+ 0x00000080,
+ 0x00000001,
+ 0x41000000,
+ 0x00000002,
+ 0x00FF0904,
+ 0x00000000,
+ 0x90400000,
+ 0x00000820,
+ 0xC0000001,
+ 0x38D612AF,
+ 0x86F8E38E,
+ 0x0A0A78B4,
+ 0x000D020A,
+ 0x00006800,
+ 0x028A4320,
+ 0xEC2CB23D,
+ 0x8F5D1451,
+ 0xA47A88A2,
+ 0x0001A0E9,
+ 0x00410D00,
+ 0x40000068,
+ 0x3D000003,
+ 0x51EC2CB2,
+ 0xA28F5D14,
+ 0xE9A47A88,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000540,
+ 0x000003A8,
+ 0x08AA0D40,
+ 0x8001C3A8,
+ 0x0000007F,
+ 0x00000000,
+ 0x00004060,
+ 0xE1208000,
+ 0x0000001F,
+ 0x00004100,
+};
diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h
new file mode 100644
index 0000000..490f109
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_IOCSR_CONFIG_H_
+#define _PRELOADER_IOCSR_CONFIG_H_
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+
+#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index a960eb6..f366565 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,17 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_DISPLAY_CPUINFO)
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
- puts("CPU : Altera SOCFPGA Platform\n");
- return 0;
-}
-#endif
-
/*
* Print Board information
*/
@@ -48,18 +37,6 @@
icache_enable();
return 0;
}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
- return 0;
-}
-#endif
/*
* DesignWare Ethernet initialization
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 2ec3bc9..5897318 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -11,6 +11,7 @@
#include <netdev.h>
#include <asm/io.h>
#include <linux/compiler.h>
+#include <asm/semihosting.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -31,17 +32,107 @@
return 0;
}
-int timer_init(void)
-{
- return 0;
-}
-
/*
* Board specific reset that is system reset.
*/
void reset_cpu(ulong addr)
{
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SEMIHOSTING
+ /*
+ * Please refer to doc/README.semihosting for a more complete
+ * description.
+ *
+ * We require that the board include file defines these env variables:
+ * - kernel_name
+ * - kernel_addr_r
+ * - initrd_name
+ * - initrd_addr_r
+ * - fdt_name
+ * - fdt_addr_r
+ *
+ * For the "fdt chosen" startup macro, this code will then define:
+ * - initrd_end (based on initrd_addr_r plus actual initrd_size)
+ *
+ * We will then load the kernel, initrd, and fdt into the specified
+ * locations in memory in a similar way that the ATF fastmodel code
+ * uses semihosting calls to load other boot stages and u-boot itself.
+ */
+
+ /* Env variable strings */
+ char *kernel_name = getenv("kernel_name");
+ char *kernel_addr_str = getenv("kernel_addr_r");
+ char *initrd_name = getenv("initrd_name");
+ char *initrd_addr_str = getenv("initrd_addr_r");
+ char *fdt_name = getenv("fdt_name");
+ char *fdt_addr_str = getenv("fdt_addr_r");
+ char initrd_end_str[64];
+
+ /* Actual addresses converted from env variables */
+ void *kernel_addr_r;
+ void *initrd_addr_r;
+ void *fdt_addr_r;
+
+ /* Actual initrd base and size */
+ unsigned long initrd_base;
+ unsigned long initrd_size;
+
+ /* Space available */
+ int avail;
+
+ /* Make sure the environment variables needed are set */
+ if (!(kernel_addr_str && initrd_addr_str && fdt_addr_str)) {
+ printf("%s: Define {kernel/initrd/fdt}_addr_r\n", __func__);
+ return -1;
+ }
+ if (!(kernel_name && initrd_name && fdt_name)) {
+ printf("%s: Define {kernel/initrd/fdt}_name\n", __func__);
+ return -1;
+ }
+
+ /* Get exact initrd_size */
+ initrd_size = smh_len(initrd_name);
+ if (initrd_size == -1) {
+ printf("%s: Can't get file size for \'%s\'\n", __func__,
+ initrd_name);
+ return -1;
+ }
+
+ /* Set initrd_end */
+ initrd_base = simple_strtoul(initrd_addr_str, NULL, 16);
+ initrd_addr_r = (void *)initrd_base;
+ sprintf(initrd_end_str, "0x%lx", initrd_base + initrd_size - 1);
+ setenv("initrd_end", initrd_end_str);
+
+ /* Load kernel to memory */
+ fdt_addr_r = (void *)simple_strtoul(fdt_addr_str, NULL, 16);
+ kernel_addr_r = (void *)simple_strtoul(kernel_addr_str, NULL, 16);
+
+ /*
+ * The kernel must be lower in memory than fdt and loading the
+ * kernel must not trample the fdt or vice versa.
+ */
+ avail = fdt_addr_r - kernel_addr_r;
+ if (avail < 0) {
+ printf("%s: fdt must be after kernel\n", __func__);
+ return -1;
+ }
+ smh_load(kernel_name, kernel_addr_r, avail, 1);
+
+ /* Load fdt to memory */
+ smh_load(fdt_name, fdt_addr_r, 0x20000, 1);
+
+ /* Load initrd to memory */
+ smh_load(initrd_name, initrd_addr_r, initrd_size, 1);
+
+#endif /* CONFIG_SEMIHOSTING */
+ return 0;
}
+#endif /* CONFIG_BOARD_LATE_INIT */
/*
* Board specific ethernet initialization routine.
diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile
new file mode 100644
index 0000000..d03c498
--- /dev/null
+++ b/board/cirrus/edb93xx/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2013
+# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# * SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := edb93xx.o
diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c
new file mode 100644
index 0000000..8963d3a
--- /dev/null
+++ b/board/cirrus/edb93xx/edb93xx.c
@@ -0,0 +1,382 @@
+/*
+ * Board initialization for EP93xx
+ *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias <at> kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson <at> netaudiotech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+ SYSCON_CLKSET2_PLL2_EN | \
+ SYSCON_CLKSET2_NBYP2 | \
+ 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
+
+#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+ 1 << SMC_BCR_MW_SHIFT)
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+ /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+ register uint32_t loops = (usecs * 1000) / 20;
+
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+#ifndef CONFIG_EP93XX_NO_FLASH_CFG
+static void flash_cfg(void)
+{
+ struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+ writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
+#else
+#define flash_cfg()
+#endif
+
+int board_init(void)
+{
+ /*
+ * Setup PLL2, PPL1 has been set during lowlevel init
+ */
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ writel(CLKSET2_VAL, &syscon->clkset2);
+
+ /*
+ * the user's guide recommends to wait at least 1 ms for PLL2 to
+ * stabilize
+ */
+ early_udelay(1000);
+
+ /* Go to Async mode */
+ __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
+ __asm__ volatile ("orr r0, r0, #0xc0000000");
+ __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ enable_interrupts();
+
+ flash_cfg();
+
+ green_led_on();
+ red_led_off();
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+ * 14.7456/2 MHz
+ */
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
+ unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
+{
+ if (dram_bank_cnt == 1) {
+ dram_bank_base[0] = PHYS_SDRAM_1;
+ } else {
+ /* Table lookup for holes in address space. Maximum memory
+ * for the single SDCS may be up to 256Mb. We start scanning
+ * banks from 1Mb, so it could be up to 128 banks theoretically.
+ * We need at maximum 7 bits for the loockup, 8 slots is
+ * enough for the worst case.
+ */
+ unsigned tbl[8];
+ unsigned i = dram_bank_cnt / 2;
+ unsigned j = 0x00100000; /* 1 Mb */
+ unsigned *ptbl = tbl;
+ do {
+ while (!(dram_addr_mask & j)) {
+ j <<= 1;
+ }
+ *ptbl++ = j;
+ j <<= 1;
+ i >>= 1;
+ } while (i != 0);
+
+ for (i = dram_bank_cnt, j = 0;
+ (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
+ unsigned addr = PHYS_SDRAM_1;
+ unsigned k;
+ unsigned bit;
+
+ for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
+ if (bit & j)
+ addr |= tbl[k];
+ }
+
+ dram_bank_base[j] = addr;
+ }
+ }
+}
+
+/* called in board_init_f (before relocation) */
+static unsigned dram_init_banksize_int(int print)
+{
+ /*
+ * Collect information of banks that has been filled during lowlevel
+ * initialization
+ */
+ unsigned i;
+ unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
+ unsigned dram_total = 0;
+ unsigned dram_bank_size = *(unsigned *)
+ (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
+ unsigned dram_addr_mask = *(unsigned *)
+ (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
+ unsigned dram_bank_cnt = *(unsigned *)
+ (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
+
+ dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
+
+ for (i = 0; i < dram_bank_cnt; i++) {
+ gd->bd->bi_dram[i].start = dram_bank_base[i];
+ gd->bd->bi_dram[i].size = dram_bank_size;
+ dram_total += dram_bank_size;
+ }
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ if (print) {
+ printf("DRAM mask: %08x\n", dram_addr_mask);
+ printf("DRAM total %u banks:\n", dram_bank_cnt);
+ printf("bank base-address size\n");
+
+ if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
+ printf("WARNING! UBoot was configured for %u banks,\n"
+ "but %u has been found. "
+ "Supressing extra memory banks\n",
+ CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
+ dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
+ }
+
+ for (i = 0; i < dram_bank_cnt; i++) {
+ printf(" %u %08x %08x\n",
+ i, dram_bank_base[i], dram_bank_size);
+ }
+ printf(" ------------------------------------------\n"
+ "Total %9d\n\n",
+ dram_total);
+ }
+
+ return dram_total;
+}
+
+void dram_init_banksize(void)
+{
+ dram_init_banksize_int(0);
+}
+
+/* called in board_init_f (before relocation) */
+int dram_init(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ unsigned sec_id = readl(SECURITY_EXTENSIONID);
+ unsigned chip_id = readl(&syscon->chipid);
+
+ printf("CPU: Cirrus Logic ");
+ switch (sec_id & 0x000001FE) {
+ case 0x00000008:
+ printf("EP9301");
+ break;
+ case 0x00000004:
+ printf("EP9307");
+ break;
+ case 0x00000002:
+ printf("EP931x");
+ break;
+ case 0x00000000:
+ printf("EP9315");
+ break;
+ default:
+ printf("<unknown>");
+ break;
+ }
+
+ printf(" - Rev. ");
+ switch (chip_id & 0xF0000000) {
+ case 0x00000000:
+ printf("A");
+ break;
+ case 0x10000000:
+ printf("B");
+ break;
+ case 0x20000000:
+ printf("C");
+ break;
+ case 0x30000000:
+ printf("D0");
+ break;
+ case 0x40000000:
+ printf("D1");
+ break;
+ case 0x50000000:
+ printf("E0");
+ break;
+ case 0x60000000:
+ printf("E1");
+ break;
+ case 0x70000000:
+ printf("E2");
+ break;
+ default:
+ printf("?");
+ break;
+ }
+ printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
+
+ gd->ram_size = dram_init_banksize_int(1);
+ return 0;
+}
+
+
+#ifdef CONFIG_EP93XX_SPI
+#include <spi.h>
+
+/*
+ * EGIO0-EGIPO7 -> port A
+ * EGIO8-EGIP15 -> port B
+ */
+
+static void ep93xx_set_epgio(unsigned num)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+ if (num < 8)
+ writel(readl(®s->padr) | (1<<num), ®s->padr);
+ else
+ writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr);
+}
+
+static void ep93xx_clear_epgio(unsigned num)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+ if (num < 8)
+ writel(readl(®s->padr) & (~(1<<num)), ®s->padr);
+ else
+ writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr);
+}
+
+static void ep93xx_dir_epgio_out(unsigned num)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+ if (num < 8)
+ writel(readl(®s->paddr) | (1<<num), ®s->paddr);
+ else
+ writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus == 0 && cs < 16)
+ return 1;
+
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ ep93xx_clear_epgio(slave->cs);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ ep93xx_set_epgio(slave->cs);
+}
+
+#ifdef CONFIG_MMC_SPI
+#include <mmc.h>
+
+#ifndef CONFIG_MMC_SPI_CS_EPGIO
+# define CONFIG_MMC_SPI_CS_EPGIO 4
+#endif
+
+#ifndef CONFIG_MMC_SPI_SPEED
+# define CONFIG_MMC_SPI_SPEED 25000000
+#endif
+
+#ifndef CONFIG_MMC_SPI_MODE
+# define CONFIG_MMC_SPI_MODE SPI_MODE_0
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+
+ ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
+ ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
+
+#ifdef CONFIG_MMC_SPI_POWER_EGPIO
+ ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
+ ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
+#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
+ ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
+ ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
+#endif
+ struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
+ CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
+
+ if (!mmc) {
+ printf("Failed to create MMC Device\n");
+ return 1;
+ }
+ mmc_init(mmc);
+ return 0;
+}
+
+
+#endif /* CONFIG_MMC_SPI */
+#endif /* CONFIG_EP93XX_SPI */
diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds
new file mode 100644
index 0000000..b0d892a
--- /dev/null
+++ b/board/cirrus/edb93xx/u-boot.lds
@@ -0,0 +1,115 @@
+/*
+ *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text : {
+ *(.__image_copy_start)
+ arch/arm/cpu/arm920t/start.o (.text*)
+ . = 0x1000;
+
+ LONG(0x53555243)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+ .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
+}
diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile
new file mode 100644
index 0000000..701b35c
--- /dev/null
+++ b/board/freescale/ls2085a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2085a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README
new file mode 100644
index 0000000..b7023e1
--- /dev/null
+++ b/board/freescale/ls2085a/README
@@ -0,0 +1,16 @@
+Freescale ls2085a_emu
+
+This is a emulator target with limited peripherals.
+
+Memory map from core's view
+
+0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c
new file mode 100644
index 0000000..257bc16
--- /dev/null
+++ b/board/freescale/ls2085a/ddr.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 3) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 1073741824u,
+ .capacity = 2147483648,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 937,
+ .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
+ .taa_ps = 13090,
+ .twr_ps = 15000,
+ .trcd_ps = 13090,
+ .trrd_ps = 5000,
+ .trp_ps = 13090,
+ .tras_ps = 33000,
+ .trc_ps = 46090,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 25000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing DDR....");
+
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+}
diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2085a/ddr.h
new file mode 100644
index 0000000..77f6aaf
--- /dev/null
+++ b/board/freescale/ls2085a/ddr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 2140, 0, 4, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 2140, 0, 5, 4, 0x0, 0x0},
+ {2, 2140, 0, 5, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
new file mode 100644
index 0000000..a18db1d7
--- /dev/null
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_mc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ init_final_memctl_regs();
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ init_early_memctl_regs(); /* tighten IFC timing */
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ printf("DRAM: ");
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+
+ out_le32(cltbenr, 0x1); /* enable cluster0 timebase */
+ out_le32(cntcr, 0x1); /* enable clock for timer */
+
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int error = 0;
+
+#ifdef CONFIG_SMC91111
+ error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+ error = cpu_eth_init(bis);
+#endif
+ return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+ if (get_mc_boot_status() == 0)
+ fdt_status_okay(fdt, offset);
+ else
+ fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_board_enet(blob);
+#endif
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 8e2db82..6f8d168 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -44,10 +44,14 @@
###########################################################################################################
Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
+Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a_semi vexpress_aemv8a:ARM64,SEMIHOSTING,BASE_FVP Steve Rae <srae@broadcom.com>
+Active aarch64 armv8 fsl-lsch3 freescale ls2085a ls2085a_emu ls2085a_emu:ARM64,EMU York Sun <yorksun@freescale.com>
+Active aarch64 armv8 fsl-lsch3 freescale ls2085a ls2085a_emu_D4 ls2085a_emu:ARM64,EMU,SYS_FSL_DDR4 York Sun <yorksun@freescale.com>
+Active aarch64 armv8 fsl-lsch3 freescale ls2085a ls2085a_simu ls2085a_simu:ARM64,SIMU York Sun <yorksun@freescale.com>
+Active arc arc700 - abilis - tb100 - Alexey Brodkin <abrodkin@synopsys.com>
Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
-Active arc arc700 - abilis - tb100 - Alexey Brodkin <abrodkin@synopsys.com>
Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
Active arm arm1136 mx31 - - imx31_phycore - -
Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
@@ -69,6 +73,7 @@
Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard <eric@eukrea.com>
Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
+Active arm arm920t ep93xx cirrus edb93xx edb9315a edb93xx:MK_edb9315a Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
Active arm arm920t ks8695 - - cm41xx - -
@@ -101,8 +106,8 @@
Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net>
Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net>
-Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com>
Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_mmc at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_MMC Bo Shen<voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com>
Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com>
Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com>
Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com>
@@ -209,7 +214,7 @@
Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm926ejs mxs freescale mx28evk mx28evk_spi mx28evk:ENV_IS_IN_SPI_FLASH Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs freescale mx28evk mx28evk_spi mx28evk:ENV_IS_IN_SPI_FLASH Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com>
Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de>
Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
@@ -288,8 +293,8 @@
Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
-Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
Active arm armv7 exynos samsung smdk5420 peach-pit - Akshay Saraswat <akshay.s@samsung.com>
+Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
@@ -321,12 +326,12 @@
Active arm armv7 mx6 embest mx6boards marsboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH Eric Bénard <eric@eukrea.com>
Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric@eukrea.com>
Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
+Active arm armv7 mx6 freescale mx6qsabreauto mx6dlsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 freescale mx6qsabreauto mx6dlsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
diff --git a/doc/README.semihosting b/doc/README.semihosting
new file mode 100644
index 0000000..7248560
--- /dev/null
+++ b/doc/README.semihosting
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Semihosting is ARM's way of having a real or virtual target communicate
+with a host or host debugger for basic operations such as file I/O,
+console I/O, etc. Please see
+http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjjgij.html for more information.
+
+For developing on armv8 virtual fastmodel platforms, semihosting is a
+valuable tool since it allows access to image/configuration files before
+eMMC or other NV media are available.
+
+There are two main ARM virtual Fixed Virtual Platform (FVP) models,
+Versatile Express (VE) FVP and BASE FVP (See
+http://www.arm.com/products/tools/models/fast-models/foundation-model.php)
+The initial vexpress64 u-boot board created here runs on the VE virtual
+platform using the license-free Foundation_v8 simulator. Fortunately,
+the Foundation_v8 simulator also supports the BASE_FVP model which
+companies can purchase licenses for and contain much more functionality.
+So we can, in u-boot, run either model by either using the VE FVP (default),
+or turning on CONFIG_BASE_FVP for the more full featured model.
+
+Rather than create a new armv8 board similar to armltd/vexpress64, add
+semihosting calls to the existing one, enabled with CONFIG_SEMIHOSTING
+and CONFIG_BASE_FVP both set. Also reuse the existing board config file
+vexpress_aemv8a.h but differentiate the two models by the presence or
+absence of CONFIG_BASE_FVP. This change is tested and works on both the
+Foundation and Base fastmodel simulators.
+
+The level of semihosting support is minimal, restricted to just what it
+takes to load images to memory. If more semihosting functionality is
+required, such as file seek, outputting strings, reading characters, etc,
+then it can be easily added later.
+
+We require that the board include file define these env variables:
+- kernel_name e.g. "uImage"
+- kernel_addr_r e.g. "0x80000000"
+- initrd_name e.g. "ramdisk.img"
+- initrd_addr_r e.g. "0x88000000"
+- fdt_name e.g. "devtree.dtb"
+- fdt_addr_r e.g. "0x83000000"
+
+Optionally, "fdt_high" and "initrd_high" can be specified as per
+their rules for allowing or preventing copying of these images.
+
+For the "fdt chosen" startup macro, this code will then define:
+- initrd_end (based on retrieving initrd_addr_r plus actual initrd_size)
+
+We will then load the kernel, initrd, and fdt into the specified
+locations in memory in a similar way that the ATF fastmodel code
+uses semihosting calls to load other boot stages and u-boot itself.
diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
index 367b670..6fb4117 100644
--- a/drivers/gpio/spear_gpio.c
+++ b/drivers/gpio/spear_gpio.c
@@ -36,7 +36,10 @@
{
struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
- writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
+ if (value)
+ writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
+ else
+ writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
return 0;
}
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..c14797c 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -429,6 +429,11 @@
(void *)I2C3_BASE_ADDR
#elif defined(CONFIG_VF610)
(void *)I2C0_BASE_ADDR
+#elif defined(CONFIG_FSL_LSCH3)
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+ (void *)I2C3_BASE_ADDR,
+ (void *)I2C4_BASE_ADDR
#else
#error "architecture not supported"
#endif
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6005f7e..6226cb2 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -64,3 +64,4 @@
obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
+obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/
diff --git a/drivers/net/fsl_mc/Makefile b/drivers/net/fsl_mc/Makefile
new file mode 100644
index 0000000..4834086
--- /dev/null
+++ b/drivers/net/fsl_mc/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Layerscape MC driver
+obj-y += mc.o
diff --git a/drivers/net/fsl_mc/mc.c b/drivers/net/fsl_mc/mc.c
new file mode 100644
index 0000000..df84568
--- /dev/null
+++ b/drivers/net/fsl_mc/mc.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <errno.h>
+#include <asm/io.h>
+#include <fsl_mc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+static int mc_boot_status;
+
+/**
+ * Copying MC firmware or DPL image to DDR
+ */
+static int mc_copy_image(const char *title,
+ u64 image_addr, u32 image_size, u64 mc_ram_addr)
+{
+ debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
+ memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
+ return 0;
+}
+
+/**
+ * MC firmware FIT image parser checks if the image is in FIT
+ * format, verifies integrity of the image and calculates
+ * raw image address and size values.
+ * Returns 0 if success and 1 if any of the above mentioned
+ * task fail.
+ **/
+
+int parse_mc_firmware_fit_image(const void **raw_image_addr,
+ size_t *raw_image_size)
+{
+ int format;
+ void *fit_hdr;
+ int node_offset;
+ const void *data;
+ size_t size;
+ const char *uname = "firmware";
+
+ /* Check if the image is in NOR flash*/
+#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
+ fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
+#endif
+
+ /* Check if Image is in FIT format */
+ format = genimg_get_format(fit_hdr);
+
+ if (format != IMAGE_FORMAT_FIT) {
+ debug("Not a FIT image\n");
+ return 1;
+ }
+
+ if (!fit_check_format(fit_hdr)) {
+ debug("Bad FIT image format\n");
+ return 1;
+ }
+
+ node_offset = fit_image_get_node(fit_hdr, uname);
+
+ if (node_offset < 0) {
+ debug("Can not find %s subimage\n", uname);
+ return 1;
+ }
+
+ /* Verify MC firmware image */
+ if (!(fit_image_verify(fit_hdr, node_offset))) {
+ debug("Bad MC firmware hash");
+ return 1;
+ }
+
+ /* Get address and size of raw image */
+ fit_image_get_data(fit_hdr, node_offset, &data, &size);
+
+ *raw_image_addr = data;
+ *raw_image_size = size;
+
+ return 0;
+}
+
+int mc_init(bd_t *bis)
+{
+ int error = 0;
+ int timeout = 200000;
+ struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+ u64 mc_ram_addr;
+ u64 mc_dpl_offset;
+ u32 reg_gsr;
+ u32 mc_fw_boot_status;
+ void *fdt_hdr;
+ int dpl_size;
+ const void *raw_image_addr;
+ size_t raw_image_size = 0;
+
+ BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0);
+
+ /*
+ * The MC private DRAM block was already carved at the end of DRAM
+ * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
+ */
+ if (gd->bd->bi_dram[1].start) {
+ mc_ram_addr =
+ gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
+ } else {
+ mc_ram_addr =
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+ }
+
+ /*
+ * Management Complex cores should be held at reset out of POR.
+ * U-boot should be the first software to touch MC. To be safe,
+ * we reset all cores again by setting GCR1 to 0. It doesn't do
+ * anything if they are held at reset. After we setup the firmware
+ * we kick off MC by deasserting the reset bit for core 0, and
+ * deasserting the reset bits for Command Portal Managers.
+ * The stop bits are not touched here. They are used to stop the
+ * cores when they are active. Setting stop bits doesn't stop the
+ * cores from fetching instructions when they are released from
+ * reset.
+ */
+ out_le32(&mc_ccsr_regs->reg_gcr1, 0);
+ dmb();
+
+ error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
+ if (error != 0)
+ goto out;
+ /*
+ * Load the MC FW at the beginning of the MC private DRAM block:
+ */
+ mc_copy_image(
+ "MC Firmware",
+ (u64)raw_image_addr,
+ raw_image_size,
+ mc_ram_addr);
+
+ /*
+ * Calculate offset in the MC private DRAM block at which the MC DPL
+ * blob is to be placed:
+ */
+#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
+ BUILD_BUG_ON(
+ (CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+ CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+
+ mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+#else
+ mc_dpl_offset = mc_get_dram_block_size() -
+ roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096);
+
+ if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) {
+ printf("%s: Invalid MC DPL offset: %llu\n",
+ __func__, mc_dpl_offset);
+ error = -EINVAL;
+ goto out;
+ }
+#endif
+
+ /* Check if DPL image is in NOR flash */
+#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
+ fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
+#endif
+
+ dpl_size = fdt_totalsize(fdt_hdr);
+
+ /*
+ * Load the MC DPL blob at the far end of the MC private DRAM block:
+ */
+ mc_copy_image(
+ "MC DPL blob",
+ (u64)fdt_hdr,
+ dpl_size,
+ mc_ram_addr + mc_dpl_offset);
+
+ debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
+
+ /*
+ * Tell MC where the MC Firmware image was loaded in DDR:
+ */
+ out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr);
+ out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32));
+ out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
+
+ /*
+ * Tell MC where the DPL blob was loaded in DDR, by indicating
+ * its offset relative to the beginning of the DDR block
+ * allocated to the MC firmware. The MC firmware is responsible
+ * for checking that there is no overlap between the DPL blob
+ * and the runtime heap and stack of the MC firmware itself.
+ *
+ * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of
+ * the GSR MC CCSR register. So, this offset is assumed to be 4-byte
+ * aligned.
+ * Care must be taken not to write 1s into bits 31 and 30 of the GSR in
+ * this case as the SoC COP or PIC will be signaled.
+ */
+ out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2));
+
+ /*
+ * Deassert reset and release MC core 0 to run
+ */
+ out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
+ dmb();
+ debug("Polling mc_ccsr_regs->reg_gsr ...\n");
+
+ for (;;) {
+ reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
+ mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
+ if (mc_fw_boot_status & 0x1)
+ break;
+
+ udelay(1000); /* throttle polling */
+ if (timeout-- <= 0)
+ break;
+ }
+
+ if (timeout <= 0) {
+ printf("%s: timeout booting management complex firmware\n",
+ __func__);
+
+ /* TODO: Get an error status from an MC CCSR register */
+ error = -ETIMEDOUT;
+ goto out;
+ }
+
+ printf("Management complex booted (boot status: %#x)\n",
+ mc_fw_boot_status);
+
+ if (mc_fw_boot_status != 0x1) {
+ /*
+ * TODO: Identify critical errors from the GSR register's FS
+ * field and for those errors, set error to -ENODEV or other
+ * appropriate errno, so that the status property is set to
+ * failure in the fsl,dprc device tree node.
+ */
+ }
+
+out:
+ if (error != 0)
+ mc_boot_status = -error;
+ else
+ mc_boot_status = 0;
+
+ return error;
+}
+
+int get_mc_boot_status(void)
+{
+ return mc_boot_status;
+}
+
+/**
+ * Return the actual size of the MC private DRAM block.
+ *
+ * NOTE: For now this function always returns the minimum required size,
+ * However, in the future, the actual size may be obtained from an environment
+ * variable.
+ */
+unsigned long mc_get_dram_block_size(void)
+{
+ return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+}
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b587308..f02c35a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -8,6 +8,7 @@
# There are many options which enable SPI, so make this library available
obj-y += spi.o
+obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ANDES_SPI) += andes_spi.o
obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c
new file mode 100644
index 0000000..235557e
--- /dev/null
+++ b/drivers/spi/ep93xx_spi.c
@@ -0,0 +1,274 @@
+/*
+ * SPI Driver for EP93xx
+ *
+ * Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Inspired form linux kernel driver and atmel uboot driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/ep93xx.h>
+
+
+#define BIT(x) (1<<(x))
+#define SSPBASE SPI_BASE
+
+#define SSPCR0 0x0000
+#define SSPCR0_MODE_SHIFT 6
+#define SSPCR0_SCR_SHIFT 8
+#define SSPCR0_SPH BIT(7)
+#define SSPCR0_SPO BIT(6)
+#define SSPCR0_FRF_SPI 0
+#define SSPCR0_DSS_8BIT 7
+
+#define SSPCR1 0x0004
+#define SSPCR1_RIE BIT(0)
+#define SSPCR1_TIE BIT(1)
+#define SSPCR1_RORIE BIT(2)
+#define SSPCR1_LBM BIT(3)
+#define SSPCR1_SSE BIT(4)
+#define SSPCR1_MS BIT(5)
+#define SSPCR1_SOD BIT(6)
+
+#define SSPDR 0x0008
+
+#define SSPSR 0x000c
+#define SSPSR_TFE BIT(0)
+#define SSPSR_TNF BIT(1)
+#define SSPSR_RNE BIT(2)
+#define SSPSR_RFF BIT(3)
+#define SSPSR_BSY BIT(4)
+#define SSPCPSR 0x0010
+
+#define SSPIIR 0x0014
+#define SSPIIR_RIS BIT(0)
+#define SSPIIR_TIS BIT(1)
+#define SSPIIR_RORIS BIT(2)
+#define SSPICR SSPIIR
+
+#define SSPCLOCK 14745600
+#define SSP_MAX_RATE (SSPCLOCK / 2)
+#define SSP_MIN_RATE (SSPCLOCK / (254 * 256))
+
+/* timeout in milliseconds */
+#define SPI_TIMEOUT 5
+/* maximum depth of RX/TX FIFO */
+#define SPI_FIFO_SIZE 8
+
+struct ep93xx_spi_slave {
+ struct spi_slave slave;
+
+ unsigned sspcr0;
+ unsigned sspcpsr;
+};
+
+static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct ep93xx_spi_slave, slave);
+}
+
+void spi_init()
+{
+}
+
+static inline void ep93xx_spi_write_u8(u16 reg, u8 value)
+{
+ writel(value, (unsigned int *)(SSPBASE + reg));
+}
+
+static inline u8 ep93xx_spi_read_u8(u16 reg)
+{
+ return readl((unsigned int *)(SSPBASE + reg));
+}
+
+static inline void ep93xx_spi_write_u16(u16 reg, u16 value)
+{
+ writel(value, (unsigned int *)(SSPBASE + reg));
+}
+
+static inline u16 ep93xx_spi_read_u16(u16 reg)
+{
+ return (u16)readl((unsigned int *)(SSPBASE + reg));
+}
+
+static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode,
+ struct ep93xx_spi_slave *slave)
+{
+ unsigned cpsr, scr;
+
+ if (rate > SSP_MAX_RATE)
+ rate = SSP_MAX_RATE;
+
+ if (rate < SSP_MIN_RATE)
+ return -1;
+
+ /* Calculate divisors so that we can get speed according the
+ * following formula:
+ * rate = spi_clock_rate / (cpsr * (1 + scr))
+ *
+ * cpsr must be even number and starts from 2, scr can be any number
+ * between 0 and 255.
+ */
+ for (cpsr = 2; cpsr <= 254; cpsr += 2) {
+ for (scr = 0; scr <= 255; scr++) {
+ if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) {
+ /* Set CHPA and CPOL, SPI format and 8bit */
+ unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) |
+ SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT;
+ if (mode & SPI_CPHA)
+ sspcr0 |= SSPCR0_SPH;
+ if (mode & SPI_CPOL)
+ sspcr0 |= SSPCR0_SPO;
+
+ slave->sspcr0 = sspcr0;
+ slave->sspcpsr = cpsr;
+ return 0;
+ }
+ }
+ }
+
+ return -1;
+}
+
+void spi_set_speed(struct spi_slave *slave, unsigned int hz)
+{
+ struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
+
+ unsigned int mode = 0;
+ if (as->sspcr0 & SSPCR0_SPH)
+ mode |= SPI_CPHA;
+ if (as->sspcr0 & SSPCR0_SPO)
+ mode |= SPI_CPOL;
+
+ ep93xx_spi_init_hw(hz, mode, as);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct ep93xx_spi_slave *as;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs);
+ if (!as)
+ return NULL;
+
+ if (ep93xx_spi_init_hw(max_hz, mode, as)) {
+ free(as);
+ return NULL;
+ }
+
+ return &as->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
+
+ free(as);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
+
+ /* Enable the SPI hardware */
+ ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE);
+
+
+ ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr);
+ ep93xx_spi_write_u16(SSPCR0, as->sspcr0);
+
+ debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n",
+ slave->cs, as->sspcpsr, as->sspcr0);
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ /* Disable the SPI hardware */
+ ep93xx_spi_write_u8(SSPCR1, 0);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ unsigned int len_tx;
+ unsigned int len_rx;
+ unsigned int len;
+ u32 status;
+ const u8 *txp = dout;
+ u8 *rxp = din;
+ u8 value;
+
+ debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
+ slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen);
+
+
+ if (bitlen == 0)
+ /* Finish any previously submitted transfers */
+ goto out;
+
+ if (bitlen % 8) {
+ /* Errors always terminate an ongoing transfer */
+ flags |= SPI_XFER_END;
+ goto out;
+ }
+
+ len = bitlen / 8;
+
+
+ if (flags & SPI_XFER_BEGIN) {
+ /* Empty RX FIFO */
+ while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE))
+ ep93xx_spi_read_u8(SSPDR);
+
+ spi_cs_activate(slave);
+ }
+
+ for (len_tx = 0, len_rx = 0; len_rx < len; ) {
+ status = ep93xx_spi_read_u8(SSPSR);
+
+ if ((len_tx < len) && (status & SSPSR_TNF)) {
+ if (txp)
+ value = *txp++;
+ else
+ value = 0xff;
+
+ ep93xx_spi_write_u8(SSPDR, value);
+ len_tx++;
+ }
+
+ if (status & SSPSR_RNE) {
+ value = ep93xx_spi_read_u8(SSPDR);
+
+ if (rxp)
+ *rxp++ = value;
+ len_rx++;
+ }
+ }
+
+out:
+ if (flags & SPI_XFER_END) {
+ /*
+ * Wait until the transfer is completely done before
+ * we deactivate CS.
+ */
+ do {
+ status = ep93xx_spi_read_u8(SSPSR);
+ } while (status & SSPSR_BSY);
+
+ spi_cs_deactivate(slave);
+ }
+
+ return 0;
+}
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7211c6a..04c1a64 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -13,6 +13,7 @@
obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
+obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
# echi
obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c
new file mode 100644
index 0000000..8fb4aba
--- /dev/null
+++ b/drivers/usb/host/ohci-ep93xx.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2013
+ * Sergey Kostanbaev < sergey.kostanbaev <at> fairwaves.ru >
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+
+int usb_cpu_init(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ unsigned long pwr = readl(&syscon->pwrcnt);
+ writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
+
+ return 0;
+}
+
+int usb_cpu_stop(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ unsigned long pwr = readl(&syscon->pwrcnt);
+ writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
+
+ return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+ return usb_cpu_stop();
+}
+
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 0000000..e788e1b
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/utils.h>
+
+#define DW_WDT_CR 0x00
+#define DW_WDT_TORR 0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET 0x00
+#define DW_WDT_CR_RMOD_OFFSET 0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+static int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+ if (i > 15)
+ i = 15;
+ if (i < 0)
+ i = 0;
+
+ writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+static void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
+ (0x1 << DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+static unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+ (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
diff --git a/include/common.h b/include/common.h
index cc74633..2e5a6d3 100644
--- a/include/common.h
+++ b/include/common.h
@@ -687,9 +687,6 @@
ulong get_bus_freq (ulong);
int get_serial_clock(void);
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
-ulong get_ddr_freq(ulong);
-#endif
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
@@ -705,6 +702,8 @@
{
return get_bus_freq(dummy);
}
+#else
+ulong get_ddr_freq(ulong);
#endif
#if defined(CONFIG_4xx)
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index febee45..b27f973 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2011 OMICRON electronics GmbH
+ * Copyright (C) 2011-2014 OMICRON electronics GmbH
*
* Based on da850evm.h. Original Copyrights follow:
*
@@ -18,6 +18,7 @@
#define CONFIG_DRIVER_TI_EMAC
#define MACH_TYPE_CALIMAIN 3528
#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
+#define CONFIG_SYS_GENERIC_BOARD
/*
* SoC Configuration
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..37bdcc0
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,292 @@
+/*
+ * U-boot - Configuration file for Cirrus Logic EDB93xx boards
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE "edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+
+#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
+
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
+#define CONFIG_SYS_PROMPT "EDB9301> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
+#define CONFIG_SYS_PROMPT "EDB9302> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
+#define CONFIG_SYS_PROMPT "EDB9302A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
+#define CONFIG_SYS_PROMPT "EDB9307> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
+#define CONFIG_SYS_PROMPT "EDB9307A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
+#define CONFIG_SYS_PROMPT "EDB9312> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
+#define CONFIG_SYS_PROMPT "EDB9315> "
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
+#define CONFIG_SYS_PROMPT "EDB9315A> "
+#define CONFIG_ENV_SECT_SIZE 0x00020000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
+#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */
+#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
+ 115200, 230400}
+#define CONFIG_SYS_SERIAL0 0x808C0000
+#define CONFIG_SYS_SERIAL1 0x808D0000
+/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1} */
+
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
+
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_GREEN 0
+#define STATUS_LED_RED 1
+/* Green */
+#define STATUS_LED_BIT STATUS_LED_GREEN
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1 STATUS_LED_RED
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT STATUS_LED_BIT
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_NET_MULTI
+#undef CONFIG_NETCONSOLE
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+ defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+ defined(CONFIG_EDB9315)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ *
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+
+#define CONFIG_EDB93XX_SDCS3
+
+#elif defined(CONFIG_EDB9302A) || \
+ defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ *
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_EDB93XX_SDCS0
+
+#else
+#error "no SDCS configuration for this board"
+#endif
+
+
+#if defined(CONFIG_EDB93XX_SDCS3)
+#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
+#define PHYS_SDRAM_1 0x00000000
+#elif defined(CONFIG_EDB93XX_SDCS0)
+#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
+#define PHYS_SDRAM_1 0xc0000000
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS 8
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
+
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_STACKSIZE (128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at
+ * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit
+ * data bus, for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ *
+ * EDB9301/02(a)7a/15a EDB9307/12/15
+ * 0x60000000 - 0x0003FFFF u-boot u-boot
+ * 0x60040000 - 0x0005FFFF environment #1 environment #1
+ * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF unused environment #2
+ * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF unused unused
+ * 0x61000000 - 0x01FFFFFF not present unused
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT (256+8)
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_ADDR 0x60040000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/* Define to enable MMC on SPI support */
+/* #define CONFIG_EP93XX_SPI_MMC */
+
+#ifdef CONFIG_EP93XX_SPI_MMC
+#define CONFIG_EP93XX_SPI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+#define CONFIG_CMD_MMC
+#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
+#endif
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_OHCI_EP93XX
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci"
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000
+
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_CMD_BOOTZ
+
+/* Define to disable flash configuration*/
+/* #define CONFIG_EP93XX_NO_FLASH_CFG */
+
+/* Define this for indusrial rated chips */
+/* #define CONFIG_EDB93XX_INDUSTRIAL */
+
+#endif /* !defined (__CONFIG_H) */
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index d026484..5d0b85e 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -12,6 +12,7 @@
#define MACH_TYPE_H2200 341
#define CONFIG_MACH_TYPE MACH_TYPE_H2200
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_CPU_PXA25X 1
#define CONFIG_BOARD_H2200
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 267a92b..eac517a 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -26,6 +26,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_OF_LIBFDT /* enable passing a Device Tree */
#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
+#define CONFIG_SYS_GENERIC_BOARD
/*
* There are various dependencies on the core module (CM) fitted
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
new file mode 100644
index 0000000..2bd5a47
--- /dev/null
+++ b/include/configs/ls2085a_common.h
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_COMMON_H
+#define __LS2_COMMON_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LSCH3
+#define CONFIG_LS2085A
+#define CONFIG_GICV3
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE 0x30000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_IDENT_STRING " LS2085A-EMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#endif
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
+
+/* SMP Definitions */
+#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 12000000 /* 12MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* IFC */
+#define CONFIG_FSL_IFC
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/*
+ * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
+ * address 0. But this region is limited to 256MB. To accommodate bigger NOR
+ * flash and other devices, we will map CS0 to 0x580000000 after relocation.
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
+ */
+#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
+#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x1) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
+ FTIM2_NOR_TCH(0x0) | \
+ FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+/* MC firmware */
+#define CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
+/* TODO Actual FW length needs to be determined at runtime from FW header */
+#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
+/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
+#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size()
+#endif
+
+/* Command line configuration */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* Physical Memory Map */
+/* fixme: these need to be checked against the board */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_SYS_CLK_FREQ 133333333
+
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x581200000\0" \
+ "kernel_load=0x806f0000\0" \
+ "kernel_size=0x1000000\0" \
+ "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
+ "earlyprintk=uart8250-8bit,0x21c0600"
+#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
+ "$kernel_size && bootm $kernel_load"
+#define CONFIG_BOOTDELAY 1
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT "> "
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#ifndef __ASSEMBLY__
+unsigned long mc_get_dram_block_size(void);
+#endif
+
+#endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
new file mode 100644
index 0000000..a5cea63
--- /dev/null
+++ b/include/configs/ls2085a_emu.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_EMU_H
+#define __LS2_EMU_H
+
+#include "ls2085a_common.h"
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
+
+#endif /* __LS2_EMU_H */
diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h
new file mode 100644
index 0000000..46d47b0
--- /dev/null
+++ b/include/configs/ls2085a_simu.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_SIMU_H
+#define __LS2_SIMU_H
+
+#include "ls2085a_common.h"
+
+/* SMSC 91C111 ethernet configuration */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE (0x2210000)
+
+#endif /* __LS2_SIMU_H */
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index ed8b4df..ff48598 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -20,6 +20,7 @@
#include <linux/sizes.h>
/* Architecture, CPU, etc.*/
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ARM1176
#define CONFIG_BCM2835
#define CONFIG_ARCH_CPU_INIT
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 0254249..7646a85 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -8,6 +8,7 @@
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/iocsr_config.h"
#include "../../board/altera/socfpga/pll_config.h"
/*
@@ -206,6 +207,17 @@
#define CONFIG_ENV_IS_NOWHERE
/*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ 25000
+
+
+/*
* SPL "Second Program Loader" aka Initial Software
*/
@@ -237,4 +249,7 @@
/* Support for lib/libgeneric.o in SPL binary */
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
#endif /* __CONFIG_H */
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index dff6adc..1905d13 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -10,9 +10,20 @@
#define DEBUG
+#ifdef CONFIG_BASE_FVP
+#ifndef CONFIG_SEMIHOSTING
+#error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
+#endif
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_ARMV8_SWITCH_TO_EL1
+#endif
+
#define CONFIG_REMAKE_ELF
+#ifndef CONFIG_BASE_FVP
+/* Base FVP not using GICv3 yet */
#define CONFIG_GICV3
+#endif
/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
@@ -30,8 +41,14 @@
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
/* Link Definitions */
+#ifdef CONFIG_BASE_FVP
+/* ATF loads u-boot here for BASE_FVP model */
+#define CONFIG_SYS_TEXT_BASE 0x88000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+#else
#define CONFIG_SYS_TEXT_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#endif
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
@@ -39,7 +56,11 @@
#define CONFIG_DEFAULT_DEVICE_TREE vexpress64
/* SMP Spin Table Definitions */
+#ifdef CONFIG_BASE_FVP
+#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+#else
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#endif
/* CS register bases for the original memory map. */
#define V2M_PA_CS0 0x00000000
@@ -99,9 +120,15 @@
#define GICD_BASE (0x2f000000)
#define GICR_BASE (0x2f100000)
#else
+
+#ifdef CONFIG_BASE_FVP
+#define GICD_BASE (0x2f000000)
+#define GICC_BASE (0x2c000000)
+#else
#define GICD_BASE (0x2C001000)
#define GICC_BASE (0x2C002000)
#endif
+#endif
#define CONFIG_SYS_MEMTEST_START V2M_BASE
#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000)
@@ -121,7 +148,6 @@
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
@@ -165,17 +191,41 @@
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Initial environment variables */
+#ifdef CONFIG_BASE_FVP
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_name=uImage\0" \
+ "kernel_addr_r=0x80000000\0" \
+ "initrd_name=ramdisk.img\0" \
+ "initrd_addr_r=0x88000000\0" \
+ "fdt_name=devtree.dtb\0" \
+ "fdt_addr_r=0x83000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0"
+
+#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
+ "0x1c090000 debug user_debug=31 "\
+ "loglevel=9"
+
+#define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \
+ "fdt chosen $initrd_addr_r $initrd_end; " \
+ "bootm $kernel_addr_r - $fdt_addr_r"
+
+#define CONFIG_BOOTDELAY 1
+
+#else
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr=0x200000\0" \
- "initrd_addr=0xa00000\0" \
+ "kernel_addr_r=0x200000\0" \
+ "initrd_addr_r=0xa00000\0" \
"initrd_size=0x2000000\0" \
- "fdt_addr=0x100000\0" \
+ "fdt_addr_r=0x100000\0" \
"fdt_high=0xa0000000\0"
#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
-#define CONFIG_BOOTCOMMAND "bootm $kernel_addr " \
- "$initrd_addr:$initrd_size $fdt_addr"
+#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \
+ "$initrd_addr_r:$initrd_size $fdt_addr_r"
#define CONFIG_BOOTDELAY -1
+#endif
/* Do not preserve environment */
#define CONFIG_ENV_IS_NOWHERE 1
@@ -187,7 +237,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING 1
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 21d7b44..fd44d7e 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -113,17 +113,25 @@
{
return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0);
}
+static inline int fdt_status_fail(void *fdt, int nodeoffset)
+{
+ return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_FAIL, 0);
+}
-int fdt_set_status_by_alias(void *fdt, const char* alias,
+int fdt_set_status_by_alias(void *fdt, const char *alias,
enum fdt_status status, unsigned int error_code);
-static inline int fdt_status_okay_by_alias(void *fdt, const char* alias)
+static inline int fdt_status_okay_by_alias(void *fdt, const char *alias)
{
return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0);
}
-static inline int fdt_status_disabled_by_alias(void *fdt, const char* alias)
+static inline int fdt_status_disabled_by_alias(void *fdt, const char *alias)
{
return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0);
}
+static inline int fdt_status_fail_by_alias(void *fdt, const char *alias)
+{
+ return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0);
+}
#endif /* ifdef CONFIG_OF_LIBFDT */
diff --git a/include/fsl_mc.h b/include/fsl_mc.h
new file mode 100644
index 0000000..b9f089e
--- /dev/null
+++ b/include/fsl_mc.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_MC_H__
+#define __FSL_MC_H__
+
+#include <common.h>
+
+#define MC_CCSR_BASE_ADDR \
+ ((struct mc_ccsr_registers __iomem *)0x8340000)
+
+#define BIT(x) (1 << (x))
+#define GCR1_P1_STOP BIT(31)
+#define GCR1_P2_STOP BIT(30)
+#define GCR1_P1_DE_RST BIT(23)
+#define GCR1_P2_DE_RST BIT(22)
+#define GCR1_M1_DE_RST BIT(15)
+#define GCR1_M2_DE_RST BIT(14)
+#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
+#define GSR_FS_MASK 0x3fffffff
+#define MCFAPR_PL_MASK (0x1 << 18)
+#define MCFAPR_BMT_MASK (0x1 << 17)
+#define MCFAPR_BYPASS_ICID_MASK \
+ (MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
+
+#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
+#define SOC_MC_PORTAL_STRIDE 0x10000
+
+#define SOC_MC_PORTAL_ADDR(_portal_id) \
+ ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
+ (_portal_id) * SOC_MC_PORTAL_STRIDE))
+
+struct mc_ccsr_registers {
+ u32 reg_gcr1;
+ u32 reserved1;
+ u32 reg_gsr;
+ u32 reserved2;
+ u32 reg_sicbalr;
+ u32 reg_sicbahr;
+ u32 reg_sicapr;
+ u32 reserved3;
+ u32 reg_mcfbalr;
+ u32 reg_mcfbahr;
+ u32 reg_mcfapr;
+ u32 reserved4[0x2f1];
+ u32 reg_psr;
+ u32 reserved5;
+ u32 reg_brr[2];
+ u32 reserved6[0x80];
+ u32 reg_error[];
+};
+
+int mc_init(bd_t *bis);
+
+int get_mc_boot_status(void);
+#endif