armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 9db4a4f..d692106 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -12,6 +12,8 @@
#include <asm/hardware.h>
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */