sunxi: Update DRAM clock for Olimex A20 boards
Originally dram clock was set to 480MHz, but this behaves
unstable. To improve stability the clock is reduced to 384MHz
Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 7a14a7b..3f4e90d 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -2,7 +2,7 @@
CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH0"
CONFIG_MMC3_PINS="PH"