EXYNOS: Move files from board/samsung to arch/arm
This patch performs the following:
1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted
the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already
done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.
TEST: Tested SD-MMC boot on SMDK5250 and Origen.
Tested USB and SPI boot on SMDK5250
Compile tested for SMDKV310.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile
index 3a885a5..63c8b46 100644
--- a/board/samsung/origen/Makefile
+++ b/board/samsung/origen/Makefile
@@ -24,19 +24,12 @@
LIB = $(obj)lib$(BOARD).o
-SOBJS := mem_setup.o
-SOBJS += lowlevel_init.o
-
ifndef CONFIG_SPL_BUILD
COBJS += origen.o
endif
-ifdef CONFIG_SPL_BUILD
-COBJS += mmc_boot.o
-endif
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
ALL +=$(obj).depend $(LIB)
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
deleted file mode 100644
index be9d418..0000000
--- a/board/samsung/origen/lowlevel_init.S
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * Lowlevel setup for ORIGEN board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include "origen_setup.h"
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
- .globl lowlevel_init
-lowlevel_init:
- push {lr}
-
- /* r5 has always zero */
- mov r5, #0
- ldr r7, =EXYNOS4_GPIO_PART1_BASE
- ldr r6, =EXYNOS4_GPIO_PART2_BASE
-
- /* check reset status */
- ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
- ldr r1, [r0]
-
- /* AFTR wakeup reset */
- ldr r2, =S5P_CHECK_DIDLE
- cmp r1, r2
- beq exit_wakeup
-
- /* LPA wakeup reset */
- ldr r2, =S5P_CHECK_LPA
- cmp r1, r2
- beq exit_wakeup
-
- /* Sleep wakeup reset */
- ldr r2, =S5P_CHECK_SLEEP
- cmp r1, r2
- beq wakeup_reset
-
- /*
- * If U-boot is already running in ram, no need to relocate U-Boot.
- * Memory controller must be configured before relocating U-Boot
- * in ram.
- */
- ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
- bic r1, pc, r0 /* pc <- current addr of code */
- /* r1 <- unmasked bits of pc */
- ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
- bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
- cmp r1, r2 /* compare r1, r2 */
- beq 1f /* r0 == r1 then skip sdram init */
-
- /* init system clock */
- bl system_clock_init
-
- /* Memory initialize */
- bl mem_ctrl_asm_init
-
-1:
- /* for UART */
- bl uart_asm_init
- bl arch_cpu_init
- bl tzpc_init
- pop {pc}
-
-wakeup_reset:
- bl system_clock_init
- bl mem_ctrl_asm_init
- bl arch_cpu_init
- bl tzpc_init
-
-exit_wakeup:
- /* Load return address and jump to kernel */
- ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
-
- /* r1 = physical address of exynos4210_cpu_resume function */
- ldr r1, [r0]
-
- /* Jump to kernel*/
- mov pc, r1
- nop
- nop
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
- push {lr}
- ldr r0, =EXYNOS4_CLOCK_BASE
-
- /* APLL(1), MPLL(1), CORE(0), HPM(0) */
- ldr r1, =CLK_SRC_CPU_VAL
- ldr r2, =CLK_SRC_CPU_OFFSET
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x10000
-2: subs r1, r1, #1
- bne 2b
-
- ldr r1, =CLK_SRC_TOP0_VAL
- ldr r2, =CLK_SRC_TOP0_OFFSET
- str r1, [r0, r2]
-
- ldr r1, =CLK_SRC_TOP1_VAL
- ldr r2, =CLK_SRC_TOP1_OFFSET
- str r1, [r0, r2]
-
- /* DMC */
- ldr r1, =CLK_SRC_DMC_VAL
- ldr r2, =CLK_SRC_DMC_OFFSET
- str r1, [r0, r2]
-
- /*CLK_SRC_LEFTBUS */
- ldr r1, =CLK_SRC_LEFTBUS_VAL
- ldr r2, =CLK_SRC_LEFTBUS_OFFSET
- str r1, [r0, r2]
-
- /*CLK_SRC_RIGHTBUS */
- ldr r1, =CLK_SRC_RIGHTBUS_VAL
- ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
- str r1, [r0, r2]
-
- /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
- ldr r1, =CLK_SRC_FSYS_VAL
- ldr r2, =CLK_SRC_FSYS_OFFSET
- str r1, [r0, r2]
-
- /* UART[0:4] */
- ldr r1, =CLK_SRC_PERIL0_VAL
- ldr r2, =CLK_SRC_PERIL0_OFFSET
- str r1, [r0, r2]
-
- /* CAM , FIMC 0-3 */
- ldr r1, =CLK_SRC_CAM_VAL
- ldr r2, =CLK_SRC_CAM_OFFSET
- str r1, [r0, r2]
-
- /* MFC */
- ldr r1, =CLK_SRC_MFC_VAL
- ldr r2, =CLK_SRC_MFC_OFFSET
- str r1, [r0, r2]
-
- /* G3D */
- ldr r1, =CLK_SRC_G3D_VAL
- ldr r2, =CLK_SRC_G3D_OFFSET
- str r1, [r0, r2]
-
- /* LCD0 */
- ldr r1, =CLK_SRC_LCD0_VAL
- ldr r2, =CLK_SRC_LCD0_OFFSET
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x10000
-3: subs r1, r1, #1
- bne 3b
-
- /* CLK_DIV_CPU0 */
- ldr r1, =CLK_DIV_CPU0_VAL
- ldr r2, =CLK_DIV_CPU0_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_CPU1 */
- ldr r1, =CLK_DIV_CPU1_VAL
- ldr r2, =CLK_DIV_CPU1_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_DMC0 */
- ldr r1, =CLK_DIV_DMC0_VAL
- ldr r2, =CLK_DIV_DMC0_OFFSET
- str r1, [r0, r2]
-
- /*CLK_DIV_DMC1 */
- ldr r1, =CLK_DIV_DMC1_VAL
- ldr r2, =CLK_DIV_DMC1_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_LEFTBUS */
- ldr r1, =CLK_DIV_LEFTBUS_VAL
- ldr r2, =CLK_DIV_LEFTBUS_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_RIGHTBUS */
- ldr r1, =CLK_DIV_RIGHTBUS_VAL
- ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_TOP */
- ldr r1, =CLK_DIV_TOP_VAL
- ldr r2, =CLK_DIV_TOP_OFFSET
- str r1, [r0, r2]
-
- /* MMC[0:1] */
- ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */
- ldr r2, =CLK_DIV_FSYS1_OFFSET
- str r1, [r0, r2]
-
- /* MMC[2:3] */
- ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */
- ldr r2, =CLK_DIV_FSYS2_OFFSET
- str r1, [r0, r2]
-
- /* MMC4 */
- ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */
- ldr r2, =CLK_DIV_FSYS3_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_PERIL0: UART Clock Divisors */
- ldr r1, =CLK_DIV_PERIL0_VAL
- ldr r2, =CLK_DIV_PERIL0_OFFSET
- str r1, [r0, r2]
-
- /* CAM, FIMC 0-3: CAM Clock Divisors */
- ldr r1, =CLK_DIV_CAM_VAL
- ldr r2, =CLK_DIV_CAM_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_MFC: MFC Clock Divisors */
- ldr r1, =CLK_DIV_MFC_VAL
- ldr r2, =CLK_DIV_MFC_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_G3D: G3D Clock Divisors */
- ldr r1, =CLK_DIV_G3D_VAL
- ldr r2, =CLK_DIV_G3D_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_LCD0: LCD0 Clock Divisors */
- ldr r1, =CLK_DIV_LCD0_VAL
- ldr r2, =CLK_DIV_LCD0_OFFSET
- str r1, [r0, r2]
-
- /* Set PLL locktime */
- ldr r1, =PLL_LOCKTIME
- ldr r2, =APLL_LOCK_OFFSET
- str r1, [r0, r2]
-
- ldr r1, =PLL_LOCKTIME
- ldr r2, =MPLL_LOCK_OFFSET
- str r1, [r0, r2]
-
- ldr r1, =PLL_LOCKTIME
- ldr r2, =EPLL_LOCK_OFFSET
- str r1, [r0, r2]
-
- ldr r1, =PLL_LOCKTIME
- ldr r2, =VPLL_LOCK_OFFSET
- str r1, [r0, r2]
-
- /* APLL_CON1 */
- ldr r1, =APLL_CON1_VAL
- ldr r2, =APLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /* APLL_CON0 */
- ldr r1, =APLL_CON0_VAL
- ldr r2, =APLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /* MPLL_CON1 */
- ldr r1, =MPLL_CON1_VAL
- ldr r2, =MPLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /* MPLL_CON0 */
- ldr r1, =MPLL_CON0_VAL
- ldr r2, =MPLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /* EPLL */
- ldr r1, =EPLL_CON1_VAL
- ldr r2, =EPLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /* EPLL_CON0 */
- ldr r1, =EPLL_CON0_VAL
- ldr r2, =EPLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /* VPLL_CON1 */
- ldr r1, =VPLL_CON1_VAL
- ldr r2, =VPLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /* VPLL_CON0 */
- ldr r1, =VPLL_CON0_VAL
- ldr r2, =VPLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x30000
-4: subs r1, r1, #1
- bne 4b
-
- pop {pc}
-/*
- * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
- * void uart_asm_init(void)
- */
- .globl uart_asm_init
-uart_asm_init:
-
- /* setup UART0-UART3 GPIOs (part1) */
- mov r0, r7
- ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
- str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
- ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
- str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
-
- ldr r0, =EXYNOS4_UART_BASE
- add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
-
- ldr r1, =ULCON_VAL
- str r1, [r0, #ULCON_OFFSET]
- ldr r1, =UCON_VAL
- str r1, [r0, #UCON_OFFSET]
- ldr r1, =UFCON_VAL
- str r1, [r0, #UFCON_OFFSET]
- ldr r1, =UBRDIV_VAL
- str r1, [r0, #UBRDIV_OFFSET]
- ldr r1, =UFRACVAL_VAL
- str r1, [r0, #UFRACVAL_OFFSET]
- mov pc, lr
- nop
- nop
- nop
-
diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S
deleted file mode 100644
index b49b193..0000000
--- a/board/samsung/origen/mem_setup.S
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Memory setup for ORIGEN board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include "origen_setup.h"
-#define SET_MIU
-
- .globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
- /*
- * Async bridge configuration at CPU_core:
- * 1: half_sync
- * 0: full_sync
- */
- ldr r0, =ASYNC_CONFIG
- mov r1, #1
- str r1, [r0]
-
-#ifdef SET_MIU
- ldr r0, =EXYNOS4_MIU_BASE
- /* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
- ldr r1, =0x20001507
- str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
-
- /* Update MIU Configuration */
- ldr r1, =0x00000001
- str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
-#endif
- /* DREX0 */
- ldr r0, =EXYNOS4_DMC0_BASE
-
- /*
- * DLL Parameter Setting:
- * Termination: Enable R/W
- * Phase Delay for DQS Cleaning: 180' Shift
- */
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /*
- * ZQ Calibration
- * Termination: Disable
- * Auto Calibration Start: Enable
- */
- ldr r1, =0xE3855703
- str r1, [r0, #DMC_PHYZQCONTROL]
-
- /* Wait ?us*/
- mov r2, #0x100000
-1: subs r2, r2, #1
- bne 1b
-
- /*
- * Update DLL Information:
- * Force DLL Resyncronization
- */
- ldr r1, =0xe000008e
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* Reset Force DLL Resyncronization */
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* Enable Differential DQS, DLL Off*/
- ldr r1, =0x71101008
- str r1, [r0, #DMC_PHYCONTROL0]
-
- /* Activate PHY DLL: DLL On */
- ldr r1, =0x7110100A
- str r1, [r0, #DMC_PHYCONTROL0]
-
- /* Set DLL Parameters */
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* DLL Start */
- ldr r1, =0x7110100B
- str r1, [r0, #DMC_PHYCONTROL0]
-
- ldr r1, =0x00000000
- str r1, [r0, #DMC_PHYCONTROL2]
-
- /* Set Clock Ratio of Bus clock to Memory Clock */
- ldr r1, =0x0FFF301a
- str r1, [r0, #DMC_CONCONTROL]
-
- /*
- * Memor Burst length: 8
- * Number of chips: 2
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 1 Cycle
- */
- ldr r1, =0x00312640
- str r1, [r0, #DMC_MEMCONTROL]
-
- /*
- * Memory Configuration Chip 0
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- ldr r1, =0x20e01323
- str r1, [r0, #DMC_MEMCONFIG0]
-
- /*
- * Memory Configuration Chip 1
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- ldr r1, =0x40e01323
- str r1, [r0, #DMC_MEMCONFIG1]
-
- /* Config Precharge Policy */
- ldr r1, =0xff000000
- str r1, [r0, #DMC_PRECHCONFIG]
-
- /*
- * TimingAref, TimingRow, TimingData, TimingPower Setting:
- * Values as per Memory AC Parameters
- */
- ldr r1, =0x000000BB
- str r1, [r0, #DMC_TIMINGAREF]
- ldr r1, =0x4046654f
- str r1, [r0, #DMC_TIMINGROW]
- ldr r1, =0x46400506
- str r1, [r0, #DMC_TIMINGDATA]
- ldr r1, =0x52000A3C
- str r1, [r0, #DMC_TIMINGPOWER]
-
- /* Chip0: NOP Command: Assert and Hold CKE to high level */
- ldr r1, =0x07000000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-2: subs r2, r2, #1
- bne 2b
-
- /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- ldr r1, =0x00020000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00030000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00010002
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00000328
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-3: subs r2, r2, #1
- bne 3b
-
- /* Chip0: ZQINIT */
- ldr r1, =0x0a000000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-4: subs r2, r2, #1
- bne 4b
-
- /* Chip1: NOP Command: Assert and Hold CKE to high level */
- ldr r1, =0x07100000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-5: subs r2, r2, #1
- bne 5b
-
- /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- ldr r1, =0x00120000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00130000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00110002
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00100328
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-6: subs r2, r2, #1
- bne 6b
-
- /* Chip1: ZQINIT */
- ldr r1, =0x0a100000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-7: subs r2, r2, #1
- bne 7b
-
- ldr r1, =0xe000008e
- str r1, [r0, #DMC_PHYCONTROL1]
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* Wait ?us*/
- mov r2, #0x100000
-8: subs r2, r2, #1
- bne 8b
-
- /* DREX1 */
- ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
-
- /*
- * DLL Parameter Setting:
- * Termination: Enable R/W
- * Phase Delay for DQS Cleaning: 180' Shift
- */
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /*
- * ZQ Calibration:
- * Termination: Disable
- * Auto Calibration Start: Enable
- */
- ldr r1, =0xE3855703
- str r1, [r0, #DMC_PHYZQCONTROL]
-
- /* Wait ?us*/
- mov r2, #0x100000
-1: subs r2, r2, #1
- bne 1b
-
- /*
- * Update DLL Information:
- * Force DLL Resyncronization
- */
- ldr r1, =0xe000008e
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* Reset Force DLL Resyncronization */
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* Enable Differential DQS, DLL Off*/
- ldr r1, =0x71101008
- str r1, [r0, #DMC_PHYCONTROL0]
-
- /* Activate PHY DLL: DLL On */
- ldr r1, =0x7110100A
- str r1, [r0, #DMC_PHYCONTROL0]
-
- /* Set DLL Parameters */
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* DLL Start */
- ldr r1, =0x7110100B
- str r1, [r0, #DMC_PHYCONTROL0]
-
- ldr r1, =0x00000000
- str r1, [r0, #DMC_PHYCONTROL2]
-
- /* Set Clock Ratio of Bus clock to Memory Clock */
- ldr r1, =0x0FFF301a
- str r1, [r0, #DMC_CONCONTROL]
-
- /*
- * Memor Burst length: 8
- * Number of chips: 2
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 1 Cycle
- */
- ldr r1, =0x00312640
- str r1, [r0, #DMC_MEMCONTROL]
-
- /*
- * Memory Configuration Chip 0
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- ldr r1, =0x20e01323
- str r1, [r0, #DMC_MEMCONFIG0]
-
- /*
- * Memory Configuration Chip 1
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- ldr r1, =0x40e01323
- str r1, [r0, #DMC_MEMCONFIG1]
-
- /* Config Precharge Policy */
- ldr r1, =0xff000000
- str r1, [r0, #DMC_PRECHCONFIG]
-
- /*
- * TimingAref, TimingRow, TimingData, TimingPower Setting:
- * Values as per Memory AC Parameters
- */
- ldr r1, =0x000000BB
- str r1, [r0, #DMC_TIMINGAREF]
- ldr r1, =0x4046654f
- str r1, [r0, #DMC_TIMINGROW]
- ldr r1, =0x46400506
- str r1, [r0, #DMC_TIMINGDATA]
- ldr r1, =0x52000A3C
- str r1, [r0, #DMC_TIMINGPOWER]
-
- /* Chip0: NOP Command: Assert and Hold CKE to high level */
- ldr r1, =0x07000000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-2: subs r2, r2, #1
- bne 2b
-
- /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- ldr r1, =0x00020000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00030000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00010002
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00000328
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-3: subs r2, r2, #1
- bne 3b
-
- /* Chip 0: ZQINIT */
- ldr r1, =0x0a000000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-4: subs r2, r2, #1
- bne 4b
-
- /* Chip1: NOP Command: Assert and Hold CKE to high level */
- ldr r1, =0x07100000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-5: subs r2, r2, #1
- bne 5b
-
- /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
- ldr r1, =0x00120000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00130000
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00110002
- str r1, [r0, #DMC_DIRECTCMD]
- ldr r1, =0x00100328
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-6: subs r2, r2, #1
- bne 6b
-
- /* Chip1: ZQINIT */
- ldr r1, =0x0a100000
- str r1, [r0, #DMC_DIRECTCMD]
-
- /* Wait ?us*/
- mov r2, #0x100000
-7: subs r2, r2, #1
- bne 7b
-
- ldr r1, =0xe000008e
- str r1, [r0, #DMC_PHYCONTROL1]
- ldr r1, =0xe0000086
- str r1, [r0, #DMC_PHYCONTROL1]
-
- /* Wait ?us*/
- mov r2, #0x100000
-8: subs r2, r2, #1
- bne 8b
-
- /* turn on DREX0, DREX1 */
- ldr r0, =EXYNOS4_DMC0_BASE
- ldr r1, =0x0FFF303a
- str r1, [r0, #DMC_CONCONTROL]
-
- ldr r0, =EXYNOS4_DMC1_BASE
- ldr r1, =0x0FFF303a
- str r1, [r0, #DMC_CONCONTROL]
-
- mov pc, lr
diff --git a/board/samsung/origen/mmc_boot.c b/board/samsung/origen/mmc_boot.c
deleted file mode 100644
index 072f161..0000000
--- a/board/samsung/origen/mmc_boot.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include<common.h>
-#include<config.h>
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* Pointer to API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
- u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
-
- copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
-}
-
-void board_init_f(unsigned long bootflag)
-{
- __attribute__((noreturn)) void (*uboot)(void);
- copy_uboot_to_ram();
-
- /* Jump to U-Boot image */
- uboot = (void *)CONFIG_SYS_TEXT_BASE;
- (*uboot)();
- /* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- /* Function attribute is no-return */
- /* This Function never executes */
- while (1)
- ;
-}
-
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
deleted file mode 100644
index 926a4cc..0000000
--- a/board/samsung/origen/origen_setup.h
+++ /dev/null
@@ -1,607 +0,0 @@
-/*
- * Machine Specific Values for ORIGEN board based on S5PV310
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ORIGEN_SETUP_H
-#define _ORIGEN_SETUP_H
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-/* Offsets of clock registers (sources and dividers) */
-#define CLK_SRC_CPU_OFFSET 0x14200
-#define CLK_DIV_CPU0_OFFSET 0x14500
-#define CLK_DIV_CPU1_OFFSET 0x14504
-
-#define CLK_SRC_DMC_OFFSET 0x10200
-#define CLK_DIV_DMC0_OFFSET 0x10500
-#define CLK_DIV_DMC1_OFFSET 0x10504
-
-#define CLK_SRC_TOP0_OFFSET 0xC210
-#define CLK_SRC_TOP1_OFFSET 0xC214
-#define CLK_DIV_TOP_OFFSET 0xC510
-
-#define CLK_SRC_LEFTBUS_OFFSET 0x4200
-#define CLK_DIV_LEFTBUS_OFFSET 0x4500
-
-#define CLK_SRC_RIGHTBUS_OFFSET 0x8200
-#define CLK_DIV_RIGHTBUS_OFFSET 0x8500
-
-#define CLK_SRC_FSYS_OFFSET 0xC240
-#define CLK_DIV_FSYS1_OFFSET 0xC544
-#define CLK_DIV_FSYS2_OFFSET 0xC548
-#define CLK_DIV_FSYS3_OFFSET 0xC54C
-
-#define CLK_SRC_CAM_OFFSET 0xC220
-#define CLK_SRC_TV_OFFSET 0xC224
-#define CLK_SRC_MFC_OFFSET 0xC228
-#define CLK_SRC_G3D_OFFSET 0xC22C
-#define CLK_SRC_LCD0_OFFSET 0xC234
-#define CLK_SRC_PERIL0_OFFSET 0xC250
-
-#define CLK_DIV_CAM_OFFSET 0xC520
-#define CLK_DIV_TV_OFFSET 0xC524
-#define CLK_DIV_MFC_OFFSET 0xC528
-#define CLK_DIV_G3D_OFFSET 0xC52C
-#define CLK_DIV_LCD0_OFFSET 0xC534
-#define CLK_DIV_PERIL0_OFFSET 0xC550
-
-#define CLK_SRC_LCD0_OFFSET 0xC234
-
-#define APLL_LOCK_OFFSET 0x14000
-#define MPLL_LOCK_OFFSET 0x14008
-#define APLL_CON0_OFFSET 0x14100
-#define APLL_CON1_OFFSET 0x14104
-#define MPLL_CON0_OFFSET 0x14108
-#define MPLL_CON1_OFFSET 0x1410C
-
-#define EPLL_LOCK_OFFSET 0xC010
-#define VPLL_LOCK_OFFSET 0xC020
-#define EPLL_CON0_OFFSET 0xC110
-#define EPLL_CON1_OFFSET 0xC114
-#define VPLL_CON0_OFFSET 0xC120
-#define VPLL_CON1_OFFSET 0xC124
-
-/* DMC: DRAM Controllor Register offsets */
-#define DMC_CONCONTROL 0x00
-#define DMC_MEMCONTROL 0x04
-#define DMC_MEMCONFIG0 0x08
-#define DMC_MEMCONFIG1 0x0C
-#define DMC_DIRECTCMD 0x10
-#define DMC_PRECHCONFIG 0x14
-#define DMC_PHYCONTROL0 0x18
-#define DMC_PHYCONTROL1 0x1C
-#define DMC_PHYCONTROL2 0x20
-#define DMC_TIMINGAREF 0x30
-#define DMC_TIMINGROW 0x34
-#define DMC_TIMINGDATA 0x38
-#define DMC_TIMINGPOWER 0x3C
-#define DMC_PHYZQCONTROL 0x44
-
-/* Bus Configuration Register Address */
-#define ASYNC_CONFIG 0x10010350
-
-/* MIU Config Register Offsets*/
-#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
-#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET 0x800
-#define INFORM1_OFFSET 0x804
-
-/* GPIO Offsets for UART: GPIO Contol Register */
-#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
-#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
-
-/* UART Register offsets */
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET 0x04
-#define UFCON_OFFSET 0x08
-#define UBRDIV_OFFSET 0x28
-#define UFRACVAL_OFFSET 0x2C
-
-/* CLK_SRC_CPU */
-#define MUX_HPM_SEL_MOUTAPLL 0x0
-#define MUX_HPM_SEL_SCLKMPLL 0x1
-#define MUX_CORE_SEL_MOUTAPLL 0x0
-#define MUX_CORE_SEL_SCLKMPLL 0x1
-#define MUX_MPLL_SEL_FILPLL 0x0
-#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
-#define MUX_APLL_SEL_FILPLL 0x0
-#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
- | (MUX_CORE_SEL_MOUTAPLL << 16) \
- | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
- | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
-
-/* CLK_DIV_CPU0 */
-#define APLL_RATIO 0x0
-#define PCLK_DBG_RATIO 0x1
-#define ATB_RATIO 0x3
-#define PERIPH_RATIO 0x3
-#define COREM1_RATIO 0x7
-#define COREM0_RATIO 0x3
-#define CORE_RATIO 0x0
-#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
- | (PCLK_DBG_RATIO << 20) \
- | (ATB_RATIO << 16) \
- | (PERIPH_RATIO << 12) \
- | (COREM1_RATIO << 8) \
- | (COREM0_RATIO << 4) \
- | (CORE_RATIO << 0))
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO 0x0
-#define COPY_RATIO 0x3
-#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
-
-/* CLK_SRC_DMC */
-#define MUX_PWI_SEL_XXTI 0x0
-#define MUX_PWI_SEL_XUSBXTI 0x1
-#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
-#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
-#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
-#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
-#define MUX_PWI_SEL_SCLKMPLL 0x6
-#define MUX_PWI_SEL_SCLKEPLL 0x7
-#define MUX_PWI_SEL_SCLKVPLL 0x8
-#define MUX_DPHY_SEL_SCLKMPLL 0x0
-#define MUX_DPHY_SEL_SCLKAPLL 0x1
-#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
-#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
-#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
- | (MUX_DPHY_SEL_SCLKMPLL << 8) \
- | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
-
-/* CLK_DIV_DMC0 */
-#define CORE_TIMERS_RATIO 0x1
-#define COPY2_RATIO 0x3
-#define DMCP_RATIO 0x1
-#define DMCD_RATIO 0x1
-#define DMC_RATIO 0x1
-#define DPHY_RATIO 0x1
-#define ACP_PCLK_RATIO 0x1
-#define ACP_RATIO 0x3
-#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
- | (COPY2_RATIO << 24) \
- | (DMCP_RATIO << 20) \
- | (DMCD_RATIO << 16) \
- | (DMC_RATIO << 12) \
- | (DPHY_RATIO << 8) \
- | (ACP_PCLK_RATIO << 4) \
- | (ACP_RATIO << 0))
-
-/* CLK_DIV_DMC1 */
-#define DPM_RATIO 0x1
-#define DVSEM_RATIO 0x1
-#define PWI_RATIO 0x1
-#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
- | (DVSEM_RATIO << 16) \
- | (PWI_RATIO << 8))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ONENAND_SEL_ACLK_133 0x0
-#define MUX_ONENAND_SEL_ACLK_160 0x1
-#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
-#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
-#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
-#define MUX_VPLL_SEL_FINPLL 0x0
-#define MUX_VPLL_SEL_FOUTVPLL 0x1
-#define MUX_EPLL_SEL_FINPLL 0x0
-#define MUX_EPLL_SEL_FOUTEPLL 0x1
-#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
-#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
-#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
- | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
- | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
- | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
- | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
- | (MUX_VPLL_SEL_FINPLL << 8) \
- | (MUX_EPLL_SEL_FINPLL << 4)\
- | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
-
-/* CLK_SRC_TOP1 */
-#define VPLLSRC_SEL_FINPLL 0x0
-#define VPLLSRC_SEL_SCLKHDMI24M 0x1
-#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
-
-/* CLK_DIV_TOP */
-#define ONENAND_RATIO 0x0
-#define ACLK_133_RATIO 0x5
-#define ACLK_160_RATIO 0x4
-#define ACLK_100_RATIO 0x7
-#define ACLK_200_RATIO 0x3
-#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
- | (ACLK_133_RATIO << 12)\
- | (ACLK_160_RATIO << 8) \
- | (ACLK_100_RATIO << 4) \
- | (ACLK_200_RATIO << 0))
-
-/* CLK_SRC_LEFTBUS */
-#define MUX_GDL_SEL_SCLKMPLL 0x0
-#define MUX_GDL_SEL_SCLKAPLL 0x1
-#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
-
-/* CLK_DIV_LEFTBUS */
-#define GPL_RATIO 0x1
-#define GDL_RATIO 0x3
-#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
-
-/* CLK_SRC_RIGHTBUS */
-#define MUX_GDR_SEL_SCLKMPLL 0x0
-#define MUX_GDR_SEL_SCLKAPLL 0x1
-#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
-
-/* CLK_DIV_RIGHTBUS */
-#define GPR_RATIO 0x1
-#define GDR_RATIO 0x3
-#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
-
-/* CLK_SRS_FSYS: 6 = SCLKMPLL */
-#define SATA_SEL_SCLKMPLL 0
-#define SATA_SEL_SCLKAPLL 1
-
-#define MMC_SEL_XXTI 0
-#define MMC_SEL_XUSBXTI 1
-#define MMC_SEL_SCLK_HDMI24M 2
-#define MMC_SEL_SCLK_USBPHY0 3
-#define MMC_SEL_SCLK_USBPHY1 4
-#define MMC_SEL_SCLK_HDMIPHY 5
-#define MMC_SEL_SCLKMPLL 6
-#define MMC_SEL_SCLKEPLL 7
-#define MMC_SEL_SCLKVPLL 8
-
-#define MMCC0_SEL MMC_SEL_SCLKMPLL
-#define MMCC1_SEL MMC_SEL_SCLKMPLL
-#define MMCC2_SEL MMC_SEL_SCLKMPLL
-#define MMCC3_SEL MMC_SEL_SCLKMPLL
-#define MMCC4_SEL MMC_SEL_SCLKMPLL
-#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
- | (MMCC4_SEL << 16) \
- | (MMCC3_SEL << 12) \
- | (MMCC2_SEL << 8) \
- | (MMCC1_SEL << 4) \
- | (MMCC0_SEL << 0))
-
-/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
-/* CLK_DIV_FSYS1 */
-#define MMC0_RATIO 0xF
-#define MMC0_PRE_RATIO 0x0
-#define MMC1_RATIO 0xF
-#define MMC1_PRE_RATIO 0x0
-#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
- | (MMC1_RATIO << 16) \
- | (MMC0_PRE_RATIO << 8) \
- | (MMC0_RATIO << 0))
-
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO 0xF
-#define MMC2_PRE_RATIO 0x0
-#define MMC3_RATIO 0xF
-#define MMC3_PRE_RATIO 0x0
-#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
- | (MMC3_RATIO << 16) \
- | (MMC2_PRE_RATIO << 8) \
- | (MMC2_RATIO << 0))
-
-/* CLK_DIV_FSYS3 */
-#define MMC4_RATIO 0xF
-#define MMC4_PRE_RATIO 0x0
-#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
- | (MMC4_RATIO << 0))
-
-/* CLK_SRC_PERIL0 */
-#define UART_SEL_XXTI 0
-#define UART_SEL_XUSBXTI 1
-#define UART_SEL_SCLK_HDMI24M 2
-#define UART_SEL_SCLK_USBPHY0 3
-#define UART_SEL_SCLK_USBPHY1 4
-#define UART_SEL_SCLK_HDMIPHY 5
-#define UART_SEL_SCLKMPLL 6
-#define UART_SEL_SCLKEPLL 7
-#define UART_SEL_SCLKVPLL 8
-
-#define UART0_SEL UART_SEL_SCLKMPLL
-#define UART1_SEL UART_SEL_SCLKMPLL
-#define UART2_SEL UART_SEL_SCLKMPLL
-#define UART3_SEL UART_SEL_SCLKMPLL
-#define UART4_SEL UART_SEL_SCLKMPLL
-#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL << 0))
-
-/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
-/* CLK_DIV_PERIL0 */
-#define UART0_RATIO 7
-#define UART1_RATIO 7
-#define UART2_RATIO 7
-#define UART3_RATIO 7
-#define UART4_RATIO 7
-#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
- | (UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO << 0))
-
-/* Clock Source CAM/FIMC */
-/* CLK_SRC_CAM */
-#define CAM0_SEL_XUSBXTI 1
-#define CAM1_SEL_XUSBXTI 1
-#define CSIS0_SEL_XUSBXTI 1
-#define CSIS1_SEL_XUSBXTI 1
-
-#define FIMC_SEL_SCLKMPLL 6
-#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
-#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
-
-#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
- | (CSIS0_SEL_XUSBXTI << 24) \
- | (CAM1_SEL_XUSBXTI << 20) \
- | (CAM0_SEL_XUSBXTI << 16) \
- | (FIMC3_LCLK_SEL << 12) \
- | (FIMC2_LCLK_SEL << 8) \
- | (FIMC1_LCLK_SEL << 4) \
- | (FIMC0_LCLK_SEL << 0))
-
-/* SCLK CAM */
-/* CLK_DIV_CAM */
-#define FIMC0_LCLK_RATIO 4
-#define FIMC1_LCLK_RATIO 4
-#define FIMC2_LCLK_RATIO 4
-#define FIMC3_LCLK_RATIO 4
-#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
- | (FIMC2_LCLK_RATIO << 8) \
- | (FIMC1_LCLK_RATIO << 4) \
- | (FIMC0_LCLK_RATIO << 0))
-
-/* SCLK MFC */
-/* CLK_SRC_MFC */
-#define MFC_SEL_MPLL 0
-#define MOUTMFC_0 0
-#define MFC_SEL MOUTMFC_0
-#define MFC_0_SEL MFC_SEL_MPLL
-#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
-
-
-/* CLK_DIV_MFC */
-#define MFC_RATIO 3
-#define CLK_DIV_MFC_VAL (MFC_RATIO)
-
-/* SCLK G3D */
-/* CLK_SRC_G3D */
-#define G3D_SEL_MPLL 0
-#define MOUTG3D_0 0
-#define G3D_SEL MOUTG3D_0
-#define G3D_0_SEL G3D_SEL_MPLL
-#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
-
-/* CLK_DIV_G3D */
-#define G3D_RATIO 1
-#define CLK_DIV_G3D_VAL (G3D_RATIO)
-
-/* SCLK LCD0 */
-/* CLK_SRC_LCD0 */
-#define FIMD_SEL_SCLKMPLL 6
-#define MDNIE0_SEL_XUSBXTI 1
-#define MDNIE_PWM0_SEL_XUSBXTI 1
-#define MIPI0_SEL_XUSBXTI 1
-#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
- | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
- | (MDNIE0_SEL_XUSBXTI << 4) \
- | (FIMD_SEL_SCLKMPLL << 0))
-
-/* CLK_DIV_LCD0 */
-#define FIMD0_RATIO 4
-#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
-
-/* Required period to generate a stable clock output */
-/* PLL_LOCK_TIME */
-#define PLL_LOCKTIME 0x1C20
-
-/* PLL Values */
-#define DISABLE 0
-#define ENABLE 1
-#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
- | (mdiv << 16) \
- | (pdiv << 8) \
- | (sdiv << 0))
-
-/* APLL_CON0 */
-#define APLL_MDIV 0xFA
-#define APLL_PDIV 0x6
-#define APLL_SDIV 0x1
-#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
-
-/* APLL_CON1 */
-#define APLL_AFC_ENB 0x1
-#define APLL_AFC 0xC
-#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
-
-/* MPLL_CON0 */
-#define MPLL_MDIV 0xC8
-#define MPLL_PDIV 0x6
-#define MPLL_SDIV 0x1
-#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
-
-/* MPLL_CON1 */
-#define MPLL_AFC_ENB 0x0
-#define MPLL_AFC 0x1C
-#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
-
-/* EPLL_CON0 */
-#define EPLL_MDIV 0x30
-#define EPLL_PDIV 0x3
-#define EPLL_SDIV 0x2
-#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
-
-/* EPLL_CON1 */
-#define EPLL_K 0x0
-#define EPLL_CON1_VAL (EPLL_K >> 0)
-
-/* VPLL_CON0 */
-#define VPLL_MDIV 0x35
-#define VPLL_PDIV 0x3
-#define VPLL_SDIV 0x2
-#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
-
-/* VPLL_CON1 */
-#define VPLL_SSCG_EN DISABLE
-#define VPLL_SEL_PF_DN_SPREAD 0x0
-#define VPLL_MRR 0x11
-#define VPLL_MFR 0x0
-#define VPLL_K 0x400
-#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
- | (VPLL_SEL_PF_DN_SPREAD << 29) \
- | (VPLL_MRR << 24) \
- | (VPLL_MFR << 16) \
- | (VPLL_K << 0))
-/*
- * UART GPIO_A0/GPIO_A1 Control Register Value
- * 0x2: UART Function
- */
-#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
-#define EXYNOS4_GPIO_A1_CON_VAL 0x222222
-
-/* ULCON: UART Line Control Value 8N1 */
-#define WORD_LEN_5_BIT 0x00
-#define WORD_LEN_6_BIT 0x01
-#define WORD_LEN_7_BIT 0x02
-#define WORD_LEN_8_BIT 0x03
-
-#define STOP_BIT_1 0x00
-#define STOP_BIT_2 0x01
-
-#define NO_PARITY 0x00
-#define ODD_PARITY 0x4
-#define EVEN_PARITY 0x5
-#define FORCED_PARITY_CHECK_AS_1 0x6
-#define FORCED_PARITY_CHECK_AS_0 0x7
-
-#define INFRAMODE_NORMAL 0x00
-#define INFRAMODE_INFRARED 0x01
-
-#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \
- | (NO_PARITY << 3) \
- | (STOP_BIT_1 << 2) \
- | (WORD_LEN_8_BIT << 0))
-
-/*
- * UCON: UART Control Value
- * Tx_interrupt Type: Level
- * Rx_interrupt Type: Level
- * Rx Timeout Enabled: Yes
- * Rx-Error Atatus_Int Enable: Yes
- * Loop_Back: No
- * Break Signal: No
- * Transmit mode : Interrupt request/polling
- * Receive mode : Interrupt request/polling
- */
-#define TX_PULSE_INTERRUPT 0
-#define TX_LEVEL_INTERRUPT 1
-#define RX_PULSE_INTERRUPT 0
-#define RX_LEVEL_INTERRUPT 1
-
-#define RX_TIME_OUT ENABLE
-#define RX_ERROR_STATE_INT_ENB ENABLE
-#define LOOP_BACK DISABLE
-#define BREAK_SIGNAL DISABLE
-
-#define TX_MODE_DISABLED 0X00
-#define TX_MODE_IRQ_OR_POLL 0X01
-#define TX_MODE_DMA 0X02
-
-#define RX_MODE_DISABLED 0X00
-#define RX_MODE_IRQ_OR_POLL 0X01
-#define RX_MODE_DMA 0X02
-
-#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \
- | (RX_LEVEL_INTERRUPT << 8) \
- | (RX_TIME_OUT << 7) \
- | (RX_ERROR_STATE_INT_ENB << 6) \
- | (LOOP_BACK << 5) \
- | (BREAK_SIGNAL << 4) \
- | (TX_MODE_IRQ_OR_POLL << 2) \
- | (RX_MODE_IRQ_OR_POLL << 0))
-
-/*
- * UFCON: UART FIFO Control Value
- * Tx FIFO Trigger LEVEL: 2 Bytes (001)
- * Rx FIFO Trigger LEVEL: 2 Bytes (001)
- * Tx Fifo Reset: No
- * Rx Fifo Reset: No
- * FIFO Enable: Yes
- */
-#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00
-#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1
-#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2
-#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3
-#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4
-#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5
-#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6
-#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
-
-#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0
-#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1
-#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2
-#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3
-#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4
-#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5
-#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6
-#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
-
-#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES
-#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES
-#define TX_FIFO_RESET DISABLE
-#define RX_FIFO_RESET DISABLE
-#define FIFO_ENABLE ENABLE
-#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \
- | (RX_FIFO_TRIGGER_LEVEL << 4) \
- | (TX_FIFO_RESET << 2) \
- | (RX_FIFO_RESET << 1) \
- | (FIFO_ENABLE << 0))
-/*
- * Baud Rate Division Value
- * 115200 BAUD:
- * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
- * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
- */
-#define UBRDIV_VAL 0x35
-
-/*
- * Fractional Part of Baud Rate Divisor:
- * 115200 BAUD:
- * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
- * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
- */
-#define UFRACVAL_VAL 0x4
-#endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index f2c32ee..9412e37 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -24,10 +24,6 @@
LIB = $(obj)lib$(BOARD).o
-SOBJS := lowlevel_init.o
-
-COBJS := clock_init.o
-COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
@@ -38,14 +34,10 @@
endif
endif
-ifdef CONFIG_SPL_BUILD
-COBJS += spl_boot.o
-endif
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
-ALL := $(obj).depend $(LIB)
+ALL := $(obj).depend $(LIB)
all: $(ALL)
diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c
deleted file mode 100644
index b288e66..0000000
--- a/board/samsung/smdk5250/clock_init.c
+++ /dev/null
@@ -1,684 +0,0 @@
-/*
- * Clock setup for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/dwmmc.h>
-
-#include "clock_init.h"
-#include "setup.h"
-
-#define FSYS1_MMC0_DIV_MASK 0xff0f
-#define FSYS1_MMC0_DIV_VAL 0x0701
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct arm_clk_ratios arm_clk_ratios[] = {
- {
- .arm_freq_mhz = 600,
-
- .apll_mdiv = 0xc8,
- .apll_pdiv = 0x4,
- .apll_sdiv = 0x1,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x2,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x1,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 800,
-
- .apll_mdiv = 0x64,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x3,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1000,
-
- .apll_mdiv = 0x7d,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x4,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1200,
-
- .apll_mdiv = 0x96,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x5,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1400,
-
- .apll_mdiv = 0xaf,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1700,
-
- .apll_mdiv = 0x1a9,
- .apll_pdiv = 0x6,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }
-};
-struct mem_timings mem_timings[] = {
- {
- .mem_manuf = MEM_MANUF_ELPIDA,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x2,
- .gpll_mdiv = 0x215,
- .gpll_pdiv = 0xc,
- .gpll_sdiv = 0x1,
- .epll_mdiv = 0x60,
- .epll_pdiv = 0x3,
- .epll_sdiv = 0x3,
- .vpll_mdiv = 0x96,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
-
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
- .pclk_cdrex_ratio = 0x5,
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010042, 0x00000d70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a44,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x4,
- .phy1_tFS = 0x4,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x7,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 0,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_ENABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGx_CHIP_COL_10 |
- DMC_MEMCONFIGx_CHIP_ROW_15 |
- DMC_MEMCONFIGx_CHIP_BANK_8,
- .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
- .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 2,
- .chips_per_channel = 2,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .impedance = IMP_OUTPUT_DRV_30_OHM,
- .gate_leveling_enable = 0,
- }, {
- .mem_manuf = MEM_MANUF_SAMSUNG,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x2,
- .gpll_mdiv = 0x215,
- .gpll_pdiv = 0xc,
- .gpll_sdiv = 0x1,
- .epll_mdiv = 0x60,
- .epll_pdiv = 0x3,
- .epll_sdiv = 0x3,
- .vpll_mdiv = 0x96,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
-
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
- .pclk_cdrex_ratio = 0x5,
- .direct_cmd_msr = {
- 0x00020018, 0x00030000, 0x00010000, 0x00000d70
- },
- .timing_ref = 0x000000bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a44,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
- .phy0_tFS = 0x8,
- .phy1_tFS = 0x8,
- .phy0_pulld_dqs = 0xf,
- .phy1_pulld_dqs = 0xf,
-
- .lpddr3_ctrl_phy_reset = 0x1,
- .ctrl_start_point = 0x10,
- .ctrl_inc = 0x10,
- .ctrl_start = 0x1,
- .ctrl_dll_on = 0x1,
- .ctrl_ref = 0x8,
-
- .ctrl_force = 0x1a,
- .ctrl_rdlat = 0x0b,
- .ctrl_bstlen = 0x08,
-
- .fp_resync = 0x8,
- .iv_size = 0x7,
- .dfi_init_start = 1,
- .aref_en = 1,
-
- .rd_fetch = 0x3,
-
- .zq_mode_dds = 0x5,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 1,
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 8
- * Number of chips: 1
- * Memory Bus width: 32 bit
- * Memory Type: DDR3
- * Additional Latancy for PLL: 0 Cycle
- */
- .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
- DMC_MEMCONTROL_DPWRDN_DISABLE |
- DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
- DMC_MEMCONTROL_TP_DISABLE |
- DMC_MEMCONTROL_DSREF_ENABLE |
- DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
- DMC_MEMCONTROL_MEM_TYPE_DDR3 |
- DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_1 |
- DMC_MEMCONTROL_BL_8 |
- DMC_MEMCONTROL_PZQ_DISABLE |
- DMC_MEMCONTROL_MRR_BYTE_7_0,
- .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
- DMC_MEMCONFIGx_CHIP_COL_10 |
- DMC_MEMCONFIGx_CHIP_ROW_15 |
- DMC_MEMCONFIGx_CHIP_BANK_8,
- .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
- .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
- .prechconfig_tp_cnt = 0xff,
- .dpwrdn_cyc = 0xff,
- .dsref_cyc = 0xffff,
- .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
- DMC_CONCONTROL_TIMEOUT_LEVEL0 |
- DMC_CONCONTROL_RD_FETCH_DISABLE |
- DMC_CONCONTROL_EMPTY_DISABLE |
- DMC_CONCONTROL_AREF_EN_DISABLE |
- DMC_CONCONTROL_IO_PD_CON_DISABLE,
- .dmc_channels = 2,
- .chips_per_channel = 2,
- .chips_to_configure = 1,
- .send_zq_init = 1,
- .impedance = IMP_OUTPUT_DRV_40_OHM,
- .gate_leveling_enable = 1,
- }
-};
-
-/**
- * Get the required memory type and speed (SPL version).
- *
- * In SPL we have no device tree, so we use the machine parameters
- *
- * @param mem_type Returns memory type
- * @param frequency_mhz Returns memory speed in MHz
- * @param arm_freq Returns ARM clock speed in MHz
- * @param mem_manuf Return Memory Manufacturer name
- * @return 0 if all ok
- */
-static int clock_get_mem_selection(enum ddr_mode *mem_type,
- unsigned *frequency_mhz, unsigned *arm_freq,
- enum mem_manuf *mem_manuf)
-{
- struct spl_machine_param *params;
-
- params = spl_get_machine_params();
- *mem_type = params->mem_type;
- *frequency_mhz = params->frequency_mhz;
- *arm_freq = params->arm_freq_mhz;
- *mem_manuf = params->mem_manuf;
-
- return 0;
-}
-
-/* Get the ratios for setting ARM clock */
-struct arm_clk_ratios *get_arm_ratios(void)
-{
- struct arm_clk_ratios *arm_ratio;
- enum ddr_mode mem_type;
- enum mem_manuf mem_manuf;
- unsigned frequency_mhz, arm_freq;
- int i;
-
- if (clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf))
- ;
- for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
- i++, arm_ratio++) {
- if (arm_ratio->arm_freq_mhz == arm_freq)
- return arm_ratio;
- }
-
- /* will hang if failed to find clock ratio */
- while (1)
- ;
-
- return NULL;
-}
-
-struct mem_timings *clock_get_mem_timings(void)
-{
- struct mem_timings *mem;
- enum ddr_mode mem_type;
- enum mem_manuf mem_manuf;
- unsigned frequency_mhz, arm_freq;
- int i;
-
- if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
- &arm_freq, &mem_manuf)) {
- for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
- i++, mem++) {
- if (mem->mem_type == mem_type &&
- mem->frequency_mhz == frequency_mhz &&
- mem->mem_manuf == mem_manuf)
- return mem;
- }
- }
-
- /* will hang if failed to find memory timings */
- while (1)
- ;
-
- return NULL;
-}
-
-void system_clock_init()
-{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
- struct mem_timings *mem;
- struct arm_clk_ratios *arm_clk_ratio;
- u32 val, tmp;
-
- mem = clock_get_mem_timings();
- arm_clk_ratio = get_arm_ratios();
-
- clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | MUX_APLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_core1);
- } while ((val | MUX_MPLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
- tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
- | MUX_GPLL_SEL_MASK;
- do {
- val = readl(&clk->mux_stat_top2);
- } while ((val | tmp) != val);
-
- clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cdrex);
- } while ((val | MUX_BPLL_SEL_MASK) != val);
-
- /* PLL locktime */
- writel(APLL_LOCK_VAL, &clk->apll_lock);
-
- writel(MPLL_LOCK_VAL, &clk->mpll_lock);
-
- writel(BPLL_LOCK_VAL, &clk->bpll_lock);
-
- writel(CPLL_LOCK_VAL, &clk->cpll_lock);
-
- writel(GPLL_LOCK_VAL, &clk->gpll_lock);
-
- writel(EPLL_LOCK_VAL, &clk->epll_lock);
-
- writel(VPLL_LOCK_VAL, &clk->vpll_lock);
-
- writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
-
- writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | HPM_SEL_SCLK_MPLL) != val);
-
- val = arm_clk_ratio->arm2_ratio << 28
- | arm_clk_ratio->apll_ratio << 24
- | arm_clk_ratio->pclk_dbg_ratio << 20
- | arm_clk_ratio->atb_ratio << 16
- | arm_clk_ratio->periph_ratio << 12
- | arm_clk_ratio->acp_ratio << 8
- | arm_clk_ratio->cpud_ratio << 4
- | arm_clk_ratio->arm_ratio;
- writel(val, &clk->div_cpu0);
- do {
- val = readl(&clk->div_stat_cpu0);
- } while (0 != val);
-
- writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
- do {
- val = readl(&clk->div_stat_cpu1);
- } while (0 != val);
-
- /* Set APLL */
- writel(APLL_CON1_VAL, &clk->apll_con1);
- val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
- arm_clk_ratio->apll_sdiv);
- writel(val, &clk->apll_con0);
- while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
- ;
-
- /* Set MPLL */
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
- writel(val, &clk->mpll_con0);
- while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set BPLL */
- writel(BPLL_CON1_VAL, &clk->bpll_con1);
- val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
- writel(val, &clk->bpll_con0);
- while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set CPLL */
- writel(CPLL_CON1_VAL, &clk->cpll_con1);
- val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
- writel(val, &clk->cpll_con0);
- while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set GPLL */
- writel(GPLL_CON1_VAL, &clk->gpll_con1);
- val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
- writel(val, &clk->gpll_con0);
- while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set EPLL */
- writel(EPLL_CON2_VAL, &clk->epll_con2);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
- writel(val, &clk->epll_con0);
- while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set VPLL */
- writel(VPLL_CON2_VAL, &clk->vpll_con2);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
- writel(val, &clk->vpll_con0);
- while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
- ;
-
- writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
- writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
- while (readl(&clk->div_stat_core0) != 0)
- ;
-
- writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
- while (readl(&clk->div_stat_core1) != 0)
- ;
-
- writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
- while (readl(&clk->div_stat_sysrgt) != 0)
- ;
-
- writel(CLK_DIV_ACP_VAL, &clk->div_acp);
- while (readl(&clk->div_stat_acp) != 0)
- ;
-
- writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
- while (readl(&clk->div_stat_syslft) != 0)
- ;
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(TOP2_VAL, &clk->src_top2);
- writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
-
- writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
- while (readl(&clk->div_stat_top0))
- ;
-
- writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
- while (readl(&clk->div_stat_top1))
- ;
-
- writel(CLK_SRC_LEX_VAL, &clk->src_lex);
- while (1) {
- val = readl(&clk->mux_stat_lex);
- if (val == (val | 1))
- break;
- }
-
- writel(CLK_DIV_LEX_VAL, &clk->div_lex);
- while (readl(&clk->div_stat_lex))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
- while (readl(&clk->div_stat_r1x))
- ;
-
- writel(CLK_REG_DISABLE, &clk->src_cdrex);
-
- writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
- while (readl(&clk->div_stat_cdrex))
- ;
-
- val = readl(&clk->src_cpu);
- val |= CLK_SRC_CPU_VAL;
- writel(val, &clk->src_cpu);
-
- val = readl(&clk->src_top2);
- val |= CLK_SRC_TOP2_VAL;
- writel(val, &clk->src_top2);
-
- val = readl(&clk->src_core1);
- val |= CLK_SRC_CORE1_VAL;
- writel(val, &clk->src_core1);
-
- writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
- writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
- while (readl(&clk->div_stat_fsys0))
- ;
-
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
-
- writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
- writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
-
- writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
- writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
- writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
- writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
-
- writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
- writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
- writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
- writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
- writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
-
- /* FIMD1 SRC CLK SELECTION */
- writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
-
- val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
- | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
- | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
- | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
- writel(val, &clk->div_fsys2);
-}
-
-void clock_init_dp_clock(void)
-{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
- /* DP clock enable */
- setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
-
- /* We run DP at 267 Mhz */
- setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
-}
-
-/*
- * Set clock divisor value for booting from EMMC.
- * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
- */
-void emmc_boot_clk_div_set(void)
-{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
- unsigned int div_mmc;
-
- div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
- div_mmc |= FSYS1_MMC0_DIV_VAL;
- writel(div_mmc, (unsigned int) &clk->div_fsys1);
-}
diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h
deleted file mode 100644
index 20a1d47..0000000
--- a/board/samsung/smdk5250/clock_init.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Clock initialization routines
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __EXYNOS_CLOCK_INIT_H
-#define __EXYNOS_CLOCK_INIT_H
-
-enum {
- MEM_TIMINGS_MSR_COUNT = 4,
-};
-
-/* These are the ratio's for configuring ARM clock */
-struct arm_clk_ratios {
- unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
-
- unsigned apll_mdiv;
- unsigned apll_pdiv;
- unsigned apll_sdiv;
-
- unsigned arm2_ratio;
- unsigned apll_ratio;
- unsigned pclk_dbg_ratio;
- unsigned atb_ratio;
- unsigned periph_ratio;
- unsigned acp_ratio;
- unsigned cpud_ratio;
- unsigned arm_ratio;
-};
-
-/* These are the memory timings for a particular memory type and speed */
-struct mem_timings {
- enum mem_manuf mem_manuf; /* Memory manufacturer */
- enum ddr_mode mem_type; /* Memory type */
- unsigned frequency_mhz; /* Frequency of memory in MHz */
-
- /* Here follow the timing parameters for the selected memory */
- unsigned apll_mdiv;
- unsigned apll_pdiv;
- unsigned apll_sdiv;
- unsigned mpll_mdiv;
- unsigned mpll_pdiv;
- unsigned mpll_sdiv;
- unsigned cpll_mdiv;
- unsigned cpll_pdiv;
- unsigned cpll_sdiv;
- unsigned gpll_mdiv;
- unsigned gpll_pdiv;
- unsigned gpll_sdiv;
- unsigned epll_mdiv;
- unsigned epll_pdiv;
- unsigned epll_sdiv;
- unsigned vpll_mdiv;
- unsigned vpll_pdiv;
- unsigned vpll_sdiv;
- unsigned bpll_mdiv;
- unsigned bpll_pdiv;
- unsigned bpll_sdiv;
- unsigned pclk_cdrex_ratio;
- unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
-
- unsigned timing_ref;
- unsigned timing_row;
- unsigned timing_data;
- unsigned timing_power;
-
- /* DQS, DQ, DEBUG offsets */
- unsigned phy0_dqs;
- unsigned phy1_dqs;
- unsigned phy0_dq;
- unsigned phy1_dq;
- unsigned phy0_tFS;
- unsigned phy1_tFS;
- unsigned phy0_pulld_dqs;
- unsigned phy1_pulld_dqs;
-
- unsigned lpddr3_ctrl_phy_reset;
- unsigned ctrl_start_point;
- unsigned ctrl_inc;
- unsigned ctrl_start;
- unsigned ctrl_dll_on;
- unsigned ctrl_ref;
-
- unsigned ctrl_force;
- unsigned ctrl_rdlat;
- unsigned ctrl_bstlen;
-
- unsigned fp_resync;
- unsigned iv_size;
- unsigned dfi_init_start;
- unsigned aref_en;
-
- unsigned rd_fetch;
-
- unsigned zq_mode_dds;
- unsigned zq_mode_term;
- unsigned zq_mode_noterm; /* 1 to allow termination disable */
-
- unsigned memcontrol;
- unsigned memconfig;
-
- unsigned membaseconfig0;
- unsigned membaseconfig1;
- unsigned prechconfig_tp_cnt;
- unsigned dpwrdn_cyc;
- unsigned dsref_cyc;
- unsigned concontrol;
- /* Channel and Chip Selection */
- uint8_t dmc_channels; /* number of memory channels */
- uint8_t chips_per_channel; /* number of chips per channel */
- uint8_t chips_to_configure; /* number of chips to configure */
- uint8_t send_zq_init; /* 1 to send this command */
- unsigned impedance; /* drive strength impedeance */
- uint8_t gate_leveling_enable; /* check gate leveling is enabled */
-};
-
-/**
- * Get the correct memory timings for our selected memory type and speed.
- *
- * This function can be called from SPL or the main U-Boot.
- *
- * @return pointer to the memory timings that we should use
- */
-struct mem_timings *clock_get_mem_timings(void);
-
-/*
- * Initialize clock for the device
- */
-void system_clock_init(void);
-
-/*
- * Set clock divisor value for booting from EMMC.
- */
-void emmc_boot_clk_div_set(void);
-#endif
diff --git a/board/samsung/smdk5250/dmc_common.c b/board/samsung/smdk5250/dmc_common.c
deleted file mode 100644
index 109602a..0000000
--- a/board/samsung/smdk5250/dmc_common.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Mem setup common file for different types of DDR present on SMDK5250 boards.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/spl.h>
-
-#include "clock_init.h"
-#include "setup.h"
-
-#define ZQ_INIT_TIMEOUT 10000
-
-int dmc_config_zq(struct mem_timings *mem,
- struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl)
-{
- unsigned long val = 0;
- int i;
-
- /*
- * ZQ Calibration:
- * Select Driver Strength,
- * long calibration for manual calibration
- */
- val = PHY_CON16_RESET_VAL;
- val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
- val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
- val |= ZQ_CLK_DIV_EN;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-
- /* Disable termination */
- if (mem->zq_mode_noterm)
- val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-
- /* ZQ_MANUAL_START: Enable */
- val |= ZQ_MANUAL_STR;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-
- /* ZQ_MANUAL_START: Disable */
- val &= ~ZQ_MANUAL_STR;
-
- /*
- * Since we are manaully calibrating the ZQ values,
- * we are looping for the ZQ_init to complete.
- */
- i = ZQ_INIT_TIMEOUT;
- while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
- i--;
- }
- if (!i)
- return -1;
- writel(val, &phy0_ctrl->phy_con16);
-
- i = ZQ_INIT_TIMEOUT;
- while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
- i--;
- }
- if (!i)
- return -1;
- writel(val, &phy1_ctrl->phy_con16);
-
- return 0;
-}
-
-void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
-{
- unsigned long val;
-
- if (mode == DDR_MODE_DDR3) {
- val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
- writel(val, &dmc->phycontrol0);
- }
-
- /* Update DLL Information: Force DLL Resyncronization */
- val = readl(&dmc->phycontrol0);
- val |= FP_RSYNC;
- writel(val, &dmc->phycontrol0);
-
- /* Reset Force DLL Resyncronization */
- val = readl(&dmc->phycontrol0);
- val &= ~FP_RSYNC;
- writel(val, &dmc->phycontrol0);
-}
-
-void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
-{
- int channel, chip;
-
- for (channel = 0; channel < mem->dmc_channels; channel++) {
- unsigned long mask;
-
- mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
- for (chip = 0; chip < mem->chips_to_configure; chip++) {
- int i;
-
- mask |= chip << DIRECT_CMD_CHIP_SHIFT;
-
- /* Sending NOP command */
- writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
-
- /*
- * TODO(alim.akhtar@samsung.com): Do we need these
- * delays? This one and the next were not there for
- * DDR3.
- */
- sdelay(0x10000);
-
- /* Sending EMRS/MRS commands */
- for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
- writel(mem->direct_cmd_msr[i] | mask,
- &dmc->directcmd);
- sdelay(0x10000);
- }
-
- if (mem->send_zq_init) {
- /* Sending ZQINIT command */
- writel(DIRECT_CMD_ZQINIT | mask,
- &dmc->directcmd);
-
- sdelay(10000);
- }
- }
- }
-}
-
-void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
-{
- int channel, chip;
-
- for (channel = 0; channel < mem->dmc_channels; channel++) {
- unsigned long mask;
-
- mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
- for (chip = 0; chip < mem->chips_per_channel; chip++) {
- mask |= chip << DIRECT_CMD_CHIP_SHIFT;
-
- /* PALL (all banks precharge) CMD */
- writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
- sdelay(0x10000);
- }
- }
-}
-
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
-{
- writel(mem->memconfig, &dmc->memconfig0);
- writel(mem->memconfig, &dmc->memconfig1);
- writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
- writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
-}
-
-void mem_ctrl_init()
-{
- struct spl_machine_param *param = spl_get_machine_params();
- struct mem_timings *mem;
- int ret;
-
- mem = clock_get_mem_timings();
-
- /* If there are any other memory variant, add their init call below */
- if (param->mem_type == DDR_MODE_DDR3) {
- ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
- if (ret) {
- /* will hang if failed to init memory control */
- while (1)
- ;
- }
- } else {
- /* will hang if unknow memory type */
- while (1)
- ;
- }
-}
diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c b/board/samsung/smdk5250/dmc_init_ddr3.c
deleted file mode 100644
index e050790..0000000
--- a/board/samsung/smdk5250/dmc_init_ddr3.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dmc.h>
-#include "setup.h"
-#include "clock_init.h"
-
-#define RDLVL_COMPLETE_TIMEOUT 10000
-
-static void reset_phy_ctrl(void)
-{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
- writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
- writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
-}
-
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
-{
- unsigned int val;
- struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
- struct exynos5_dmc *dmc;
- int i;
-
- phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
- phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
- dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
-
- reset_phy_ctrl();
-
- /* Set Impedance Output Driver */
- val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
- (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
- (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
- (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
- writel(val, &phy0_ctrl->phy_con39);
- writel(val, &phy1_ctrl->phy_con39);
-
- /* Set Read Latency and Burst Length for PHY0 and PHY1 */
- val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
- (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
- writel(val, &phy0_ctrl->phy_con42);
- writel(val, &phy1_ctrl->phy_con42);
-
- /* ZQ Calibration */
- if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
- return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
-
- /* DQ Signal */
- writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
- writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
-
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
- | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
- &dmc->concontrol);
-
- update_reset_dll(dmc, DDR_MODE_DDR3);
-
- /* DQS Signal */
- writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
- writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
-
- writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
- writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
-
- writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
- writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
-
- val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- /* Start DLL locking */
- writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
- &phy0_ctrl->phy_con12);
- writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
- &phy1_ctrl->phy_con12);
-
- update_reset_dll(dmc, DDR_MODE_DDR3);
-
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
- &dmc->concontrol);
-
- /* Memory Channel Inteleaving Size */
- writel(mem->iv_size, &dmc->ivcontrol);
-
- writel(mem->memconfig, &dmc->memconfig0);
- writel(mem->memconfig, &dmc->memconfig1);
- writel(mem->membaseconfig0, &dmc->membaseconfig0);
- writel(mem->membaseconfig1, &dmc->membaseconfig1);
-
- /* Precharge Configuration */
- writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
- &dmc->prechconfig);
-
- /* Power Down mode Configuration */
- writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
- mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
- &dmc->pwrdnconfig);
-
- /* TimingRow, TimingData, TimingPower and Timingaref
- * values as per Memory AC parameters
- */
- writel(mem->timing_ref, &dmc->timingref);
- writel(mem->timing_row, &dmc->timingrow);
- writel(mem->timing_data, &dmc->timingdata);
- writel(mem->timing_power, &dmc->timingpower);
-
- /* Send PALL command */
- dmc_config_prech(mem, dmc);
-
- /* Send NOP, MRS and ZQINIT commands */
- dmc_config_mrs(mem, dmc);
-
- if (mem->gate_leveling_enable) {
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- val |= BYTE_RDLVL_EN;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = (mem->ctrl_start_point <<
- PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
- (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- val = PHY_CON2_RESET_VAL;
- val |= INIT_DESKEW_EN;
- val |= RDLVL_GATE_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
-
- val = PHY_CON0_RESET_VAL;
- val |= P0_CMD_EN;
- val |= BYTE_RDLVL_EN;
- val |= CTRL_SHGATE;
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- val = PHY_CON1_RESET_VAL;
- val &= ~(CTRL_GATEDURADJ_MASK);
- writel(val, &phy0_ctrl->phy_con1);
- writel(val, &phy1_ctrl->phy_con1);
-
- writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
- i = RDLVL_COMPLETE_TIMEOUT;
- while ((readl(&dmc->phystatus) &
- (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
- (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
- /*
- * TODO(waihong): Comment on how long this take to
- * timeout
- */
- sdelay(100);
- i--;
- }
- if (!i)
- return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
- writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
-
- writel(0, &phy0_ctrl->phy_con14);
- writel(0, &phy1_ctrl->phy_con14);
-
- val = (mem->ctrl_start_point <<
- PHY_CON12_CTRL_START_POINT_SHIFT) |
- (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
- (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
- (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
- (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
- (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
- writel(val, &phy0_ctrl->phy_con12);
- writel(val, &phy1_ctrl->phy_con12);
-
- update_reset_dll(dmc, DDR_MODE_DDR3);
- }
-
- /* Send PALL command */
- dmc_config_prech(mem, dmc);
-
- writel(mem->memcontrol, &dmc->memcontrol);
-
- /* Set DMC Concontrol and enable auto-refresh counter */
- writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
- | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
- return 0;
-}
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
deleted file mode 100644
index eb91d13..0000000
--- a/board/samsung/smdk5250/setup.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * Machine Specific Values for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SMDK5250_SETUP_H
-#define _SMDK5250_SETUP_H
-
-#include <config.h>
-#include <asm/arch/dmc.h>
-
-/* APLL_CON1 */
-#define APLL_CON1_VAL (0x00203800)
-
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x00203800)
-
-/* CPLL_CON1 */
-#define CPLL_CON1_VAL (0x00203800)
-
-/* GPLL_CON1 */
-#define GPLL_CON1_VAL (0x00203800)
-
-/* EPLL_CON1, CON2 */
-#define EPLL_CON1_VAL 0x00000000
-#define EPLL_CON2_VAL 0x00000080
-
-/* VPLL_CON1, CON2 */
-#define VPLL_CON1_VAL 0x00000000
-#define VPLL_CON2_VAL 0x00000080
-
-/* BPLL_CON1 */
-#define BPLL_CON1_VAL 0x00203800
-
-/* Set PLL */
-#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 0
-#define MUX_CPU_SEL 0
-#define MUX_APLL_SEL 1
-
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
- | (MUX_CPU_SEL << 16) \
- | (MUX_APLL_SEL))
-
-/* MEMCONTROL register bit fields */
-#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
-#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
-#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
-#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
-#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
-#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
-#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
-
-#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
-#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
-#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
-
-#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
-
-#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
-#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
-
-#define DMC_MEMCONTROL_BL_8 (3 << 20)
-#define DMC_MEMCONTROL_BL_4 (2 << 20)
-
-#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
-
-#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
-#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
-
-/* MEMCONFIG0 register bit fields */
-#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)
-#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
-#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
-#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
-#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
-
-#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
-#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0)
-#define DMC_MEMBASECONFIG_VAL(x) ( \
- DMC_MEMBASECONFIGx_CHIP_BASE(x) | \
- DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \
-)
-
-#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
-#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
-
-#define DMC_PRECHCONFIG_VAL 0xFF000000
-#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
-
-#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
-#define DFI_INIT_START (1 << 28)
-#define EMPTY (1 << 8)
-#define AREF_EN (1 << 5)
-
-#define DFI_INIT_COMPLETE_CHO (1 << 2)
-#define DFI_INIT_COMPLETE_CH1 (1 << 3)
-
-#define RDLVL_COMPLETE_CHO (1 << 14)
-#define RDLVL_COMPLETE_CH1 (1 << 15)
-
-#define CLK_STOP_EN (1 << 0)
-#define DPWRDN_EN (1 << 1)
-#define DSREF_EN (1 << 5)
-
-/* COJCONTROL register bit fields */
-#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
-#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
-#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
-#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
-#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
-#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
-#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
-
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
- | (APLL_RATIO << 24) \
- | (PCLK_DBG_RATIO << 20) \
- | (ATB_RATIO << 16) \
- | (PERIPH_RATIO << 12) \
- | (ACP_RATIO << 8) \
- | (CPUD_RATIO << 4) \
- | (ARM_RATIO))
-
-
-/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL 0x66666
-#define CLK_DIV_FSYS0_VAL 0x0BB00000
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO 0x2
-#define COPY_RATIO 0x0
-
-/* CLK_DIV_CPU1 = 0x00000003 */
-#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
- | (COPY_RATIO))
-
-/* CLK_SRC_CORE0 */
-#define CLK_SRC_CORE0_VAL 0x00000000
-
-/* CLK_SRC_CORE1 */
-#define CLK_SRC_CORE1_VAL 0x100
-
-/* CLK_DIV_CORE0 */
-#define CLK_DIV_CORE0_VAL 0x00120000
-
-/* CLK_DIV_CORE1 */
-#define CLK_DIV_CORE1_VAL 0x07070700
-
-/* CLK_DIV_SYSRGT */
-#define CLK_DIV_SYSRGT_VAL 0x00000111
-
-/* CLK_DIV_ACP */
-#define CLK_DIV_ACP_VAL 0x12
-
-/* CLK_DIV_SYSLFT */
-#define CLK_DIV_SYSLFT_VAL 0x00000311
-
-/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_VAL 0x1
-
-/* CLK_DIV_CDREX */
-#define MCLK_CDREX2_RATIO 0x0
-#define ACLK_EFCON_RATIO 0x1
-#define MCLK_DPHY_RATIO 0x1
-#define MCLK_CDREX_RATIO 0x1
-#define ACLK_C2C_200_RATIO 0x1
-#define C2C_CLK_400_RATIO 0x1
-#define PCLK_CDREX_RATIO 0x1
-#define ACLK_CDREX_RATIO 0x1
-
-#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
- | (C2C_CLK_400_RATIO << 6) \
- | (PCLK_CDREX_RATIO << 4) \
- | (ACLK_CDREX_RATIO))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ACLK_300_GSCL_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID_SEL 0x0
-#define MUX_ACLK_400_G3D_MID_SEL 0x0
-#define MUX_ACLK_333_SEL 0x0
-#define MUX_ACLK_300_DISP1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID_SEL 0x0
-#define MUX_ACLK_200_SEL 0x0
-#define MUX_ACLK_166_SEL 0x0
-#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
- | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
- | (MUX_ACLK_400_G3D_MID_SEL << 20) \
- | (MUX_ACLK_333_SEL << 16) \
- | (MUX_ACLK_300_DISP1_SEL << 15) \
- | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
- | (MUX_ACLK_200_SEL << 12) \
- | (MUX_ACLK_166_SEL << 8))
-
-/* CLK_SRC_TOP1 */
-#define MUX_ACLK_400_G3D_SEL 0x1
-#define MUX_ACLK_400_ISP_SEL 0x0
-#define MUX_ACLK_400_IOP_SEL 0x0
-#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
-#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
- |(MUX_ACLK_400_ISP_SEL << 24) \
- |(MUX_ACLK_400_IOP_SEL << 20) \
- |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
- |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
- |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
-
-/* CLK_SRC_TOP2 */
-#define MUX_GPLL_SEL 0x1
-#define MUX_BPLL_USER_SEL 0x0
-#define MUX_MPLL_USER_SEL 0x0
-#define MUX_VPLL_SEL 0x1
-#define MUX_EPLL_SEL 0x1
-#define MUX_CPLL_SEL 0x1
-#define VPLLSRC_SEL 0x0
-#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
- | (MUX_BPLL_USER_SEL << 24) \
- | (MUX_MPLL_USER_SEL << 20) \
- | (MUX_VPLL_SEL << 16) \
- | (MUX_EPLL_SEL << 12) \
- | (MUX_CPLL_SEL << 8) \
- | (VPLLSRC_SEL))
-/* CLK_SRC_TOP3 */
-#define MUX_ACLK_333_SUB_SEL 0x1
-#define MUX_ACLK_400_SUB_SEL 0x1
-#define MUX_ACLK_266_ISP_SUB_SEL 0x1
-#define MUX_ACLK_266_GPS_SUB_SEL 0x0
-#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
-#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
-#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
- | (MUX_ACLK_400_SUB_SEL << 20) \
- | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
- | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
- | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
- | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
- | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
- | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
-
-/* CLK_DIV_TOP0 */
-#define ACLK_300_DISP1_RATIO 0x2
-#define ACLK_400_G3D_RATIO 0x0
-#define ACLK_333_RATIO 0x0
-#define ACLK_266_RATIO 0x2
-#define ACLK_200_RATIO 0x3
-#define ACLK_166_RATIO 0x1
-#define ACLK_133_RATIO 0x1
-#define ACLK_66_RATIO 0x5
-
-#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
- | (ACLK_400_G3D_RATIO << 24) \
- | (ACLK_333_RATIO << 20) \
- | (ACLK_266_RATIO << 16) \
- | (ACLK_200_RATIO << 12) \
- | (ACLK_166_RATIO << 8) \
- | (ACLK_133_RATIO << 4) \
- | (ACLK_66_RATIO))
-
-/* CLK_DIV_TOP1 */
-#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
-#define ACLK_66_PRE_RATIO 0x1
-#define ACLK_400_ISP_RATIO 0x1
-#define ACLK_400_IOP_RATIO 0x1
-#define ACLK_300_GSCL_RATIO 0x2
-
-#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
- | (ACLK_66_PRE_RATIO << 24) \
- | (ACLK_400_ISP_RATIO << 20) \
- | (ACLK_400_IOP_RATIO << 16) \
- | (ACLK_300_GSCL_RATIO << 12))
-
-/* APLL_LOCK */
-#define APLL_LOCK_VAL (0x546)
-/* MPLL_LOCK */
-#define MPLL_LOCK_VAL (0x546)
-/* CPLL_LOCK */
-#define CPLL_LOCK_VAL (0x546)
-/* GPLL_LOCK */
-#define GPLL_LOCK_VAL (0x546)
-/* EPLL_LOCK */
-#define EPLL_LOCK_VAL (0x3A98)
-/* VPLL_LOCK */
-#define VPLL_LOCK_VAL (0x3A98)
-/* BPLL_LOCK */
-#define BPLL_LOCK_VAL (0x546)
-
-#define MUX_APLL_SEL_MASK (1 << 0)
-#define MUX_MPLL_SEL_MASK (1 << 8)
-#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
-#define MUX_CPLL_SEL_MASK (1 << 8)
-#define MUX_EPLL_SEL_MASK (1 << 12)
-#define MUX_VPLL_SEL_MASK (1 << 16)
-#define MUX_GPLL_SEL_MASK (1 << 28)
-#define MUX_BPLL_SEL_MASK (1 << 0)
-#define MUX_HPM_SEL_MASK (1 << 20)
-#define HPM_SEL_SCLK_MPLL (1 << 21)
-#define APLL_CON0_LOCKED (1 << 29)
-#define MPLL_CON0_LOCKED (1 << 29)
-#define BPLL_CON0_LOCKED (1 << 29)
-#define CPLL_CON0_LOCKED (1 << 29)
-#define EPLL_CON0_LOCKED (1 << 29)
-#define GPLL_CON0_LOCKED (1 << 29)
-#define VPLL_CON0_LOCKED (1 << 29)
-#define CLK_REG_DISABLE 0x0
-#define TOP2_VAL 0x0110000
-
-/* CLK_SRC_PERIC0 */
-#define PWM_SEL 6
-#define UART3_SEL 6
-#define UART2_SEL 6
-#define UART1_SEL 6
-#define UART0_SEL 6
-/* SRC_CLOCK = SCLK_MPLL */
-#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL))
-
-/* CLK_SRC_PERIC1 */
-/* SRC_CLOCK = SCLK_MPLL */
-#define SPI0_SEL 6
-#define SPI1_SEL 6
-#define SPI2_SEL 6
-#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
- | (SPI1_SEL << 20) \
- | (SPI0_SEL << 16))
-
-/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
-#define SPI0_ISP_SEL 6
-#define SPI1_ISP_SEL 6
-#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
- | (SPI0_ISP_SEL << 0)
-
-/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
-#define SPI0_ISP_RATIO 0xf
-#define SPI1_ISP_RATIO 0xf
-#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
- | (SPI0_ISP_RATIO << 0)
-
-/* CLK_DIV_PERIL0 */
-#define UART5_RATIO 7
-#define UART4_RATIO 7
-#define UART3_RATIO 7
-#define UART2_RATIO 7
-#define UART1_RATIO 7
-#define UART0_RATIO 7
-
-#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO))
-/* CLK_DIV_PERIC1 */
-#define SPI1_RATIO 0x7
-#define SPI0_RATIO 0xf
-#define SPI1_SUB_RATIO 0x0
-#define SPI0_SUB_RATIO 0x0
-#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
- | ((SPI1_RATIO << 16) \
- | (SPI0_SUB_RATIO << 8) \
- | (SPI0_RATIO << 0)))
-
-/* CLK_DIV_PERIC2 */
-#define SPI2_RATIO 0xf
-#define SPI2_SUB_RATIO 0x0
-#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
- | (SPI2_RATIO << 0))
-
-/* CLK_DIV_PERIC3 */
-#define PWM_RATIO 8
-#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
-
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO_MASK 0xf
-#define MMC2_RATIO_VAL 0x3
-#define MMC2_RATIO_OFFSET 0
-
-#define MMC2_PRE_RATIO_MASK 0xff
-#define MMC2_PRE_RATIO_VAL 0x9
-#define MMC2_PRE_RATIO_OFFSET 8
-
-#define MMC3_RATIO_MASK 0xf
-#define MMC3_RATIO_VAL 0x1
-#define MMC3_RATIO_OFFSET 16
-
-#define MMC3_PRE_RATIO_MASK 0xff
-#define MMC3_PRE_RATIO_VAL 0x0
-#define MMC3_PRE_RATIO_OFFSET 24
-
-/* CLK_SRC_LEX */
-#define CLK_SRC_LEX_VAL 0x0
-
-/* CLK_DIV_LEX */
-#define CLK_DIV_LEX_VAL 0x10
-
-/* CLK_DIV_R0X */
-#define CLK_DIV_R0X_VAL 0x10
-
-/* CLK_DIV_L0X */
-#define CLK_DIV_R1X_VAL 0x10
-
-/* CLK_DIV_ISP0 */
-#define CLK_DIV_ISP0_VAL 0x31
-
-/* CLK_DIV_ISP1 */
-#define CLK_DIV_ISP1_VAL 0x0
-
-/* CLK_DIV_ISP2 */
-#define CLK_DIV_ISP2_VAL 0x1
-
-/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL 0x6
-
-/*
- * DIV_DISP1_0
- * For DP, divisor should be 2
- */
-#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
-
-/* CLK_GATE_IP_DISP1 */
-#define CLK_GATE_DP1_ALLOW (1 << 4)
-
-#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
-#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
-
-#define PHY_CON0_RESET_VAL 0x17020a40
-#define P0_CMD_EN (1 << 14)
-#define BYTE_RDLVL_EN (1 << 13)
-#define CTRL_SHGATE (1 << 8)
-
-#define PHY_CON1_RESET_VAL 0x09210100
-#define CTRL_GATEDURADJ_MASK (0xf << 20)
-
-#define PHY_CON2_RESET_VAL 0x00010004
-#define INIT_DESKEW_EN (1 << 6)
-#define RDLVL_GATE_EN (1 << 24)
-
-/*ZQ Configurations */
-#define PHY_CON16_RESET_VAL 0x08000304
-
-#define ZQ_CLK_DIV_EN (1 << 18)
-#define ZQ_MANUAL_STR (1 << 1)
-#define ZQ_DONE (1 << 0)
-
-#define CTRL_RDLVL_GATE_ENABLE 1
-#define CTRL_RDLVL_GATE_DISABLE 1
-
-/* Direct Command */
-#define DIRECT_CMD_NOP 0x07000000
-#define DIRECT_CMD_PALL 0x01000000
-#define DIRECT_CMD_ZQINIT 0x0a000000
-#define DIRECT_CMD_CHANNEL_SHIFT 28
-#define DIRECT_CMD_CHIP_SHIFT 20
-
-/* DMC PHY Control0 register */
-#define PHY_CONTROL0_RESET_VAL 0x0
-#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
-#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
-#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
-#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
-
-/* Driver strength for CK, CKE, CS & CA */
-#define IMP_OUTPUT_DRV_40_OHM 0x5
-#define IMP_OUTPUT_DRV_30_OHM 0x7
-#define CA_CK_DRVR_DS_OFFSET 9
-#define CA_CKE_DRVR_DS_OFFSET 6
-#define CA_CS_DRVR_DS_OFFSET 3
-#define CA_ADR_DRVR_DS_OFFSET 0
-
-#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
-#define PHY_CON42_CTRL_RDLAT_SHIFT 0
-
-struct mem_timings;
-
-/* Errors that we can encourter in low-level setup */
-enum {
- SETUP_ERR_OK,
- SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
- SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
-};
-
-/*
- * Memory variant specific initialization code
- *
- * @param mem Memory timings for this memory type.
- * @param mem_iv_size Memory interleaving size is a configurable parameter
- * which the DMC uses to decide how to split a memory
- * chunk into smaller chunks to support concurrent
- * accesses; may vary across boards.
- * @return 0 if ok, SETUP_ERR_... if there is a problem
- */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
-
-/*
- * Configure ZQ I/O interface
- *
- * @param mem Memory timings for this memory type.
- * @param phy0_ctrl Pointer to struct containing PHY0 control reg
- * @param phy1_ctrl Pointer to struct containing PHY1 control reg
- * @return 0 if ok, -1 on error
- */
-int dmc_config_zq(struct mem_timings *mem,
- struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl);
-
-/*
- * Send NOP and MRS/EMRS Direct commands
- *
- * @param mem Memory timings for this memory type.
- * @param dmc Pointer to struct of DMC registers
- */
-void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
-
-/*
- * Send PALL Direct commands
- *
- * @param mem Memory timings for this memory type.
- * @param dmc Pointer to struct of DMC registers
- */
-void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
-
-/*
- * Configure the memconfig and membaseconfig registers
- *
- * @param mem Memory timings for this memory type.
- * @param exynos5_dmc Pointer to struct of DMC registers
- */
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
-
-/*
- * Reset the DLL. This function is common between DDR3 and LPDDR2.
- * However, the reset value is different. So we are passing a flag
- * ddr_mode to distinguish between LPDDR2 and DDR3.
- *
- * @param exynos5_dmc Pointer to struct of DMC registers
- * @param ddr_mode Type of DDR memory
- */
-void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
-
-void sdelay(unsigned long);
-void mem_ctrl_init(void);
-void system_clock_init(void);
-#endif
diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c
deleted file mode 100644
index 83275f1..0000000
--- a/board/samsung/smdk5250/spl_boot.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include<common.h>
-#include<config.h>
-
-#include <asm/arch-exynos/dmc.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/spl.h>
-
-#include "clock_init.h"
-
-/* Index into irom ptr table */
-enum index {
- MMC_INDEX,
- EMMC44_INDEX,
- EMMC44_END_INDEX,
- SPI_INDEX,
- USB_INDEX,
-};
-
-/* IROM Function Pointers Table */
-u32 irom_ptr_table[] = {
- [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
- [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
- [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
- -EMMC4.4 end boot operation */
- [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
- [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
- };
-
-void *get_irom_func(int index)
-{
- return (void *)*(u32 *)irom_ptr_table[index];
-}
-
-/*
- * Set/clear program flow prediction and return the previous state.
- */
-static int config_branch_prediction(int set_cr_z)
-{
- unsigned int cr;
-
- /* System Control Register: 11th bit Z Branch prediction enable */
- cr = get_cr();
- set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
-
- return cr & CR_Z;
-}
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* Pointer to API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
- int is_cr_z_set;
- unsigned int sec_boot_check;
- enum boot_mode bootmode = BOOT_MODE_OM;
-
- u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
- u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
- u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
- void (*end_bootop_from_emmc)(void);
- u32 (*usb_copy)(void);
-
- /* Read iRAM location to check for secondary USB boot mode */
- sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
- if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
- bootmode = BOOT_MODE_USB;
-
- if (bootmode == BOOT_MODE_OM)
- bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
-
- switch (bootmode) {
- case BOOT_MODE_SERIAL:
- spi_copy = get_irom_func(SPI_INDEX);
- spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
- CONFIG_SYS_TEXT_BASE);
- break;
- case BOOT_MODE_MMC:
- copy_bl2 = get_irom_func(MMC_INDEX);
- copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
- CONFIG_SYS_TEXT_BASE);
- break;
- case BOOT_MODE_EMMC:
- /* Set the FSYS1 clock divisor value for EMMC boot */
- emmc_boot_clk_div_set();
-
- copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
- end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
-
- copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
- end_bootop_from_emmc();
- break;
- case BOOT_MODE_USB:
- /*
- * iROM needs program flow prediction to be disabled
- * before copy from USB device to RAM
- */
- is_cr_z_set = config_branch_prediction(0);
- usb_copy = get_irom_func(USB_INDEX);
- usb_copy();
- config_branch_prediction(is_cr_z_set);
- break;
- default:
- break;
- }
-}
-
-void board_init_f(unsigned long bootflag)
-{
- __attribute__((noreturn)) void (*uboot)(void);
- copy_uboot_to_ram();
-
- /* Jump to U-Boot image */
- uboot = (void *)CONFIG_SYS_TEXT_BASE;
- (*uboot)();
- /* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- /* Function attribute is no-return */
- /* This Function never executes */
- while (1)
- ;
-}
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile
index 56e0c16..c4cd0a3 100644
--- a/board/samsung/smdkv310/Makefile
+++ b/board/samsung/smdkv310/Makefile
@@ -24,18 +24,12 @@
LIB = $(obj)lib$(BOARD).o
-SOBJS := mem_setup.o
-SOBJS += lowlevel_init.o
ifndef CONFIG_SPL_BUILD
COBJS += smdkv310.o
endif
-ifdef CONFIG_SPL_BUILD
-COBJS += mmc_boot.o
-endif
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
ALL := $(obj).depend $(LIB)
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
deleted file mode 100644
index 31e0e2e..0000000
--- a/board/samsung/smdkv310/lowlevel_init.S
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
- * Lowlevel setup for SMDKV310 board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-#define MEM_DLLl_ON
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
- .globl lowlevel_init
-lowlevel_init:
- push {lr}
-
- /* r5 has always zero */
- mov r5, #0
- ldr r7, =EXYNOS4_GPIO_PART1_BASE
- ldr r6, =EXYNOS4_GPIO_PART2_BASE
-
- /* check reset status */
- ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
- ldr r1, [r0]
-
- /* AFTR wakeup reset */
- ldr r2, =S5P_CHECK_DIDLE
- cmp r1, r2
- beq exit_wakeup
-
- /* Sleep wakeup reset */
- ldr r2, =S5P_CHECK_SLEEP
- cmp r1, r2
- beq wakeup_reset
-
- /*
- * If U-boot is already running in ram, no need to relocate U-Boot.
- * Memory controller must be configured before relocating U-Boot
- * in ram.
- */
- ldr r0, =0x00ffffff /* r0 <- Mask Bits*/
- bic r1, pc, r0 /* pc <- current addr of code */
- /* r1 <- unmasked bits of pc */
-
- ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
- bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
- cmp r1, r2 /* compare r1, r2 */
- beq 1f /* r0 == r1 then skip sdram init */
-
- /* init system clock */
- bl system_clock_init
-
- /* Memory initialize */
- bl mem_ctrl_asm_init
-
-1:
- /* for UART */
- bl uart_asm_init
- bl arch_cpu_init
- bl tzpc_init
- pop {pc}
-
-wakeup_reset:
- bl system_clock_init
- bl mem_ctrl_asm_init
- bl arch_cpu_init
- bl tzpc_init
-
-exit_wakeup:
- /* Load return address and jump to kernel */
- ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
-
- /* r1 = physical address of exynos4210_cpu_resume function */
- ldr r1, [r0]
-
- /* Jump to kernel*/
- mov pc, r1
- nop
- nop
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
- push {lr}
- ldr r0, =EXYNOS4_CLOCK_BASE
-
- /* APLL(1), MPLL(1), CORE(0), HPM(0) */
- ldr r1, =0x0101
- ldr r2, =0x14200 @CLK_SRC_CPU
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x10000
-2: subs r1, r1, #1
- bne 2b
-
- ldr r1, =0x00
- ldr r2, =0x0C210 @CLK_SRC_TOP0
- str r1, [r0, r2]
-
- ldr r1, =0x00
- ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET
- str r1, [r0, r2]
-
- /* DMC */
- ldr r1, =0x00
- ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET
- str r1, [r0, r2]
-
- /*CLK_SRC_LEFTBUS */
- ldr r1, =0x00
- ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET
- str r1, [r0, r2]
-
- /*CLK_SRC_RIGHTBUS */
- ldr r1, =0x00
- ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET
- str r1, [r0, r2]
-
- /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
- ldr r1, =0x066666
- ldr r2, =0x0C240 @ CLK_SRC_FSYS
- str r1, [r0, r2]
-
- /* UART[0:4], PWM: SCLKMPLL(6) */
- ldr r1, =0x06666666
- ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x10000
-3: subs r1, r1, #1
- bne 3b
-
- /*
- * CLK_DIV_CPU0:
- *
- * PCLK_DBG_RATIO[20] 0x1
- * ATB_RATIO[16] 0x3
- * PERIPH_RATIO[12] 0x3
- * COREM1_RATIO[8] 0x7
- * COREM0_RATIO[4] 0x3
- */
- ldr r1, =0x0133730
- ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET
- str r1, [r0, r2]
-
- /* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */
- ldr r1, =0x03
- ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET
- str r1, [r0, r2]
-
- /*
- * CLK_DIV_DMC0:
- *
- * CORE_TIMERS_RATIO[28] 0x1
- * COPY2_RATIO[24] 0x3
- * DMCP_RATIO[20] 0x1
- * DMCD_RATIO[16] 0x1
- * DMC_RATIO[12] 0x1
- * DPHY_RATIO[8] 0x1
- * ACP_PCLK_RATIO[4] 0x1
- * ACP_RATIO[0] 0x3
- */
- ldr r1, =0x13111113
- ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET
- str r1, [r0, r2]
-
- /*
- * CLK_DIV_DMC1:
- *
- * DPM_RATIO[24] 0x1
- * DVSEM_RATIO[16] 0x1
- * PWI_RATIO[8] 0x1
- */
- ldr r1, =0x01010100
- ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET
- str r1, [r0, r2]
-
- /*
- * CLK_DIV_LEFRBUS:
- *
- * GPL_RATIO[4] 0x1
- * GDL_RATIO[0] 0x3
- */
- ldr r1, =0x013
- ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET
- str r1, [r0, r2]
-
- /*
- * CLK_DIV_RIGHTBUS:
- *
- * GPR_RATIO[4] 0x1
- * GDR_RATIO[0] 0x3
- */
- ldr r1, =0x013
- ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET
- str r1, [r0, r2]
-
- /*
- * CLK_DIV_TOP:
- *
- * ONENAND_RATIO[16] 0x0
- * ACLK_133_RATIO[12] 0x5
- * ACLK_160_RATIO[8] 0x4
- * ACLK_100_RATIO[4] 0x7
- * ACLK_200_RATIO[0] 0x3
- */
- ldr r1, =0x05473
- ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET
- str r1, [r0, r2]
-
- /* MMC[0:1] */
- ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C544 @ CLK_DIV_FSYS1
- str r1, [r0, r2]
-
- /* MMC[2:3] */
- ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C548 @ CLK_DIV_FSYS2
- str r1, [r0, r2]
-
- /* MMC4 */
- ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C54C @ CLK_DIV_FSYS3
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x10000
-4: subs r1, r1, #1
- bne 4b
-
- /*
- * CLK_DIV_PERIL0:
- *
- * UART5_RATIO[20] 8
- * UART4_RATIO[16] 8
- * UART3_RATIO[12] 8
- * UART2_RATIO[8] 8
- * UART1_RATIO[4] 8
- * UART0_RATIO[0] 8
- */
- ldr r1, =0x774777
- ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET
- str r1, [r0, r2]
-
- /* SLIMBUS: ???, PWM */
- ldr r1, =0x8
- ldr r2, =0x0C55C @ CLK_DIV_PERIL3
- str r1, [r0, r2]
-
- /* Set PLL locktime */
- ldr r1, =0x01C20
- ldr r2, =0x014000 @APLL_LOCK_OFFSET
- str r1, [r0, r2]
- ldr r1, =0x01C20
- ldr r2, =0x014008 @MPLL_LOCK_OFFSET
- str r1, [r0, r2]
- ldr r1, =0x01C20
- ldr r2, =0x0C010 @EPLL_LOCK_OFFSET
- str r1, [r0, r2]
- ldr r1, =0x01C20
- ldr r2, =0x0C020 @VPLL_LOCK_OFFSET
- str r1, [r0, r2]
-
- /*
- * APLL_CON1:
- *
- * APLL_AFC_ENB[31] 0x1
- * APLL_AFC[0] 0xC
- */
- ldr r1, =0x8000000C
- ldr r2, =0x014104 @APLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /*
- * APLL_CON0:
- *
- * APLL_MDIV[16] 0xFA
- * APLL_PDIV[8] 0x6
- * APLL_SDIV[0] 0x1
- */
- ldr r1, =0x80FA0601
- ldr r2, =0x014100 @APLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /*
- * MPLL_CON1:
- *
- * MPLL_AFC_ENB[31] 0x1
- * MPLL_AFC[0] 0x1C
- */
- ldr r1, =0x0000001C
- ldr r2, =0x01410C @MPLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /*
- * MPLL_CON0:
- *
- * MPLL_MDIV[16] 0xC8
- * MPLL_PDIV[8] 0x6
- * MPLL_SDIV[0] 0x1
- */
- ldr r1, =0x80C80601
- ldr r2, =0x014108 @MPLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /* EPLL */
- ldr r1, =0x0
- ldr r2, =0x0C114 @EPLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /*
- * EPLL_CON0:
- *
- * EPLL_MDIV[16] 0x30
- * EPLL_PDIV[8] 0x3
- * EPLL_SDIV[0] 0x2
- */
- ldr r1, =0x80300302
- ldr r2, =0x0C110 @EPLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /*
- * VPLL_CON1:
- *
- * VPLL_MRR[24] 0x11
- * VPLL_MFR[16] 0x0
- * VPLL_K[0] 0x400
- */
- ldr r1, =0x11000400
- ldr r2, =0x0C124 @VPLL_CON1_OFFSET
- str r1, [r0, r2]
-
- /*
- * VPLL_CON0:
- *
- * VPLL_MDIV[16] 0x35
- * VPLL_PDIV[8] 0x3
- * VPLL_SDIV[0] 0x2
- */
- ldr r1, =0x80350302
- ldr r2, =0x0C120 @VPLL_CON0_OFFSET
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x30000
-3: subs r1, r1, #1
- bne 3b
-
- pop {pc}
-/*
- * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
- * void uart_asm_init(void)
- */
- .globl uart_asm_init
-uart_asm_init:
-
- /* setup UART0-UART3 GPIOs (part1) */
- mov r0, r7
- ldr r1, =0x22222222
- str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
- ldr r1, =0x00222222
- str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
-
- ldr r0, =EXYNOS4_UART_BASE
- add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
-
- ldr r1, =0x3C5
- str r1, [r0, #0x4]
- ldr r1, =0x111
- str r1, [r0, #0x8]
- ldr r1, =0x3
- str r1, [r0, #0x0]
- ldr r1, =0x35
- str r1, [r0, #0x28]
- ldr r1, =0x4
- str r1, [r0, #0x2c]
-
- mov pc, lr
- nop
- nop
- nop
diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S
deleted file mode 100644
index d3b6265..0000000
--- a/board/samsung/smdkv310/mem_setup.S
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * Memory setup for SMDKV310 board based on EXYNOS4210
- *
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-#define SET_MIU
-
-#define MEM_DLL
-
-#ifdef CONFIG_CLK_800_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_200_200
-#define DRAM_CLK_200
-#endif
-#ifdef CONFIG_CLK_1000_330_165
-#define DRAM_CLK_330
-#endif
-#ifdef CONFIG_CLK_1000_400_200
-#define DRAM_CLK_400
-#endif
-
- .globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
-
- /*
- * Async bridge configuration at CPU_core:
- * 1: half_sync
- * 0: full_sync
- */
- ldr r0, =0x10010350
- mov r1, #1
- str r1, [r0]
-
-#ifdef SET_MIU
- ldr r0, =EXYNOS4_MIU_BASE @0x10600000
-#ifdef CONFIG_MIU_1BIT_INTERLEAVED
- ldr r1, =0x0000000c
- str r1, [r0, #0x400] @MIU_INTLV_CONFIG
- ldr r1, =0x40000000
- str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
- ldr r1, =0xbfffffff
- str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
- ldr r1, =0x00000001
- str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
-#endif
-#ifdef CONFIG_MIU_2BIT_INTERLEAVED
- ldr r1, =0x2000150c
- str r1, [r0, #0x400] @MIU_INTLV_CONFIG
- ldr r1, =0x40000000
- str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
- ldr r1, =0xbfffffff
- str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
- ldr r1, =0x00000001
- str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
-#endif
-#ifdef CONFIG_MIU_LINEAR
- ldr r1, =0x40000000
- str r1, [r0, #0x818] @MIU_SINGLE_MAPPING0_START_ADDR
- ldr r1, =0x7fffffff
- str r1, [r0, #0x820] @MIU_SINGLE_MAPPING0_END_ADDR
- ldr r1, =0x80000000
- str r1, [r0, #0x828] @MIU_SINGLE_MAPPING1_START_ADDR
- ldr r1, =0xbfffffff
- str r1, [r0, #0x830] @MIU_SINGLE_MAPPING1_END_ADDR]
- ldr r1, =0x00000006
- str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
-#endif
-#endif
- /* DREX0 */
- ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
-
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
-
- ldr r1, =0xE3855703
- str r1, [r0, #0x44] @DMC_PHYZQCONTROL
-
- mov r2, #0x100000
-1: subs r2, r2, #1
- bne 1b
-
- ldr r1, =0xe000008e
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
-
- ldr r1, =0x71101008
- str r1, [r0, #0x18] @DMC_PHYCONTROL0
- ldr r1, =0x7110100A
- str r1, [r0, #0x18] @DMC_PHYCONTROL0
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
- ldr r1, =0x7110100B
- str r1, [r0, #0x18] @DMC_PHYCONTROL0
-
- ldr r1, =0x00000000
- str r1, [r0, #0x20] @DMC_PHYCONTROL2
-
- ldr r1, =0x0FFF301a
- str r1, [r0, #0x00] @DMC_CONCONTROL
- ldr r1, =0x00312640
- str r1, [r0, #0x04] @DMC_MEMCONTROL]
-
-#ifdef CONFIG_MIU_LINEAR
- ldr r1, =0x40e01323
- str r1, [r0, #0x08] @DMC_MEMCONFIG0
- ldr r1, =0x60e01323
- str r1, [r0, #0x0C] @DMC_MEMCONFIG1
-#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
- ldr r1, =0x20e01323
- str r1, [r0, #0x08] @DMC_MEMCONFIG0
- ldr r1, =0x40e01323
- str r1, [r0, #0x0C] @DMC_MEMCONFIG1
-#endif
-
- ldr r1, =0xff000000
- str r1, [r0, #0x14] @DMC_PRECHCONFIG
-
- ldr r1, =0x000000BC
- str r1, [r0, #0x30] @DMC_TIMINGAREF
-
-#ifdef DRAM_CLK_330
- ldr r1, =0x3545548d
- str r1, [r0, #0x34] @DMC_TIMINGROW
- ldr r1, =0x45430506
- str r1, [r0, #0x38] @DMC_TIMINGDATA
- ldr r1, =0x4439033c
- str r1, [r0, #0x3C] @DMC_TIMINGPOWER
-#endif
-#ifdef DRAM_CLK_400
- ldr r1, =0x4046654f
- str r1, [r0, #0x34] @DMC_TIMINGROW
- ldr r1, =0x56500506
- str r1, [r0, #0x38] @DMC_TIMINGDATA
- ldr r1, =0x5444033d
- str r1, [r0, #0x3C] @DMC_TIMINGPOWER
-#endif
- ldr r1, =0x07000000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-2: subs r2, r2, #1
- bne 2b
-
- ldr r1, =0x00020000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00030000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00010002
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00000328
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-3: subs r2, r2, #1
- bne 3b
-
- ldr r1, =0x0a000000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-4: subs r2, r2, #1
- bne 4b
-
- ldr r1, =0x07100000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-5: subs r2, r2, #1
- bne 5b
-
- ldr r1, =0x00120000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00130000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00110002
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00100328
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-6: subs r2, r2, #1
- bne 6b
-
- ldr r1, =0x0a100000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-7: subs r2, r2, #1
- bne 7b
-
- ldr r1, =0xe000008e
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
-
- mov r2, #0x100000
-8: subs r2, r2, #1
- bne 8b
-
- /* DREX1 */
- ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
-
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
-
- ldr r1, =0xE3855703
- str r1, [r0, #0x44] @DMC_PHYZQCONTROL
-
- mov r2, #0x100000
-1: subs r2, r2, #1
- bne 1b
-
- ldr r1, =0xe000008e
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
-
- ldr r1, =0x71101008
- str r1, [r0, #0x18] @DMC_PHYCONTROL0
- ldr r1, =0x7110100A
- str r1, [r0, #0x18] @DMC_PHYCONTROL0
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
- ldr r1, =0x7110100B
- str r1, [r0, #0x18] @DMC_PHYCONTROL0
-
- ldr r1, =0x00000000
- str r1, [r0, #0x20] @DMC_PHYCONTROL2
-
- ldr r1, =0x0FFF301a
- str r1, [r0, #0x00] @DMC_CONCONTROL
- ldr r1, =0x00312640
- str r1, [r0, #0x04] @DMC_MEMCONTROL]
-
-#ifdef CONFIG_MIU_LINEAR
- ldr r1, =0x40e01323
- str r1, [r0, #0x08] @DMC_MEMCONFIG0
- ldr r1, =0x60e01323
- str r1, [r0, #0x0C] @DMC_MEMCONFIG1
-#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
- ldr r1, =0x20e01323
- str r1, [r0, #0x08] @DMC_MEMCONFIG0
- ldr r1, =0x40e01323
- str r1, [r0, #0x0C] @DMC_MEMCONFIG1
-#endif
-
- ldr r1, =0xff000000
- str r1, [r0, #0x14] @DMC_PRECHCONFIG
-
- ldr r1, =0x000000BC
- str r1, [r0, #0x30] @DMC_TIMINGAREF
-
-#ifdef DRAM_CLK_330
- ldr r1, =0x3545548d
- str r1, [r0, #0x34] @DMC_TIMINGROW
- ldr r1, =0x45430506
- str r1, [r0, #0x38] @DMC_TIMINGDATA
- ldr r1, =0x4439033c
- str r1, [r0, #0x3C] @DMC_TIMINGPOWER
-#endif
-#ifdef DRAM_CLK_400
- ldr r1, =0x4046654f
- str r1, [r0, #0x34] @DMC_TIMINGROW
- ldr r1, =0x56500506
- str r1, [r0, #0x38] @DMC_TIMINGDATA
- ldr r1, =0x5444033d
- str r1, [r0, #0x3C] @DMC_TIMINGPOWER
-#endif
-
- ldr r1, =0x07000000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-2: subs r2, r2, #1
- bne 2b
-
- ldr r1, =0x00020000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00030000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00010002
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00000328
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-3: subs r2, r2, #1
- bne 3b
-
- ldr r1, =0x0a000000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-4: subs r2, r2, #1
- bne 4b
-
- ldr r1, =0x07100000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-5: subs r2, r2, #1
- bne 5b
-
- ldr r1, =0x00120000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00130000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00110002
- str r1, [r0, #0x10] @DMC_DIRECTCMD
- ldr r1, =0x00100328
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-6: subs r2, r2, #1
- bne 6b
-
- ldr r1, =0x0a100000
- str r1, [r0, #0x10] @DMC_DIRECTCMD
-
- mov r2, #0x100000
-7: subs r2, r2, #1
- bne 7b
-
- ldr r1, =0xe000008e
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
- ldr r1, =0xe0000086
- str r1, [r0, #0x1C] @DMC_PHYCONTROL1
-
- mov r2, #0x100000
-8: subs r2, r2, #1
- bne 8b
-
- /* turn on DREX0, DREX1 */
- ldr r0, =0x10400000 @APB_DMC_0_BASE
- ldr r1, =0x0FFF303a
- str r1, [r0, #0x00] @DMC_CONCONTROL
-
- ldr r0, =0x10410000 @APB_DMC_1_BASE
- ldr r1, =0x0FFF303a
- str r1, [r0, #0x00] @DMC_CONCONTROL
-
- mov pc, lr
diff --git a/board/samsung/smdkv310/mmc_boot.c b/board/samsung/smdkv310/mmc_boot.c
deleted file mode 100644
index d3fc18d..0000000
--- a/board/samsung/smdkv310/mmc_boot.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include<common.h>
-#include<config.h>
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
- u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR;
-
- copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
-}
-
-void board_init_f(unsigned long bootflag)
-{
- __attribute__((noreturn)) void (*uboot)(void);
- copy_uboot_to_ram();
-
- /* Jump to U-Boot image */
- uboot = (void *)CONFIG_SYS_TEXT_BASE;
- (*uboot)();
- /* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- /*Function attribute is no-return*/
- /*This Function never executes*/
- while (1)
- ;
-}
-
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
-{
-}