commit bd35b562280e16a5afa52a66b0cb270795f3328e
author Michal Simek <michal.simek@xilinx.com> Fri Jul 20 10:16:21 2018 +0200
committer Michal Simek <michal.simek@xilinx.com> Mon Aug 06 08:44:35 2018 +0200
tree 0be9bfe26a63ffa1f952071407c587b7a1838e39
parent 386c979dd3301eeff1c2a31e446e30c8a48be59b

arm: zynq: Remove fclk-enable property for cse-nor target

Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arch/arm/dts/zynq-cse-nor.dts

diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index ba6f9a1..edc8f59 100644
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -56,7 +56,6 @@
 			clkc: clkc@100 {
 				#clock-cells = <1>;
 				compatible = "xlnx,ps7-clkc";
-				fclk-enable = <0xf>;
 				clock-output-names = "armpll", "ddrpll",
 						"iopll", "cpu_6or4x",
 						"cpu_3or2x", "cpu_2x", "cpu_1x",