tree 61cd055ff4710141c57d53e2d574c433a5176b7d
parent efd16d02d0528b0e3e0a7bc657cb1eb63c73b1ab
author Marek Vasut <marex@denx.de> 1410737277 +0200
committer Marek Vasut <marex@denx.de> 1412610410 +0200

arm: socfpga: cache: Define cacheline size

The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>