commit bd279e325156a7cd6291e48f21a87f00af1eba5d
author Marek Vasut <marex@denx.de> Mon Sep 15 01:27:57 2014 +0200
committer Marek Vasut <marex@denx.de> Mon Oct 06 17:46:50 2014 +0200
tree 61cd055ff4710141c57d53e2d574c433a5176b7d
parent efd16d02d0528b0e3e0a7bc657cb1eb63c73b1ab

arm: socfpga: cache: Define cacheline size

The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

include/configs/socfpga_cyclone5.h

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 54343b8..76979b1 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -26,6 +26,8 @@
 #define CONFIG_SOCFPGA
 #define CONFIG_CLOCKS
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /* base address for .text section */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040