diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 0e1ad0e..31a5c8d 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -26,6 +26,7 @@
 obj-y	+= board.o
 endif
 
+obj-$(CONFIG_CPU_V7M) += cmd_boot.o
 obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
diff --git a/arch/arm/lib/cmd_boot.c b/arch/arm/lib/cmd_boot.c
new file mode 100644
index 0000000..37bb6a5
--- /dev/null
+++ b/arch/arm/lib/cmd_boot.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2008-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMv7M does not support ARM instruction mode. However, the
+ * interworking BLX and BX instructions do encode the ARM/Thumb
+ * field in bit 0. This means that when executing any Branch
+ * and eXchange instruction we must set bit 0 to one to guarantee
+ * that we keep the processor in Thumb instruction mode. From The
+ * ARMv7-M Instruction Set A4.1.1:
+ *   "ARMv7-M only supports the Thumb instruction execution state,
+ *    therefore the value of address bit [0] must be 1 in interworking
+ *    instructions, otherwise a fault occurs."
+ */
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+			 int argc, char * const argv[])
+{
+	ulong addr = (ulong)entry | 1;
+	entry = (void *)addr;
+
+	return entry(argc, argv);
+}