tree e30126c87d2fff657f6cbcf14b37df543dde9194
parent 0fe0ddc27fc0ab326e8c46a145a296dd10494e43
author Peng Fan <peng.fan@nxp.com> 1452049591 +0800
committer Stefano Babic <sbabic@denx.de> 1453634001 +0100

imx: mx6ul/sx: fix mmdc_ch0 clk calculation

Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.

Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>