| commit | 6b41ae8f050384b31cb64152f7e10268516cd47a | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@amd.com> | Tue Oct 31 11:50:54 2023 +0100 |
| committer | Michal Simek <michal.simek@amd.com> | Tue Nov 07 13:47:09 2023 +0100 |
| tree | 14e4fd613f6f834c6c9f3744ed56b620f984fd9e | |
| parent | 7d3fdfcc8622d310ffc305ad435bcb70b62d6ba7 [diff] |
xilinx: versal: Setup 30MHz as default spi frequency Align default SPI configuration with ZynqMP/Versal NET. There is no reason to run on lower frequencies. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c1d6ebd659f3002649b1200c926f8b9ed3132085.1698749448.git.michal.simek@amd.com