global: Migrate CONFIG_MAX_MEM_MAPPED to CFG

Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED

Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 2aeec7d..5c45c2a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1308,13 +1308,13 @@
 	 * allocated from first region. If the memory extends to  the second
 	 * region (or the third region if applicable), Management Complex (MC)
 	 * memory should be put into the highest region, i.e. the end of DDR
-	 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
+	 * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
 	 * U-Boot doesn't relocate itself into higher address. Should DDR be
 	 * configured to skip the first region, this function needs to be
 	 * adjusted.
 	 */
-	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
-		ea_size = CONFIG_MAX_MEM_MAPPED;
+	if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
+		ea_size = CFG_MAX_MEM_MAPPED;
 		rem = gd->ram_size - ea_size;
 	} else {
 		ea_size = gd->ram_size;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 57d92f6..12758c8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -36,7 +36,7 @@
 
 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE			0x06000000
@@ -121,7 +121,7 @@
 
 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
 #define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
@@ -147,7 +147,7 @@
 
 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE				0x06000000
@@ -191,7 +191,7 @@
 
 /* DDR */
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SEC */
 
@@ -211,7 +211,7 @@
 #define CFG_SYS_NUM_FM1_DTSEC		7
 #define CFG_SYS_NUM_FM1_10GEC		1
 #define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
 
 #define QE_MURAM_SIZE		0x6000UL
 #define MAX_QE_RISC		1
@@ -250,14 +250,14 @@
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
 #define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CFG_SYS_NUM_FMAN			1
 #define CFG_SYS_NUM_FM1_DTSEC		8
 #define CFG_SYS_NUM_FM1_10GEC		2
 #define CFG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CFG_SYS_DDR_BLOCK1_SIZE
+#define CFG_MAX_MEM_MAPPED           CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SMMU Defintions */
 #define SMMU_BASE		0x09000000
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 4a4d642..d0abbda 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -70,7 +70,7 @@
 /* SATA */
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 #ifdef CONFIG_DDR_SPD
-#define CONFIG_MAX_MEM_MAPPED			((phys_size_t)2 << 30)
+#define CFG_MAX_MEM_MAPPED			((phys_size_t)2 << 30)
 #endif
 
 #define DCU_LAYER_MAX_NUM			16