Add the files for the SMN42 board
diff --git a/include/asm-arm/arch-lpc2292/hardware.h b/include/asm-arm/arch-lpc2292/hardware.h
new file mode 100644
index 0000000..fd2b464
--- /dev/null
+++ b/include/asm-arm/arch-lpc2292/hardware.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_LPC2292)
+#include <asm-arm/arch-lpc2292/lpc2292_registers.h>
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lpc2292/lpc2292_registers.h b/include/asm-arm/arch-lpc2292/lpc2292_registers.h
new file mode 100644
index 0000000..5715f3e
--- /dev/null
+++ b/include/asm-arm/arch-lpc2292/lpc2292_registers.h
@@ -0,0 +1,225 @@
+#ifndef __LPC2292_REGISTERS_H
+#define __LPC2292_REGISTERS_H
+
+#include <config.h>
+
+/* Macros for reading/writing registers */
+#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
+#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
+#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
+#define GET8(reg) (*(volatile unsigned char*)(reg))
+#define GET16(reg) (*(volatile unsigned short*)(reg))
+#define GET32(reg) (*(volatile unsigned int*)(reg))
+
+/* External Memory Controller */
+
+#define BCFG0 0xFFE00000 /* 32-bits */
+#define BCFG1 0xFFE00004 /* 32-bits */
+#define BCFG2 0xFFE00008 /* 32-bits */
+#define BCFG3 0xFFE0000c /* 32-bits */
+
+/* System Control Block */
+
+#define EXTINT 0xE01FC140
+#define EXTWAKE 0xE01FC144
+#define EXTMODE 0xE01FC148
+#define EXTPOLAR 0xE01FC14C
+#define MEMMAP 0xE01FC040
+#define PLLCON 0xE01FC080
+#define PLLCFG 0xE01FC084
+#define PLLSTAT 0xE01FC088
+#define PLLFEED 0xE01FC08C
+#define PCON 0xE01FC0C0
+#define PCONP 0xE01FC0C4
+#define VPBDIV 0xE01FC100
+
+/* Memory Acceleration Module */
+
+#define MAMCR 0xE01FC000
+#define MAMTIM 0xE01FC004
+
+/* Vectored Interrupt Controller */
+
+#define VICIRQStatus 0xFFFFF000
+#define VICFIQStatus 0xFFFFF004
+#define VICRawIntr 0xFFFFF008
+#define VICIntSelect 0xFFFFF00C
+#define VICIntEnable 0xFFFFF010
+#define VICIntEnClr 0xFFFFF014
+#define VICSoftInt 0xFFFFF018
+#define VICSoftIntClear 0xFFFFF01C
+#define VICProtection 0xFFFFF020
+#define VICVectAddr 0xFFFFF030
+#define VICDefVectAddr 0xFFFFF034
+#define VICVectAddr0 0xFFFFF100
+#define VICVectAddr1 0xFFFFF104
+#define VICVectAddr2 0xFFFFF108
+#define VICVectAddr3 0xFFFFF10C
+#define VICVectAddr4 0xFFFFF110
+#define VICVectAddr5 0xFFFFF114
+#define VICVectAddr6 0xFFFFF118
+#define VICVectAddr7 0xFFFFF11C
+#define VICVectAddr8 0xFFFFF120
+#define VICVectAddr9 0xFFFFF124
+#define VICVectAddr10 0xFFFFF128
+#define VICVectAddr11 0xFFFFF12C
+#define VICVectAddr12 0xFFFFF130
+#define VICVectAddr13 0xFFFFF134
+#define VICVectAddr14 0xFFFFF138
+#define VICVectAddr15 0xFFFFF13C
+#define VICVectCntl0 0xFFFFF200
+#define VICVectCntl1 0xFFFFF204
+#define VICVectCntl2 0xFFFFF208
+#define VICVectCntl3 0xFFFFF20C
+#define VICVectCntl4 0xFFFFF210
+#define VICVectCntl5 0xFFFFF214
+#define VICVectCntl6 0xFFFFF218
+#define VICVectCntl7 0xFFFFF21C
+#define VICVectCntl8 0xFFFFF220
+#define VICVectCntl9 0xFFFFF224
+#define VICVectCntl10 0xFFFFF228
+#define VICVectCntl11 0xFFFFF22C
+#define VICVectCntl12 0xFFFFF230
+#define VICVectCntl13 0xFFFFF234
+#define VICVectCntl14 0xFFFFF238
+#define VICVectCntl15 0xFFFFF23C
+
+/* Pin connect block */
+
+#define PINSEL0 0xE002C000 /* 32 bits */
+#define PINSEL1 0xE002C004 /* 32 bits */
+#define PINSEL2 0xE002C014 /* 32 bits */
+
+/* GPIO */
+
+#define IO0PIN 0xE0028000
+#define IO0SET 0xE0028004
+#define IO0DIR 0xE0028008
+#define IO0CLR 0xE002800C
+#define IO1PIN 0xE0028010
+#define IO1SET 0xE0028014
+#define IO1DIR 0xE0028018
+#define IO1CLR 0xE002801C
+#define IO2PIN 0xE0028020
+#define IO2SET 0xE0028024
+#define IO2DIR 0xE0028028
+#define IO2CLR 0xE002802C
+#define IO3PIN 0xE0028030
+#define IO3SET 0xE0028034
+#define IO3DIR 0xE0028038
+#define IO3CLR 0xE002803C
+
+/* Uarts */
+
+#define U0RBR 0xE000C000
+#define U0THR 0xE000C000
+#define U0IER 0xE000C004
+#define U0IIR 0xE000C008
+#define U0FCR 0xE000C008
+#define U0LCR 0xE000C00C
+#define U0LSR 0xE000C014
+#define U0SCR 0xE000C01C
+#define U0DLL 0xE000C000
+#define U0DLM 0xE000C004
+
+#define U1RBR 0xE0010000
+#define U1THR 0xE0010000
+#define U1IER 0xE0010004
+#define U1IIR 0xE0010008
+#define U1FCR 0xE0010008
+#define U1LCR 0xE001000C
+#define U1MCR 0xE0010010
+#define U1LSR 0xE0010014
+#define U1MSR 0xE0010018
+#define U1SCR 0xE001001C
+#define U1DLL 0xE0010000
+#define U1DLM 0xE0010004
+
+/* I2C */
+
+#define I2CONSET 0xE001C000
+#define I2STAT 0xE001C004
+#define I2DAT 0xE001C008
+#define I2ADR 0xE001C00C
+#define I2SCLH 0xE001C010
+#define I2SCLL 0xE001C014
+#define I2CONCLR 0xE001C018
+
+/* SPI */
+
+#define S0SPCR 0xE0020000
+#define S0SPSR 0xE0020004
+#define S0SPDR 0xE0020008
+#define S0SPCCR 0xE002000C
+#define S0SPINT 0xE002001C
+
+#define S1SPCR 0xE0030000
+#define S1SPSR 0xE0030004
+#define S1SPDR 0xE0030008
+#define S1SPCCR 0xE003000C
+#define S1SPINT 0xE003001C
+
+/* CAN controller */
+
+/* skip for now */
+
+/* Timers */
+
+#define T0IR 0xE0004000
+#define T0TCR 0xE0004004
+#define T0TC 0xE0004008
+#define T0PR 0xE000400C
+#define T0PC 0xE0004010
+#define T0MCR 0xE0004014
+#define T0MR0 0xE0004018
+#define T0MR1 0xE000401C
+#define T0MR2 0xE0004020
+#define T0MR3 0xE0004024
+#define T0CCR 0xE0004028
+#define T0CR0 0xE000402C
+#define T0CR1 0xE0004030
+#define T0CR2 0xE0004034
+#define T0CR3 0xE0004038
+#define T0EMR 0xE000403C
+
+#define T1IR 0xE0008000
+#define T1TCR 0xE0008004
+#define T1TC 0xE0008008
+#define T1PR 0xE000800C
+#define T1PC 0xE0008010
+#define T1MCR 0xE0008014
+#define T1MR0 0xE0008018
+#define T1MR1 0xE000801C
+#define T1MR2 0xE0008020
+#define T1MR3 0xE0008024
+#define T1CCR 0xE0008028
+#define T1CR0 0xE000802C
+#define T1CR1 0xE0008030
+#define T1CR2 0xE0008034
+#define T1CR3 0xE0008038
+#define T1EMR 0xE000803C
+
+/* PWM */
+
+/* skip for now */
+
+/* A/D converter */
+
+/* skip for now */
+
+/* Real Time Clock */
+
+/* skip for now */
+
+/* Watchdog */
+
+#define WDMOD 0xE0000000
+#define WDTC 0xE0000004
+#define WDFEED 0xE0000008
+#define WDTV 0xE000000C
+
+/* EmbeddedICE LOGIC */
+
+/* skip for now */
+
+#endif
diff --git a/include/asm-arm/arch-lpc2292/mmc.h b/include/asm-arm/arch-lpc2292/mmc.h
new file mode 100644
index 0000000..e664a5f
--- /dev/null
+++ b/include/asm-arm/arch-lpc2292/mmc.h
@@ -0,0 +1,22 @@
+/*
+ * A dummy header file for use with the LPC2292 port to keep the
+ * compiler happy.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MMC_ARM_TDM_H_
+#define _MMC_ARM_TDM_H_
+#endif /* _MMC_ARM_TDM_H_ */
diff --git a/include/asm-arm/arch-lpc2292/spi.h b/include/asm-arm/arch-lpc2292/spi.h
new file mode 100644
index 0000000..6ae66e8
--- /dev/null
+++ b/include/asm-arm/arch-lpc2292/spi.h
@@ -0,0 +1,82 @@
+/*
+ This file defines the interface to the lpc22xx SPI module.
+ Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
+
+ This file may be included in software not adhering to the GPL.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#ifndef SPI_H
+#define SPI_H
+
+#include <config.h>
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+
+#define SPIF 0x80
+
+#define spi_lock() disable_interrupts();
+#define spi_unlock() enable_interrupts();
+
+extern unsigned long spi_flags;
+extern unsigned char spi_idle;
+
+int spi_init(void);
+
+static inline unsigned char spi_read(void)
+{
+ unsigned char b;
+
+ PUT8(S0SPDR, spi_idle);
+ while (!(GET8(S0SPSR) & SPIF));
+ b = GET8(S0SPDR);
+
+ return b;
+}
+
+static inline void spi_write(unsigned char b)
+{
+ PUT8(S0SPDR, b);
+ while (!(GET8(S0SPSR) & SPIF));
+ GET8(S0SPDR); /* this will clear the SPIF bit */
+}
+
+static inline void spi_set_clock(unsigned char clk_value)
+{
+ PUT8(S0SPCCR, clk_value);
+}
+
+static inline void spi_set_cfg(unsigned char phase,
+ unsigned char polarity,
+ unsigned char lsbf)
+{
+ unsigned char v = 0x20; /* master bit set */
+
+ if (phase)
+ v |= 0x08; /* set phase bit */
+ if (polarity) {
+ v |= 0x10; /* set polarity bit */
+ spi_idle = 0xFF;
+ } else {
+ spi_idle = 0x00;
+ }
+ if (lsbf)
+ v |= 0x40; /* set lsbf bit */
+
+ PUT8(S0SPCR, v);
+}
+#endif /* SPI_H */