tree 118a069b493e29e96192ac1d50c08d913509d6da
parent a5694a121471da3e51fe6e6b5c1996cc9519f5ee
author Yuri Tikhonov <yur@emcraft.com> 1224240858 +0200
committer Wolfgang Denk <wd@denx.de> 1224241362 +0200

ppc4xx: PPC44x MQ initialization

Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).

Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.

Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>