* Patch by Hans-Joerg Frieden, 06 Dec 2002
Fix misc problems with AmigaOne support
* Patch by Chris Hallinan, 3 Dec 2002:
minor cleanup to the MPC8245 EPIC driver
* Patch by Pierre Aubert , 28 Nov 2002
Add support for external (SIU) interrupts on MPC8xx
* Patch by Pierre Aubert , 28 Nov 2002
Fix nested syscalls bug in standalone applications
* Patch by David Müller, 27 Nov 2002:
fix output of "pciinfo" command for CardBus bridge devices.
* Fix bug in TQM8260 board detection - boards got stuck when board ID
was not readable
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index 300ac02..5a3b557 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -205,9 +205,27 @@
PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
- PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
- if (header_type & 0x01) { /* PCI-to-PCI bridge */
+ switch (header_type & 0x03) {
+ case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
+ PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
+ PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
+ PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
+ PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
+ PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
+ PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
+ PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
+ PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
+ PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
+ PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
+ PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
+ PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
+ PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
+ break;
+
+ case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
+
+ PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
@@ -227,19 +245,39 @@
PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
- } else { /* PCI device */
- PRINT(" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
- PRINT(" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
- PRINT(" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
- PRINT(" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
- PRINT(" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
- PRINT(" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
- PRINT(" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
- PRINT(" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
- PRINT(" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
- PRINT(" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
- PRINT(" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
- PRINT(" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
+ break;
+
+ case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
+
+ PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
+ PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
+ PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
+ PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
+ PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
+ PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
+ PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
+ PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
+ PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
+ PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
+ PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
+ PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
+ PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
+ PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
+ PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
+ PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
+ PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
+ PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
+ PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
+ PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
+ PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
+ PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
+ PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
+ PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
+ break;
+
+ default:
+ printf("unknown header\n");
+ break;
}
#undef PRINT
diff --git a/common/env_common.c b/common/env_common.c
index bd22e15..4f618d6 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -156,9 +156,24 @@
return (c);
}
+#ifdef CONFIG_AMIGAONEG3SE
uchar env_get_char_memory (int index)
{
DECLARE_GLOBAL_DATA_PTR;
+ uchar retval;
+ enable_nvram();
+ if (gd->env_valid) {
+ retval = ( *((uchar *)(gd->env_addr + index)) );
+ } else {
+ retval = ( default_environment[index] );
+ }
+ disable_nvram();
+ return retval;
+}
+#else
+uchar env_get_char_memory (int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
if (gd->env_valid) {
return ( *((uchar *)(gd->env_addr + index)) );
@@ -166,6 +181,7 @@
return ( default_environment[index] );
}
}
+#endif
uchar *env_get_addr (int index)
{
diff --git a/common/env_nvram.c b/common/env_nvram.c
index fdfa4fc..76e8438 100644
--- a/common/env_nvram.c
+++ b/common/env_nvram.c
@@ -66,7 +66,25 @@
extern uchar (*env_get_char)(int);
extern uchar env_get_char_memory (int index);
+#ifdef CONFIG_AMIGAONEG3SE
+uchar env_get_char_spec (int index)
+{
+#ifdef CFG_NVRAM_ACCESS_ROUTINE
+ uchar c;
+
+ nvram_read(&c, CFG_ENV_ADDR+index, 1);
+ return c;
+#else
+ DECLARE_GLOBAL_DATA_PTR;
+ uchar retval;
+ enable_nvram();
+ retval = *((uchar *)(gd->env_addr + index));
+ disable_nvram();
+ return retval;
+#endif
+}
+#else
uchar env_get_char_spec (int index)
{
#ifdef CFG_NVRAM_ACCESS_ROUTINE
@@ -81,6 +99,7 @@
return *((uchar *)(gd->env_addr + index));
#endif
}
+#endif
void env_relocate_spec (void)
{
@@ -94,13 +113,19 @@
int saveenv (void)
{
int rcode = 0;
-
+#ifdef CONFIG_AMIGAONEG3SE
+ enable_nvram();
+#endif
#ifdef CFG_NVRAM_ACCESS_ROUTINE
nvram_write(CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE);
#else
if (memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE) == NULL)
rcode = 1 ;
#endif
+#ifdef CONFIG_AMIGAONEG3SE
+ udelay(10000);
+ disable_nvram();
+#endif
return rcode;
}
@@ -113,7 +138,9 @@
int env_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
-
+#ifdef CONFIG_AMIGAONEG3SE
+ enable_nvram();
+#endif
#if defined(CFG_NVRAM_ACCESS_ROUTINE)
ulong crc;
uchar data[ENV_SIZE];
@@ -131,7 +158,9 @@
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 0;
}
-
+#ifdef CONFIG_AMIGAONEG3SE
+ disable_nvram();
+#endif
return (0);
}