diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index d3c33e8..36397fe 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -181,7 +181,7 @@
 	struct phy_device *phydev;
 	int phy_of_handle;
 	struct mii_dev *bus;
-#ifdef CONFIG_CLK_ZYNQMP
+#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 	struct clk clk;
 #endif
 };
@@ -456,13 +456,21 @@
 		break;
 	}
 
-#ifndef CONFIG_CLK_ZYNQMP
+#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
+	ret = clk_set_rate(&priv->clk, clk_rate);
+	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+		dev_err(dev, "failed to set tx clock rate\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->clk);
+	if (ret && ret != -ENOSYS) {
+		dev_err(dev, "failed to enable tx clock\n");
+		return ret;
+	}
+#else
 	zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
 				ZYNQ_GEM_BASEADDR0, clk_rate);
-#else
-	ret = clk_set_rate(&priv->clk, clk_rate);
-	if (IS_ERR_VALUE(ret))
-		return -1;
 #endif
 
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
@@ -636,7 +644,7 @@
 	priv->tx_bd = (struct emac_bd *)bd_space;
 	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 
-#ifdef CONFIG_CLK_ZYNQMP
+#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 	ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to get clock\n");