clk: mediatek: add set_clr_upd mux type flow
Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 6c6b500..450de98 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -67,12 +67,23 @@
if (++index == mux->num_parents)
return -EINVAL;
- /* switch mux to a select parent */
- val = readl(base + mux->mux_reg);
- val &= ~(mux->mux_mask << mux->mux_shift);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = (mux->mux_mask << mux->mux_shift);
+ writel(val, base + mux->mux_clr_reg);
- val |= index << mux->mux_shift;
- writel(val, base + mux->mux_reg);
+ val = (index << mux->mux_shift);
+ writel(val, base + mux->mux_set_reg);
+
+ if (mux->upd_shift >= 0)
+ writel(BIT(mux->upd_shift), base + mux->upd_reg);
+ } else {
+ /* switch mux to a select parent */
+ val = readl(base + mux->mux_reg);
+ val &= ~(mux->mux_mask << mux->mux_shift);
+
+ val |= index << mux->mux_shift;
+ writel(val, base + mux->mux_reg);
+ }
return 0;
}
@@ -332,9 +343,14 @@
return 0;
/* enable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val &= ~BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_clr_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val &= ~BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
if (mux->flags & CLK_DOMAIN_SCPSYS) {
/* enable scpsys clock off control */
@@ -360,9 +376,14 @@
return 0;
/* disable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val |= BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_set_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val |= BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
return 0;
}