tree bf8de48d06c87611423f7e700f765958cfc294a9
parent 4193d0ece20c5b293d1f11132b8e001a7f2ac962
author Ley Foon Tan <ley.foon.tan@intel.com> 1553189043 +0800
committer Marek Vasut <marex@denx.de> 1555532417 +0200

arm: dts: Stratix10: Modify stratix10 socdk memory node

The stratix10 socdk ships with 4GB of memory.  Modify the
device tree to represent this.  Note that to access 4GB of
memory in Stratix 10, due to the IO space from 2GB to 4GB,
we use the fact that the DDR controller ignores upper address
bits outside of the configured DRAM's size.  This means that
, the 4GB DRAM is mapped to memory every 4GB.

For an 8GB memory, you can either live with the 2GB IO space,
and loose access to that memory from the processor, or use
the same trick:

Loose 2GB of memory:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* last 4GB */
                      <1 0x00000000 1 0x00000000>;
                u-boot,dm-pre-reloc;
        };

or to map it all:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* next 6GB */
                      <2 0x80000000 1 0x80000000>;
                u-boot,dm-pre-reloc;
        };

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>