pinctrl: nuvoton: add NPCM7xx/NPCM8xx reset type detect
add reset type detect and persist setting.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index c6ffa89..0ec47e9 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -20,7 +20,7 @@
#define SWRSTC1 0x44
#define SWRSTC2 0x48
#define SWRSTC3 0x4c
-#define SWRSTC4 0x50
+#define TIPRSTC 0x50
#define CORSTC 0x5c
#define FLOCKR1 0x74
#define INTCR4 0xc0
@@ -772,6 +772,10 @@
regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(offset), 0);
regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), 0);
+ regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(offset), 0);
+ regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(offset), 0);
+ regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(offset), 0);
+ regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(offset), 0);
} else {
regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(offset),
BIT(offset));
@@ -781,6 +785,14 @@
BIT(offset));
regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset),
BIT(offset));
+ regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(offset),
+ BIT(offset));
+ regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(offset),
+ BIT(offset));
+ regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(offset),
+ BIT(offset));
+ regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(offset),
+ BIT(offset));
}
return 0;
@@ -804,6 +816,14 @@
regmap_read(priv->rst_regmap, WD1RCR, &val);
else if (status & WD2RST)
regmap_read(priv->rst_regmap, WD2RCR, &val);
+ else if (status & SW1RST)
+ regmap_read(priv->rst_regmap, SWRSTC1, &val);
+ else if (status & SW2RST)
+ regmap_read(priv->rst_regmap, SWRSTC2, &val);
+ else if (status & SW3RST)
+ regmap_read(priv->rst_regmap, SWRSTC3, &val);
+ else if (status & TIPRST)
+ regmap_read(priv->rst_regmap, TIPRSTC, &val);
else
return false;