tree 1697676be5ad01f701dd3b7921bf073c3103a367
parent 05c38549add01f73873031cda80bebeb3680a23d
author Pali Rohár <pali@kernel.org> 1621964558 +0200
committer Stefan Roese <sr@denx.de> 1625755252 +0200

serial: a37xx: Fix parent clock rate value and divider calculation

UART parent clock is by default the platform's xtal clock, which is
25 MHz.

The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
  Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in a suboptimal value
for divisor if the correct parent clock rate was used.

Change the code for divisor calculation to round to closest value, i.e.
  Divisor = Round(UART clock / (16 * baudrate))
and change the parent clock rate value to that returned by
get_ref_clk().

This makes A3720 UART stable at standard UART baudrates between 1800 and
230400.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>