tree e9fe6b1ff6f4f9e1907df5390b59bf07fe983766
parent 9fd3c06575be0663cfabb8550acdb1e7ad1d2119
author Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 1565000699 +0530
committer Michal Simek <michal.simek@xilinx.com> 1570518674 +0200

arm64: versal: fpga: Add PL bit stream load support

This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>