Merge patch series "buildman: Add initial support for config fragments"
Simon Glass <sjg@chromium.org> says:
This series updates buildman to process #include lines in defconfig
files. With this, it is no-longer necessary to duplicate lines certain
lines from the include-file in the defconfig, e.g. CONFIG_ARM and
CONFIG_SOC_...
Link: https://lore.kernel.org/r/20241108152350.3686274-1-sjg@chromium.org
diff --git a/Kconfig b/Kconfig
index eb55f25..bd63fea 100644
--- a/Kconfig
+++ b/Kconfig
@@ -595,27 +595,6 @@
WARNING: Please make sure that this value is a multiple of the OS
page size.
-config SYS_HAS_SRAM
- bool
- default y if TARGET_PIC32MZDASK
- default y if TARGET_DEVKIT8000
- help
- Enable this to allow support for the on board SRAM.
- SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
- SRAM size is controlled by CONFIG_SYS_SRAM_SIZE.
-
-config SYS_SRAM_BASE
- hex
- default 0x80000000 if TARGET_PIC32MZDASK
- default 0x40200000 if TARGET_DEVKIT8000
- default 0x0
-
-config SYS_SRAM_SIZE
- hex
- default 0x00080000 if TARGET_PIC32MZDASK
- default 0x10000 if TARGET_DEVKIT8000
- default 0x0
-
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
diff --git a/Makefile b/Makefile
index 7275a02..81b73a1 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 3a04a9f..2c1ab04 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -43,7 +43,6 @@
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
- platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
return 1;
}
diff --git a/arch/Kconfig b/arch/Kconfig
index 8f1f466..c39efb4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -212,7 +212,8 @@
imply VIRTIO_MMIO
imply VIRTIO_PCI
imply VIRTIO_SANDBOX
- imply VIRTIO_BLK
+ # Re-enable this when fully implemented
+ # imply VIRTIO_BLK
imply VIRTIO_NET
imply DM_SOUND
imply PCI_SANDBOX_EP
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index e6be635..5d6953f 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -825,7 +825,7 @@
void dcache_disable(void)
{
- uint32_t sctlr;
+ unsigned long sctlr;
sctlr = get_sctlr();
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index d568efa..82ecf02 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -94,3 +94,8 @@
secure_ram_addr(psci_arch_init)();
}
#endif
+
+void allow_unaligned(void)
+{
+ set_sctlr(get_sctlr() & ~CR_A);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aeccfa9..042282f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -778,8 +778,6 @@
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
- imx6dl-dhcom-pdk2.dtb \
- imx6dl-dhcom-picoitx.dts \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
@@ -811,8 +809,7 @@
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-sielaff.dtb \
- imx6dl-wandboard-revd1.dtb \
- imx6s-dhcom-drc02.dtb
+ imx6dl-wandboard-revd1.dtb
endif
@@ -824,7 +821,6 @@
imx6q-cubox-i.dtb \
imx6q-cubox-i-emmc-som-v15.dtb \
imx6q-cubox-i-som-v15.dtb \
- imx6q-dhcom-pdk2.dtb \
imx6q-display5.dtb \
imx6q-gw51xx.dtb \
imx6q-gw52xx.dtb \
@@ -979,9 +975,6 @@
imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
-dtb-$(CONFIG_TARGET_RZG2L) += \
- r9a07g044l2-smarc.dts
-
ifdef CONFIG_RCAR_64
DTC_FLAGS += -R 4 -p 0x1000
endif
diff --git a/arch/arm/dts/imx6dl-dhcom-pdk2.dts b/arch/arm/dts/imx6dl-dhcom-pdk2.dts
deleted file mode 100644
index d596874..0000000
--- a/arch/arm/dts/imx6dl-dhcom-pdk2.dts
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+)
-/*
- * Copyright (C) 2019 DH electronics GmbH
- */
-
-/dts-v1/;
-
-#include "imx6dl.dtsi"
-#include "imx6qdl-dhcom-som.dtsi"
-#include "imx6qdl-dhcom-pdk2.dtsi"
-
-/ {
- model = "Freescale i.MX6 Duallite/Solo DHCOM Premium Developer Kit (2)";
- compatible = "dh,imx6dl-dhcom-pdk2", "dh,imx6dl-dhcom", "fsl,imx6dl";
-};
diff --git a/arch/arm/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/dts/imx6dl-dhcom-picoitx.dts
deleted file mode 100644
index 038bb00..0000000
--- a/arch/arm/dts/imx6dl-dhcom-picoitx.dts
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2021 DH electronics GmbH
- *
- * DHCOM iMX6 variant:
- * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
- * DHCOM PCB number: 493-300 or newer
- * PicoITX PCB number: 487-600 or newer
- */
-/dts-v1/;
-
-#include "imx6dl.dtsi"
-#include "imx6qdl-dhcom-som.dtsi"
-#include "imx6qdl-dhcom-picoitx.dtsi"
-
-/ {
- model = "DH electronics i.MX6DL DHCOM on PicoITX";
- compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som",
- "fsl,imx6dl";
-};
diff --git a/arch/arm/dts/imx6q-dhcom-pdk2.dts b/arch/arm/dts/imx6q-dhcom-pdk2.dts
deleted file mode 100644
index d4d5737..0000000
--- a/arch/arm/dts/imx6q-dhcom-pdk2.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2021 DH electronics GmbH
- * Copyright (C) 2018 Marek Vasut <marex@denx.de>
- *
- * DHCOM iMX6 variant:
- * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
- * DHCOM PCB number: 493-300 or newer
- * PDK2 PCB number: 516-400 or newer
- */
-/dts-v1/;
-
-#include "imx6q.dtsi"
-#include "imx6qdl-dhcom-som.dtsi"
-#include "imx6qdl-dhcom-pdk2.dtsi"
-
-/ {
- model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)";
- compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som",
- "fsl,imx6q";
-};
-
-&sata {
- status = "okay";
-};
diff --git a/arch/arm/dts/imx6s-dhcom-drc02.dts b/arch/arm/dts/imx6s-dhcom-drc02.dts
deleted file mode 100644
index 4077b60..0000000
--- a/arch/arm/dts/imx6s-dhcom-drc02.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2021 DH electronics GmbH
- *
- * DHCOM iMX6 variant:
- * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2
- * DHCOM PCB number: 493-400 or newer
- * DRC02 PCB number: 568-100 or newer
- */
-/dts-v1/;
-
-/*
- * The kernel only distinguishes between i.MX6 Quad and DualLite,
- * but the Solo is actually a DualLite with only one CPU. So use
- * DualLite for the Solo and disable one CPU node.
- */
-
-#include "imx6dl.dtsi"
-#include "imx6qdl-dhcom-som.dtsi"
-#include "imx6qdl-dhcom-drc02.dtsi"
-
-/ {
- model = "DH electronics i.MX6S DHCOM on DRC02";
- compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
- "fsl,imx6dl";
-
- cpus {
- /delete-node/ cpu@1;
- };
-};
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi
deleted file mode 100644
index 648e7f4..0000000
--- a/arch/arm/dts/meson-a1.dtsi
+++ /dev/null
@@ -1,518 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- */
-
-#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
-#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
-#include <dt-bindings/gpio/meson-a1-gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/meson-a1-power.h>
-#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
-
-/ {
- compatible = "amlogic,a1";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- };
- };
-
- efuse: efuse {
- compatible = "amlogic,meson-gxbb-efuse";
- clocks = <&clkc_periphs CLKID_OTP>;
- #address-cells = <1>;
- #size-cells = <1>;
- secure-monitor = <&sm>;
- power-domains = <&pwrc PWRC_OTP_ID>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x800000>;
- alignment = <0x0 0x400000>;
- linux,cma-default;
- };
- };
-
- sm: secure-monitor {
- compatible = "amlogic,meson-gxbb-sm";
-
- pwrc: power-controller {
- compatible = "amlogic,meson-a1-pwrc";
- #power-domain-cells = <1>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- spifc: spi@fd000400 {
- compatible = "amlogic,a1-spifc";
- reg = <0x0 0xfd000400 0x0 0x290>;
- clocks = <&clkc_periphs CLKID_SPIFC>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&pwrc PWRC_SPIFC_ID>;
- status = "disabled";
- };
-
- apb: bus@fe000000 {
- compatible = "simple-bus";
- reg = <0x0 0xfe000000 0x0 0x1000000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
-
- reset: reset-controller@0 {
- compatible = "amlogic,meson-a1-reset";
- reg = <0x0 0x0 0x0 0x8c>;
- #reset-cells = <1>;
- };
-
- periphs_pinctrl: pinctrl@400 {
- compatible = "amlogic,meson-a1-periphs-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio: bank@400 {
- reg = <0x0 0x0400 0x0 0x003c>,
- <0x0 0x0480 0x0 0x0118>;
- reg-names = "mux", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&periphs_pinctrl 0 0 62>;
- };
-
- i2c0_f11_pins: i2c0-f11 {
- mux {
- groups = "i2c0_sck_f11",
- "i2c0_sda_f12";
- function = "i2c0";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c0_f9_pins: i2c0-f9 {
- mux {
- groups = "i2c0_sck_f9",
- "i2c0_sda_f10";
- function = "i2c0";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_x_pins: i2c1-x {
- mux {
- groups = "i2c1_sck_x",
- "i2c1_sda_x";
- function = "i2c1";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_a_pins: i2c1-a {
- mux {
- groups = "i2c1_sck_a",
- "i2c1_sda_a";
- function = "i2c1";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_x0_pins: i2c2-x0 {
- mux {
- groups = "i2c2_sck_x0",
- "i2c2_sda_x1";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_x15_pins: i2c2-x15 {
- mux {
- groups = "i2c2_sck_x15",
- "i2c2_sda_x16";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_a4_pins: i2c2-a4 {
- mux {
- groups = "i2c2_sck_a4",
- "i2c2_sda_a5";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_a8_pins: i2c2-a8 {
- mux {
- groups = "i2c2_sck_a8",
- "i2c2_sda_a9";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_x_pins: i2c3-x {
- mux {
- groups = "i2c3_sck_x",
- "i2c3_sda_x";
- function = "i2c3";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_f_pins: i2c3-f {
- mux {
- groups = "i2c3_sck_f",
- "i2c3_sda_f";
- function = "i2c3";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- uart_a_pins: uart-a {
- mux {
- groups = "uart_a_tx",
- "uart_a_rx";
- function = "uart_a";
- };
- };
-
- uart_a_cts_rts_pins: uart-a-cts-rts {
- mux {
- groups = "uart_a_cts",
- "uart_a_rts";
- function = "uart_a";
- bias-pull-down;
- };
- };
-
- sdio_pins: sdio {
- mux0 {
- groups = "sdcard_d0_x",
- "sdcard_d1_x",
- "sdcard_d2_x",
- "sdcard_d3_x",
- "sdcard_cmd_x";
- function = "sdcard";
- bias-pull-up;
- };
-
- mux1 {
- groups = "sdcard_clk_x";
- function = "sdcard";
- bias-disable;
- };
- };
-
- sdio_clk_gate_pins: sdio-clk-gate {
- mux {
- groups = "sdcard_clk_x";
- function = "sdcard";
- bias-pull-down;
- };
- };
-
- spifc_pins: spifc {
- mux {
- groups = "spif_mo",
- "spif_mi",
- "spif_clk",
- "spif_cs",
- "spif_hold_n",
- "spif_wp_n";
- function = "spif";
- };
- };
- };
-
- gpio_intc: interrupt-controller@440 {
- compatible = "amlogic,meson-a1-gpio-intc",
- "amlogic,meson-gpio-intc";
- reg = <0x0 0x0440 0x0 0x14>;
- interrupt-controller;
- #interrupt-cells = <2>;
- amlogic,channel-interrupts =
- <49 50 51 52 53 54 55 56>;
- };
-
- clkc_periphs: clock-controller@800 {
- compatible = "amlogic,a1-peripherals-clkc";
- reg = <0 0x800 0 0x104>;
- #clock-cells = <1>;
- clocks = <&clkc_pll CLKID_FCLK_DIV2>,
- <&clkc_pll CLKID_FCLK_DIV3>,
- <&clkc_pll CLKID_FCLK_DIV5>,
- <&clkc_pll CLKID_FCLK_DIV7>,
- <&clkc_pll CLKID_HIFI_PLL>,
- <&xtal>;
- clock-names = "fclk_div2", "fclk_div3",
- "fclk_div5", "fclk_div7",
- "hifi_pll", "xtal";
- };
-
- i2c0: i2c@1400 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x1400 0x0 0x20>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_A>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- uart_AO: serial@1c00 {
- compatible = "amlogic,meson-a1-uart",
- "amlogic,meson-ao-uart";
- reg = <0x0 0x1c00 0x0 0x18>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- uart_AO_B: serial@2000 {
- compatible = "amlogic,meson-a1-uart",
- "amlogic,meson-ao-uart";
- reg = <0x0 0x2000 0x0 0x18>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- saradc: adc@2c00 {
- compatible = "amlogic,meson-g12a-saradc",
- "amlogic,meson-saradc";
- reg = <0x0 0x2c00 0x0 0x48>;
- #io-channel-cells = <1>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>,
- <&clkc_periphs CLKID_SARADC_EN>,
- <&clkc_periphs CLKID_SARADC>,
- <&clkc_periphs CLKID_SARADC_SEL>;
- clock-names = "clkin", "core",
- "adc_clk", "adc_sel";
- status = "disabled";
- };
-
- i2c1: i2c@5c00 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x5c00 0x0 0x20>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_B>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- i2c2: i2c@6800 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x6800 0x0 0x20>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_C>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- i2c3: i2c@6c00 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x6c00 0x0 0x20>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_D>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- usb2_phy1: phy@4000 {
- compatible = "amlogic,a1-usb2-phy";
- clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
- clock-names = "xtal";
- reg = <0x0 0x4000 0x0 0x60>;
- resets = <&reset RESET_USBPHY>;
- reset-names = "phy";
- #phy-cells = <0>;
- power-domains = <&pwrc PWRC_USB_ID>;
- };
-
- hwrng: rng@5118 {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0x5118 0x0 0x4>;
- power-domains = <&pwrc PWRC_OTP_ID>;
- };
-
- sec_AO: ao-secure@5a20 {
- compatible = "amlogic,meson-gx-ao-secure", "syscon";
- reg = <0x0 0x5a20 0x0 0x140>;
- amlogic,has-chip-id;
- };
-
- clkc_pll: pll-clock-controller@7c80 {
- compatible = "amlogic,a1-pll-clkc";
- reg = <0 0x7c80 0 0x18c>;
- #clock-cells = <1>;
- clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
- <&clkc_periphs CLKID_HIFIPLL_IN>;
- clock-names = "fixpll_in", "hifipll_in";
- };
-
- sd_emmc: sd@10000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0x10000 0x0 0x800>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
- <&clkc_periphs CLKID_SD_EMMC>,
- <&clkc_pll CLKID_FCLK_DIV2>;
- clock-names = "core",
- "clkin0",
- "clkin1";
- assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
- assigned-clock-parents = <&xtal>;
- resets = <&reset RESET_SD_EMMC_A>;
- power-domains = <&pwrc PWRC_SD_EMMC_ID>;
- status = "disabled";
- };
- };
-
- usb: usb@fe004400 {
- status = "disabled";
- compatible = "amlogic,meson-a1-usb-ctrl";
- reg = <0x0 0xfe004400 0x0 0xa0>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc_periphs CLKID_USB_CTRL>,
- <&clkc_periphs CLKID_USB_BUS>,
- <&clkc_periphs CLKID_USB_CTRL_IN>;
- clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
- resets = <&reset RESET_USBCTRL>;
- reset-name = "usb_ctrl";
-
- dr_mode = "otg";
-
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy1";
-
- dwc3: usb@ff400000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xff400000 0x0 0x100000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,dis_u2_susphy_quirk;
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,parkmode-disable-ss-quirk;
- };
-
- dwc2: usb@ff500000 {
- compatible = "amlogic,meson-a1-usb", "snps,dwc2";
- reg = <0x0 0xff500000 0x0 0x40000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy";
- clocks = <&clkc_periphs CLKID_USB_PHY>;
- clock-names = "otg";
- dr_mode = "peripheral";
- g-rx-fifo-size = <192>;
- g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 16 16 16>;
- };
- };
-
- gic: interrupt-controller@ff901000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xff901000 0x0 0x1000>,
- <0x0 0xff902000 0x0 0x2000>,
- <0x0 0xff904000 0x0 0x2000>,
- <0x0 0xff906000 0x0 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-};
diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi
new file mode 100644
index 0000000..dd5a208
--- /dev/null
+++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board
+ *
+ * Copyright (C) 2021-2024 Renesas Electronics Corporation
+ */
+
+#include "r8a774a1-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi
deleted file mode 100644
index 3ad619b..0000000
--- a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board
- *
- * Copyright (C) 2021 Renesas Electronics Corporation
- */
-
-#include "r8a774a1-u-boot.dtsi"
-
-&gpio3 {
- bt_reg_on{
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "bt-reg-on";
- };
-};
-
-&gpio4 {
- wlan_reg_on{
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "wlan-reg-on";
- };
-};
diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi
index 38f5bfe..3530eeb 100644
--- a/arch/arm/dts/r8a774a1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774a1-u-boot.dtsi
@@ -10,45 +10,3 @@
&extalr_clk {
bootph-all;
};
-
-/delete-node/ &audma0;
-/delete-node/ &audma1;
-/delete-node/ &can0;
-/delete-node/ &can1;
-/delete-node/ &canfd;
-/delete-node/ &csi20;
-/delete-node/ &csi40;
-/delete-node/ &du;
-/delete-node/ &fcpf0;
-/delete-node/ &fcpvb0;
-/delete-node/ &fcpvd0;
-/delete-node/ &fcpvd1;
-/delete-node/ &fcpvd2;
-/delete-node/ &fcpvi0;
-/delete-node/ &hdmi0;
-/delete-node/ &lvds0;
-/delete-node/ &rcar_sound;
-/delete-node/ &sound_card;
-/delete-node/ &vin0;
-/delete-node/ &vin1;
-/delete-node/ &vin2;
-/delete-node/ &vin3;
-/delete-node/ &vin4;
-/delete-node/ &vin5;
-/delete-node/ &vin6;
-/delete-node/ &vin7;
-/delete-node/ &vspb;
-/delete-node/ &vspd0;
-/delete-node/ &vspd1;
-/delete-node/ &vspd2;
-/delete-node/ &vspi0;
-
-/ {
- /delete-node/ hdmi0-out;
-};
-
-/ {
- soc {
- /delete-node/ fdp1@fe940000;
- };
-};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi
new file mode 100644
index 0000000..b378cab
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2021-2024 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi
deleted file mode 100644
index 6f2f6c7..0000000
--- a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include "r8a774b1-u-boot.dtsi"
-
-&gpio3 {
- bt_reg_on{
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "bt-reg-on";
- };
-};
-
-&gpio4 {
- wlan_reg_on{
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "wlan-reg-on";
- };
-};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi
index d4890eb..07aeabc 100644
--- a/arch/arm/dts/r8a774b1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -10,43 +10,3 @@
&extalr_clk {
bootph-all;
};
-
-/delete-node/ &audma0;
-/delete-node/ &audma1;
-/delete-node/ &can0;
-/delete-node/ &can1;
-/delete-node/ &canfd;
-/delete-node/ &csi20;
-/delete-node/ &csi40;
-/delete-node/ &du;
-/delete-node/ &fcpf0;
-/delete-node/ &fcpvb0;
-/delete-node/ &fcpvd0;
-/delete-node/ &fcpvd1;
-/delete-node/ &fcpvi0;
-/delete-node/ &hdmi0;
-/delete-node/ &lvds0;
-/delete-node/ &rcar_sound;
-/delete-node/ &sound_card;
-/delete-node/ &vin0;
-/delete-node/ &vin1;
-/delete-node/ &vin2;
-/delete-node/ &vin3;
-/delete-node/ &vin4;
-/delete-node/ &vin5;
-/delete-node/ &vin6;
-/delete-node/ &vin7;
-/delete-node/ &vspb;
-/delete-node/ &vspd0;
-/delete-node/ &vspd1;
-/delete-node/ &vspi0;
-
-/ {
- /delete-node/ hdmi0-out;
-};
-
-/ {
- soc {
- /delete-node/ fdp1@fe940000;
- };
-};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi
new file mode 100644
index 0000000..560bea4
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
+ *
+ * Copyright (C) 2020-2024 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-u-boot.dtsi"
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi
deleted file mode 100644
index 8e57e03..0000000
--- a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include "r8a774e1-u-boot.dtsi"
-
-&gpio3 {
- bt_reg_on{
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "bt-reg-on";
- };
-};
-
-&gpio4 {
- wlan_reg_on{
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "wlan-reg-on";
- };
-};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi
index 45ef5b7..2202731 100644
--- a/arch/arm/dts/r8a774e1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -10,49 +10,3 @@
&extalr_clk {
bootph-all;
};
-
-/delete-node/ &audma0;
-/delete-node/ &audma1;
-/delete-node/ &can0;
-/delete-node/ &can1;
-/delete-node/ &canfd;
-/delete-node/ &csi20;
-/delete-node/ &csi40;
-/delete-node/ &du;
-/delete-node/ &fcpf0;
-/delete-node/ &fcpf1;
-/delete-node/ &fcpvb0;
-/delete-node/ &fcpvb1;
-/delete-node/ &fcpvd0;
-/delete-node/ &fcpvd1;
-/delete-node/ &fcpvi0;
-/delete-node/ &fcpvi1;
-/delete-node/ &hdmi0;
-/delete-node/ &lvds0;
-/delete-node/ &rcar_sound;
-/delete-node/ &sound_card;
-/delete-node/ &vin0;
-/delete-node/ &vin1;
-/delete-node/ &vin2;
-/delete-node/ &vin3;
-/delete-node/ &vin4;
-/delete-node/ &vin5;
-/delete-node/ &vin6;
-/delete-node/ &vin7;
-/delete-node/ &vspbc;
-/delete-node/ &vspbd;
-/delete-node/ &vspd0;
-/delete-node/ &vspd1;
-/delete-node/ &vspi0;
-/delete-node/ &vspi1;
-
-/ {
- /delete-node/ hdmi0-out;
-};
-
-/ {
- soc {
- /delete-node/ fdp1@fe940000;
- /delete-node/ fdp1@fe944000;
- };
-};
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
deleted file mode 100644
index 66f68fc..0000000
--- a/arch/arm/dts/r9a07g044.dtsi
+++ /dev/null
@@ -1,1273 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/r9a07g044-cpg.h>
-
-/ {
- compatible = "renesas,r9a07g044";
- #address-cells = <2>;
- #size-cells = <2>;
-
- audio_clk1: audio1-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by boards that provide it */
- clock-frequency = <0>;
- };
-
- audio_clk2: audio2-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by boards that provide it */
- clock-frequency = <0>;
- };
-
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
- extal_clk: extal-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
- cluster0_opp: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-150000000 {
- opp-hz = /bits/ 64 <150000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <300000>;
- };
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <300000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <300000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1100000>;
- clock-latency-ns = <300000>;
- opp-suspend;
- };
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- };
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a55";
- reg = <0>;
- device_type = "cpu";
- #cooling-cells = <2>;
- next-level-cache = <&L3_CA55>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- cpu1: cpu@100 {
- compatible = "arm,cortex-a55";
- reg = <0x100>;
- device_type = "cpu";
- next-level-cache = <&L3_CA55>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- L3_CA55: cache-controller-0 {
- compatible = "cache";
- cache-unified;
- cache-size = <0x40000>;
- cache-level = <3>;
- };
- };
-
- gpu_opp_table: opp-table-1 {
- compatible = "operating-points-v2";
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-125000000 {
- opp-hz = /bits/ 64 <125000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-62500000 {
- opp-hz = /bits/ 64 <62500000>;
- opp-microvolt = <1100000>;
- };
-
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- opp-microvolt = <1100000>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a55-pmu";
- interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- soc: soc {
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- mtu3: timer@10001200 {
- compatible = "renesas,r9a07g044-mtu3",
- "renesas,rz-mtu3";
- reg = <0 0x10001200 0 0xb00>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
- "tciv0", "tgie0", "tgif0",
- "tgia1", "tgib1", "tciv1", "tciu1",
- "tgia2", "tgib2", "tciv2", "tciu2",
- "tgia3", "tgib3", "tgic3", "tgid3",
- "tciv3",
- "tgia4", "tgib4", "tgic4", "tgid4",
- "tciv4",
- "tgiu5", "tgiv5", "tgiw5",
- "tgia6", "tgib6", "tgic6", "tgid6",
- "tciv6",
- "tgia7", "tgib7", "tgic7", "tgid7",
- "tciv7",
- "tgia8", "tgib8", "tgic8", "tgid8",
- "tciv8", "tciu8";
- clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- ssi0: ssi@10049c00 {
- compatible = "renesas,r9a07g044-ssi",
- "renesas,rz-ssi";
- reg = <0 0x10049c00 0 0x400>;
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx";
- clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
- <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
- <&audio_clk1>, <&audio_clk2>;
- clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
- resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
- dmas = <&dmac 0x2655>, <&dmac 0x2656>;
- dma-names = "tx", "rx";
- power-domains = <&cpg>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- ssi1: ssi@1004a000 {
- compatible = "renesas,r9a07g044-ssi",
- "renesas,rz-ssi";
- reg = <0 0x1004a000 0 0x400>;
- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx";
- clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
- <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
- <&audio_clk1>, <&audio_clk2>;
- clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
- resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
- dmas = <&dmac 0x2659>, <&dmac 0x265a>;
- dma-names = "tx", "rx";
- power-domains = <&cpg>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- ssi2: ssi@1004a400 {
- compatible = "renesas,r9a07g044-ssi",
- "renesas,rz-ssi";
- reg = <0 0x1004a400 0 0x400>;
- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rt";
- clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
- <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
- <&audio_clk1>, <&audio_clk2>;
- clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
- resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
- dmas = <&dmac 0x265f>;
- dma-names = "rt";
- power-domains = <&cpg>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- ssi3: ssi@1004a800 {
- compatible = "renesas,r9a07g044-ssi",
- "renesas,rz-ssi";
- reg = <0 0x1004a800 0 0x400>;
- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "int_req", "dma_rx", "dma_tx";
- clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
- <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
- <&audio_clk1>, <&audio_clk2>;
- clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
- resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
- dmas = <&dmac 0x2661>, <&dmac 0x2662>;
- dma-names = "tx", "rx";
- power-domains = <&cpg>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- spi0: spi@1004ac00 {
- compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
- reg = <0 0x1004ac00 0 0x400>;
- interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error", "rx", "tx";
- clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
- resets = <&cpg R9A07G044_RSPI0_RST>;
- dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
- dma-names = "tx", "rx";
- power-domains = <&cpg>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@1004b000 {
- compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
- reg = <0 0x1004b000 0 0x400>;
- interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error", "rx", "tx";
- clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
- resets = <&cpg R9A07G044_RSPI1_RST>;
- dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
- dma-names = "tx", "rx";
- power-domains = <&cpg>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@1004b400 {
- compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
- reg = <0 0x1004b400 0 0x400>;
- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "error", "rx", "tx";
- clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
- resets = <&cpg R9A07G044_RSPI2_RST>;
- dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
- dma-names = "tx", "rx";
- power-domains = <&cpg>;
- num-cs = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- scif0: serial@1004b800 {
- compatible = "renesas,scif-r9a07g044";
- reg = <0 0x1004b800 0 0x400>;
- interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eri", "rxi", "txi",
- "bri", "dri", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
- clock-names = "fck";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
- status = "disabled";
- };
-
- scif1: serial@1004bc00 {
- compatible = "renesas,scif-r9a07g044";
- reg = <0 0x1004bc00 0 0x400>;
- interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eri", "rxi", "txi",
- "bri", "dri", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
- clock-names = "fck";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
- status = "disabled";
- };
-
- scif2: serial@1004c000 {
- compatible = "renesas,scif-r9a07g044";
- reg = <0 0x1004c000 0 0x400>;
- interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eri", "rxi", "txi",
- "bri", "dri", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
- clock-names = "fck";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
- status = "disabled";
- };
-
- scif3: serial@1004c400 {
- compatible = "renesas,scif-r9a07g044";
- reg = <0 0x1004c400 0 0x400>;
- interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eri", "rxi", "txi",
- "bri", "dri", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
- clock-names = "fck";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
- status = "disabled";
- };
-
- scif4: serial@1004c800 {
- compatible = "renesas,scif-r9a07g044";
- reg = <0 0x1004c800 0 0x400>;
- interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eri", "rxi", "txi",
- "bri", "dri", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
- clock-names = "fck";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
- status = "disabled";
- };
-
- sci0: serial@1004d000 {
- compatible = "renesas,r9a07g044-sci", "renesas,sci";
- reg = <0 0x1004d000 0 0x400>;
- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eri", "rxi", "txi", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
- clock-names = "fck";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_SCI0_RST>;
- status = "disabled";
- };
-
- sci1: serial@1004d400 {
- compatible = "renesas,r9a07g044-sci", "renesas,sci";
- reg = <0 0x1004d400 0 0x400>;
- interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eri", "rxi", "txi", "tei";
- clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
- clock-names = "fck";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_SCI1_RST>;
- status = "disabled";
- };
-
- canfd: can@10050000 {
- compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
- reg = <0 0x10050000 0 0x8000>;
- interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g_err", "g_recc",
- "ch0_err", "ch0_rec", "ch0_trx",
- "ch1_err", "ch1_rec", "ch1_trx";
- clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
- <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
- assigned-clock-rates = <50000000>;
- resets = <&cpg R9A07G044_CANFD_RSTP_N>,
- <&cpg R9A07G044_CANFD_RSTC_N>;
- reset-names = "rstp_n", "rstc_n";
- power-domains = <&cpg>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
- channel1 {
- status = "disabled";
- };
- };
-
- i2c0: i2c@10058000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
- reg = <0 0x10058000 0 0x400>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tei", "ri", "ti", "spi", "sti",
- "naki", "ali", "tmoi";
- clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
- clock-frequency = <100000>;
- resets = <&cpg R9A07G044_I2C0_MRST>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- i2c1: i2c@10058400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
- reg = <0 0x10058400 0 0x400>;
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tei", "ri", "ti", "spi", "sti",
- "naki", "ali", "tmoi";
- clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
- clock-frequency = <100000>;
- resets = <&cpg R9A07G044_I2C1_MRST>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- i2c2: i2c@10058800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
- reg = <0 0x10058800 0 0x400>;
- interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tei", "ri", "ti", "spi", "sti",
- "naki", "ali", "tmoi";
- clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
- clock-frequency = <100000>;
- resets = <&cpg R9A07G044_I2C2_MRST>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- i2c3: i2c@10058c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
- reg = <0 0x10058c00 0 0x400>;
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tei", "ri", "ti", "spi", "sti",
- "naki", "ali", "tmoi";
- clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
- clock-frequency = <100000>;
- resets = <&cpg R9A07G044_I2C3_MRST>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- adc: adc@10059000 {
- compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
- reg = <0 0x10059000 0 0x400>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
- clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
- <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
- clock-names = "adclk", "pclk";
- resets = <&cpg R9A07G044_ADC_PRESETN>,
- <&cpg R9A07G044_ADC_ADRST_N>;
- reset-names = "presetn", "adrst-n";
- power-domains = <&cpg>;
- status = "disabled";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@0 {
- reg = <0>;
- };
- channel@1 {
- reg = <1>;
- };
- channel@2 {
- reg = <2>;
- };
- channel@3 {
- reg = <3>;
- };
- channel@4 {
- reg = <4>;
- };
- channel@5 {
- reg = <5>;
- };
- channel@6 {
- reg = <6>;
- };
- channel@7 {
- reg = <7>;
- };
- };
-
- tsu: thermal@10059400 {
- compatible = "renesas,r9a07g044-tsu",
- "renesas,rzg2l-tsu";
- reg = <0 0x10059400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
- resets = <&cpg R9A07G044_TSU_PRESETN>;
- power-domains = <&cpg>;
- #thermal-sensor-cells = <1>;
- };
-
- sbc: spi@10060000 {
- compatible = "renesas,r9a07g044-rpc-if",
- "renesas,rzg2l-rpc-if";
- reg = <0 0x10060000 0 0x10000>,
- <0 0x20000000 0 0x10000000>,
- <0 0x10070000 0 0x10000>;
- reg-names = "regs", "dirmap", "wbuf";
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
- <&cpg CPG_MOD R9A07G044_SPI_CLK>;
- resets = <&cpg R9A07G044_SPI_RST>;
- power-domains = <&cpg>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- cru: video@10830000 {
- compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
- reg = <0 0x10830000 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
- <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
- <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
- clock-names = "video", "apb", "axi";
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
- resets = <&cpg R9A07G044_CRU_PRESETN>,
- <&cpg R9A07G044_CRU_ARESETN>;
- reset-names = "presetn", "aresetn";
- power-domains = <&cpg>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <0>;
- cruparallel: endpoint@0 {
- reg = <0>;
- };
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
- crucsi2: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&csi2cru>;
- };
- };
- };
- };
-
- csi2: csi2@10830400 {
- compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
- reg = <0 0x10830400 0 0xfc00>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
- <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
- <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
- clock-names = "system", "video", "apb";
- resets = <&cpg R9A07G044_CRU_PRESETN>,
- <&cpg R9A07G044_CRU_CMN_RSTB>;
- reset-names = "presetn", "cmn-rstb";
- power-domains = <&cpg>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- csi2cru: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&crucsi2>;
- };
- };
- };
- };
-
- dsi: dsi@10850000 {
- compatible = "renesas,r9a07g044-mipi-dsi",
- "renesas,rzg2l-mipi-dsi";
- reg = <0 0x10850000 0 0x20000>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "seq0", "seq1", "vin1", "rcv",
- "ferr", "ppi", "debug";
- clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
- <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
- <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
- <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
- <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
- <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
- clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
- resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
- <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
- <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
- reset-names = "rst", "arst", "prst";
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- vspd: vsp@10870000 {
- compatible = "renesas,r9a07g044-vsp2";
- reg = <0 0x10870000 0 0x10000>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
- <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
- <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
- clock-names = "aclk", "pclk", "vclk";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_LCDC_RESET_N>;
- renesas,fcp = <&fcpvd>;
- };
-
- fcpvd: fcp@10880000 {
- compatible = "renesas,r9a07g044-fcpvd",
- "renesas,fcpv";
- reg = <0 0x10880000 0 0x10000>;
- clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
- <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
- <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
- clock-names = "aclk", "pclk", "vclk";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_LCDC_RESET_N>;
- };
-
- cpg: clock-controller@11010000 {
- compatible = "renesas,r9a07g044-cpg";
- reg = <0 0x11010000 0 0x10000>;
- clocks = <&extal_clk>;
- clock-names = "extal";
- #clock-cells = <2>;
- #reset-cells = <1>;
- #power-domain-cells = <0>;
- };
-
- sysc: system-controller@11020000 {
- compatible = "renesas,r9a07g044-sysc";
- reg = <0 0x11020000 0 0x10000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "lpm_int", "ca55stbydone_int",
- "cm33stbyr_int", "ca55_deny";
- status = "disabled";
- };
-
- pinctrl: pinctrl@11030000 {
- compatible = "renesas,r9a07g044-pinctrl";
- reg = <0 0x11030000 0 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- interrupt-parent = <&irqc>;
- interrupt-controller;
- gpio-ranges = <&pinctrl 0 0 392>;
- clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_GPIO_RSTN>,
- <&cpg R9A07G044_GPIO_PORT_RESETN>,
- <&cpg R9A07G044_GPIO_SPARE_RESETN>;
- };
-
- irqc: interrupt-controller@110a0000 {
- compatible = "renesas,r9a07g044-irqc",
- "renesas,rzg2l-irqc";
- #interrupt-cells = <2>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0x110a0000 0 0x10000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
- <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
- clock-names = "clk", "pclk";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_IA55_RESETN>;
- };
-
- dmac: dma-controller@11820000 {
- compatible = "renesas,r9a07g044-dmac",
- "renesas,rz-dmac";
- reg = <0 0x11820000 0 0x10000>,
- <0 0x11830000 0 0x10000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15";
- clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
- <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
- clock-names = "main", "register";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_DMAC_ARESETN>,
- <&cpg R9A07G044_DMAC_RST_ASYNC>;
- reset-names = "arst", "rst_async";
- #dma-cells = <1>;
- dma-channels = <16>;
- };
-
- gpu: gpu@11840000 {
- compatible = "renesas,r9a07g044-mali",
- "arm,mali-bifrost";
- reg = <0x0 0x11840000 0x0 0x10000>;
- interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "job", "mmu", "gpu", "event";
- clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
- <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
- <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
- clock-names = "gpu", "bus", "bus_ace";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_GPU_RESETN>,
- <&cpg R9A07G044_GPU_AXI_RESETN>,
- <&cpg R9A07G044_GPU_ACE_RESETN>;
- reset-names = "rst", "axi_rst", "ace_rst";
- operating-points-v2 = <&gpu_opp_table>;
- };
-
- gic: interrupt-controller@11900000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x11900000 0 0x40000>,
- <0x0 0x11940000 0 0x60000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
- };
-
- sdhi0: mmc@11c00000 {
- compatible = "renesas,sdhi-r9a07g044",
- "renesas,rcar-gen3-sdhi";
- reg = <0x0 0x11c00000 0 0x10000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
- <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
- <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
- <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
- clock-names = "core", "clkh", "cd", "aclk";
- resets = <&cpg R9A07G044_SDHI0_IXRST>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- sdhi1: mmc@11c10000 {
- compatible = "renesas,sdhi-r9a07g044",
- "renesas,rcar-gen3-sdhi";
- reg = <0x0 0x11c10000 0 0x10000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
- <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
- <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
- <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
- clock-names = "core", "clkh", "cd", "aclk";
- resets = <&cpg R9A07G044_SDHI1_IXRST>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- eth0: ethernet@11c20000 {
- compatible = "renesas,r9a07g044-gbeth",
- "renesas,rzg2l-gbeth";
- reg = <0 0x11c20000 0 0x10000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mux", "fil", "arp_ns";
- phy-mode = "rgmii";
- clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
- <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
- <&cpg CPG_CORE R9A07G044_CLK_HP>;
- clock-names = "axi", "chi", "refclk";
- resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
- power-domains = <&cpg>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- eth1: ethernet@11c30000 {
- compatible = "renesas,r9a07g044-gbeth",
- "renesas,rzg2l-gbeth";
- reg = <0 0x11c30000 0 0x10000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mux", "fil", "arp_ns";
- phy-mode = "rgmii";
- clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
- <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
- <&cpg CPG_CORE R9A07G044_CLK_HP>;
- clock-names = "axi", "chi", "refclk";
- resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
- power-domains = <&cpg>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- phyrst: usbphy-ctrl@11c40000 {
- compatible = "renesas,r9a07g044-usbphy-ctrl",
- "renesas,rzg2l-usbphy-ctrl";
- reg = <0 0x11c40000 0 0x10000>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
- resets = <&cpg R9A07G044_USB_PRESETN>;
- power-domains = <&cpg>;
- #reset-cells = <1>;
- status = "disabled";
- };
-
- ohci0: usb@11c50000 {
- compatible = "generic-ohci";
- reg = <0 0x11c50000 0 0x100>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
- <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
- resets = <&phyrst 0>,
- <&cpg R9A07G044_USB_U2H0_HRESETN>;
- phys = <&usb2_phy0 1>;
- phy-names = "usb";
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- ohci1: usb@11c70000 {
- compatible = "generic-ohci";
- reg = <0 0x11c70000 0 0x100>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
- <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
- resets = <&phyrst 1>,
- <&cpg R9A07G044_USB_U2H1_HRESETN>;
- phys = <&usb2_phy1 1>;
- phy-names = "usb";
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- ehci0: usb@11c50100 {
- compatible = "generic-ehci";
- reg = <0 0x11c50100 0 0x100>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
- <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
- resets = <&phyrst 0>,
- <&cpg R9A07G044_USB_U2H0_HRESETN>;
- phys = <&usb2_phy0 2>;
- phy-names = "usb";
- companion = <&ohci0>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- ehci1: usb@11c70100 {
- compatible = "generic-ehci";
- reg = <0 0x11c70100 0 0x100>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
- <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
- resets = <&phyrst 1>,
- <&cpg R9A07G044_USB_U2H1_HRESETN>;
- phys = <&usb2_phy1 2>;
- phy-names = "usb";
- companion = <&ohci1>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- usb2_phy0: usb-phy@11c50200 {
- compatible = "renesas,usb2-phy-r9a07g044",
- "renesas,rzg2l-usb2-phy";
- reg = <0 0x11c50200 0 0x700>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
- <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
- resets = <&phyrst 0>;
- #phy-cells = <1>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- usb2_phy1: usb-phy@11c70200 {
- compatible = "renesas,usb2-phy-r9a07g044",
- "renesas,rzg2l-usb2-phy";
- reg = <0 0x11c70200 0 0x700>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
- <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
- resets = <&phyrst 1>;
- #phy-cells = <1>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- hsusb: usb@11c60000 {
- compatible = "renesas,usbhs-r9a07g044",
- "renesas,rza2-usbhs";
- reg = <0 0x11c60000 0 0x10000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
- <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
- resets = <&phyrst 0>,
- <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
- renesas,buswait = <7>;
- phys = <&usb2_phy0 3>;
- phy-names = "usb";
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- wdt0: watchdog@12800800 {
- compatible = "renesas,r9a07g044-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800800 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
- <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G044_WDT0_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- wdt1: watchdog@12800c00 {
- compatible = "renesas,r9a07g044-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800C00 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
- <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G044_WDT1_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- ostm0: timer@12801000 {
- compatible = "renesas,r9a07g044-ostm",
- "renesas,ostm";
- reg = <0x0 0x12801000 0x0 0x400>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
- clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
- resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- ostm1: timer@12801400 {
- compatible = "renesas,r9a07g044-ostm",
- "renesas,ostm";
- reg = <0x0 0x12801400 0x0 0x400>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
- clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
- resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- ostm2: timer@12801800 {
- compatible = "renesas,r9a07g044-ostm",
- "renesas,ostm";
- reg = <0x0 0x12801800 0x0 0x400>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
- clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
- resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
- power-domains = <&cpg>;
- status = "disabled";
- };
- };
-
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsu 0>;
- sustainable-power = <717>;
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&cpu0 0 2>;
- contribution = <1024>;
- };
- };
-
- trips {
- sensor_crit: sensor-crit {
- temperature = <125000>;
- hysteresis = <1000>;
- type = "critical";
- };
-
- target: trip-point {
- temperature = <100000>;
- hysteresis = <1000>;
- type = "passive";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-};
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts b/arch/arm/dts/r9a07g044l2-smarc.dts
deleted file mode 100644
index 568d49c..0000000
--- a/arch/arm/dts/r9a07g044l2-smarc.dts
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G2L SMARC EVK board
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-
-/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
-#define PMOD1_SER0 1
-
-/*
- * To enable MTU3a PWM on PMOD0,
- * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
- * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
- */
-#define PMOD_MTU3 0
-
-#if (PMOD_MTU3 && PMOD1_SER0)
-#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
-#endif
-
-#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
-
-#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
-#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
-#endif
-
-#include "r9a07g044l2.dtsi"
-#include "rzg2l-smarc-som.dtsi"
-#include "rzg2l-smarc-pinfunction.dtsi"
-#include "rz-smarc-common.dtsi"
-#include "rzg2l-smarc.dtsi"
-
-/ {
- model = "Renesas SMARC EVK based on r9a07g044l2";
- compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
-};
diff --git a/arch/arm/dts/r9a07g044l2.dtsi b/arch/arm/dts/r9a07g044l2.dtsi
deleted file mode 100644
index 91dc10b..0000000
--- a/arch/arm/dts/r9a07g044l2.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r9a07g044.dtsi"
-
-/ {
- compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
-};
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi
new file mode 100644
index 0000000..2ab32cf
--- /dev/null
+++ b/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rk3328-nanopi-r2s-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi b/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi
new file mode 100644
index 0000000..19acbce
--- /dev/null
+++ b/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#include "rk356x-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi
new file mode 100644
index 0000000..5a3073d
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+&fspim2_pins {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sfc {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
+
+/* USB A out */
+&usb_host1_xhci {
+ snps,dis_u3_susphy_quirk;
+};
diff --git a/arch/arm/dts/rz-smarc-common.dtsi b/arch/arm/dts/rz-smarc-common.dtsi
deleted file mode 100644
index b7a3e6c..0000000
--- a/arch/arm/dts/rz-smarc-common.dtsi
+++ /dev/null
@@ -1,183 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
-
-/*
- * SSI-WM8978
- *
- * This command is required when Playback/Capture
- *
- * amixer cset name='Left Input Mixer L2 Switch' on
- * amixer cset name='Right Input Mixer R2 Switch' on
- * amixer cset name='Headphone Playback Volume' 100
- * amixer cset name='PCM Volume' 100%
- * amixer cset name='Input PGA Volume' 25
- *
- */
-
-/ {
- aliases {
- serial0 = &scif0;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- snd_rzg2l: sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&cpu_dai>;
- simple-audio-card,frame-master = <&cpu_dai>;
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,widgets = "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "L2", "Mic Bias",
- "R2", "Mic Bias",
- "Mic Bias", "Microphone Jack";
-
- cpu_dai: simple-audio-card,cpu {
- };
-
- codec_dai: simple-audio-card,codec {
- clocks = <&versa3 2>;
- sound-dai = <&wm8978>;
- };
- };
-
- usb0_vbus_otg: regulator-usb0-vbus-otg {
- compatible = "regulator-fixed";
-
- regulator-name = "USB0_VBUS_OTG";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-
- x1: x1-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-};
-
-&audio_clk1 {
- clock-frequency = <11289600>;
-};
-
-&audio_clk2 {
- clock-frequency = <12288000>;
-};
-
-&canfd {
- pinctrl-0 = <&can0_pins &can1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- channel0 {
- status = "okay";
- };
-
- channel1 {
- status = "okay";
- };
-};
-
-&ehci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&hsusb {
- dr_mode = "otg";
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&ohci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&phyrst {
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-1 = <&sdhi1_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <&vccq_sdhi1>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-0 = <&spi1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- vbus-supply = <&usb0_vbus_otg>;
- status = "okay";
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
diff --git a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
deleted file mode 100644
index 18c526c..0000000
--- a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
-
-&pinctrl {
- pinctrl-0 = <&sound_clk_pins>;
- pinctrl-names = "default";
-
- can0_pins: can0 {
- pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
- <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
- };
-
- /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
- can0-stb-hog {
- gpio-hog;
- gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "can0_stb";
- };
-
- can1_pins: can1 {
- pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
- <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
- };
-
- /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
- can1-stb-hog {
- gpio-hog;
- gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "can1_stb";
- };
-
- i2c0_pins: i2c0 {
- pins = "RIIC0_SDA", "RIIC0_SCL";
- input-enable;
- };
-
- i2c1_pins: i2c1 {
- pins = "RIIC1_SDA", "RIIC1_SCL";
- input-enable;
- };
-
- i2c3_pins: i2c3 {
- pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
- <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
- };
-
- mtu3_pins: mtu3 {
- mtu3-ext-clk-input-pin {
- pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
- <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
- };
-
- mtu3-pwm {
- pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
- <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
- <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
- <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
- };
-
-#if MTU3_COUNTER_Z_PHASE_SIGNAL
- mtu3-zphase-clk {
- pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
- };
-#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
- };
-
- scif0_pins: scif0 {
- pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
- <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
- };
-
- scif2_pins: scif2 {
- pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
- <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
- <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
- <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
- };
-
- sd1-pwr-en-hog {
- gpio-hog;
- gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "sd1_pwr_en";
- };
-
- sdhi1_pins: sd1 {
- sd1_data {
- pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
- power-source = <3300>;
- };
-
- sd1_ctrl {
- pins = "SD1_CLK", "SD1_CMD";
- power-source = <3300>;
- };
-
- sd1_mux {
- pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
- };
- };
-
- sdhi1_pins_uhs: sd1_uhs {
- sd1_data_uhs {
- pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
- power-source = <1800>;
- };
-
- sd1_ctrl_uhs {
- pins = "SD1_CLK", "SD1_CMD";
- power-source = <1800>;
- };
-
- sd1_mux_uhs {
- pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
- };
- };
-
- sound_clk_pins: sound_clk {
- pins = "AUDIO_CLK1", "AUDIO_CLK2";
- input-enable;
- };
-
- spi1_pins: spi1 {
- pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
- <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
- <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
- <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
- };
-
- ssi0_pins: ssi0 {
- pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
- <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
- <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
- <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
- };
-
- usb0_pins: usb0 {
- pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
- <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
- <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
- };
-
- usb1_pins: usb1 {
- pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
- <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
- };
-};
-
diff --git a/arch/arm/dts/rzg2l-smarc-som.dtsi b/arch/arm/dts/rzg2l-smarc-som.dtsi
deleted file mode 100644
index 547859c..0000000
--- a/arch/arm/dts/rzg2l-smarc-som.dtsi
+++ /dev/null
@@ -1,371 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
-#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
-
-/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
-#define EMMC 1
-
-/*
- * To enable uSD card on CN3,
- * SW1[2] should be at position 3/ON.
- * Disable eMMC by setting "#define EMMC 0" above.
- */
-#define SDHI (!EMMC)
-
-/ {
- aliases {
- ethernet0 = ð0;
- ethernet1 = ð1;
- };
-
- chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- };
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_1p1v: regulator-vdd-core {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.1V";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- states = <3300000 1>, <1800000 0>;
- regulator-boot-on;
- gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
- regulator-always-on;
- };
-
- /* 32.768kHz crystal */
- x2: x2-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-};
-
-&adc {
- pinctrl-0 = <&adc_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /delete-node/ channel@6;
- /delete-node/ channel@7;
-};
-
-ð0 {
- pinctrl-0 = <ð0_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
- status = "okay";
-
- phy0: ethernet-phy@7 {
- compatible = "ethernet-phy-id0022.1640",
- "ethernet-phy-ieee802.3-c22";
- reg = <7>;
- interrupt-parent = <&irqc>;
- interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
- rxc-skew-psec = <2400>;
- txc-skew-psec = <2400>;
- rxdv-skew-psec = <0>;
- txen-skew-psec = <0>;
- rxd0-skew-psec = <0>;
- rxd1-skew-psec = <0>;
- rxd2-skew-psec = <0>;
- rxd3-skew-psec = <0>;
- txd0-skew-psec = <0>;
- txd1-skew-psec = <0>;
- txd2-skew-psec = <0>;
- txd3-skew-psec = <0>;
- };
-};
-
-ð1 {
- pinctrl-0 = <ð1_pins>;
- pinctrl-names = "default";
- phy-handle = <&phy1>;
- phy-mode = "rgmii-id";
- status = "okay";
-
- phy1: ethernet-phy@7 {
- compatible = "ethernet-phy-id0022.1640",
- "ethernet-phy-ieee802.3-c22";
- reg = <7>;
- interrupt-parent = <&irqc>;
- interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
- rxc-skew-psec = <2400>;
- txc-skew-psec = <2400>;
- rxdv-skew-psec = <0>;
- txen-skew-psec = <0>;
- rxd0-skew-psec = <0>;
- rxd1-skew-psec = <0>;
- rxd2-skew-psec = <0>;
- rxd3-skew-psec = <0>;
- txd0-skew-psec = <0>;
- txd1-skew-psec = <0>;
- txd2-skew-psec = <0>;
- txd3-skew-psec = <0>;
- };
-};
-
-&extal_clk {
- clock-frequency = <24000000>;
-};
-
-&gpu {
- mali-supply = <®_1p1v>;
-};
-
-&i2c3 {
- raa215300: pmic@12 {
- compatible = "renesas,raa215300";
- reg = <0x12>, <0x6f>;
- reg-names = "main", "rtc";
-
- clocks = <&x2>;
- clock-names = "xin";
- };
-};
-
-&ostm1 {
- status = "okay";
-};
-
-&ostm2 {
- status = "okay";
-};
-
-&pinctrl {
- adc_pins: adc {
- pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
- };
-
- eth0_pins: eth0 {
- pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
- <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
- <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
- <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
- <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
- <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
- <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
- <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
- <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
- <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
- <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
- <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
- <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
- <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
- <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
- <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
- };
-
- eth1_pins: eth1 {
- pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
- <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
- <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
- <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
- <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
- <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
- <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
- <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
- <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
- <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
- <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
- <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
- <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
- <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
- <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
- <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
- };
-
- gpio-sd0-pwr-en-hog {
- gpio-hog;
- gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "gpio_sd0_pwr_en";
- };
-
- qspi0_pins: qspi0 {
- qspi0-data {
- pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
- power-source = <1800>;
- };
-
- qspi0-ctrl {
- pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
- power-source = <1800>;
- };
- };
-
- /*
- * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
- * The below switch logic can be used to select the device between
- * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
- * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
- * SW1[2] should be at position 3/ON to enable uSD card CN3
- */
- sd0-dev-sel-hog {
- gpio-hog;
- gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "sd0_dev_sel";
- };
-
- sdhi0_emmc_pins: sd0emmc {
- sd0_emmc_data {
- pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
- "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
- power-source = <1800>;
- };
-
- sd0_emmc_ctrl {
- pins = "SD0_CLK", "SD0_CMD";
- power-source = <1800>;
- };
-
- sd0_emmc_rst {
- pins = "SD0_RST#";
- power-source = <1800>;
- };
- };
-
- sdhi0_pins: sd0 {
- sd0_data {
- pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
- power-source = <3300>;
- };
-
- sd0_ctrl {
- pins = "SD0_CLK", "SD0_CMD";
- power-source = <3300>;
- };
-
- sd0_mux {
- pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
- };
- };
-
- sdhi0_pins_uhs: sd0_uhs {
- sd0_data_uhs {
- pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
- power-source = <1800>;
- };
-
- sd0_ctrl_uhs {
- pins = "SD0_CLK", "SD0_CMD";
- power-source = <1800>;
- };
-
- sd0_mux_uhs {
- pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
- };
- };
-};
-
-&sbc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 {
- compatible = "micron,mt25qu512a", "jedec,spi-nor";
- reg = <0>;
- m25p,fast-read;
- spi-max-frequency = <50000000>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- boot@0 {
- reg = <0x00000000 0x2000000>;
- read-only;
- };
- user@2000000 {
- reg = <0x2000000 0x2000000>;
- };
- };
- };
-};
-
-#if SDHI
-&sdhi0 {
- pinctrl-0 = <&sdhi0_pins>;
- pinctrl-1 = <&sdhi0_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <&vccq_sdhi0>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-#endif
-
-#if EMMC
-&sdhi0 {
- pinctrl-0 = <&sdhi0_emmc_pins>;
- pinctrl-1 = <&sdhi0_emmc_pins>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- fixed-emmc-driver-type = <1>;
- status = "okay";
-};
-#endif
-
-&wdt0 {
- status = "okay";
- timeout-sec = <60>;
-};
-
-&wdt1 {
- status = "okay";
- timeout-sec = <60>;
-};
diff --git a/arch/arm/dts/rzg2l-smarc.dtsi b/arch/arm/dts/rzg2l-smarc.dtsi
deleted file mode 100644
index 37807f1..0000000
--- a/arch/arm/dts/rzg2l-smarc.dtsi
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
-
-/ {
- aliases {
- serial1 = &scif2;
- i2c3 = &i2c3;
- };
-
- osc1: cec-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- hdmi-out {
- compatible = "hdmi-connector";
- type = "d";
-
- port {
- hdmi_con_out: endpoint {
- remote-endpoint = <&adv7535_out>;
- };
- };
- };
-};
-
-&cpu_dai {
- sound-dai = <&ssi0>;
-};
-
-&dsi {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_out: endpoint {
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&adv7535_in>;
- };
- };
- };
-};
-
-&i2c1 {
- adv7535: hdmi@3d {
- compatible = "adi,adv7535";
- reg = <0x3d>;
-
- interrupt-parent = <&pinctrl>;
- interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
- clocks = <&osc1>;
- clock-names = "cec";
- avdd-supply = <®_1p8v>;
- dvdd-supply = <®_1p8v>;
- pvdd-supply = <®_1p8v>;
- a2vdd-supply = <®_1p8v>;
- v3p3-supply = <®_3p3v>;
- v1p2-supply = <®_1p8v>;
-
- adi,dsi-lanes = <4>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7535_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7535_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
- };
- };
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
-
- status = "okay";
-
- wm8978: codec@1a {
- compatible = "wlf,wm8978";
- #sound-dai-cells = <0>;
- reg = <0x1a>;
- };
-
- versa3: clock-generator@68 {
- compatible = "renesas,5p35023";
- reg = <0x68>;
- #clock-cells = <1>;
- clocks = <&x1>;
-
- renesas,settings = [
- 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
- 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
- 80 b0 45 c4 95
- ];
-
- assigned-clocks = <&versa3 0>, <&versa3 1>,
- <&versa3 2>, <&versa3 3>,
- <&versa3 4>, <&versa3 5>;
- assigned-clock-rates = <24000000>, <11289600>,
- <11289600>, <12000000>,
- <25000000>, <12288000>;
- };
-};
-
-#if PMOD_MTU3
-&mtu3 {
- pinctrl-0 = <&mtu3_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-#if MTU3_COUNTER_Z_PHASE_SIGNAL
-/* SDHI cd pin is muxed with counter Z phase signal */
-&sdhi1 {
- status = "disabled";
-};
-#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
-
-&spi1 {
- status = "disabled";
-};
-#endif /* PMOD_MTU3 */
-
-/*
- * To enable SCIF2 (SER0) on PMOD1 (CN7)
- * SW1 should be at position 2->3 so that SER0_CTS# line is activated
- * SW2 should be at position 2->3 so that SER0_TX line is activated
- * SW3 should be at position 2->3 so that SER0_RX line is activated
- * SW4 should be at position 2->3 so that SER0_RTS# line is activated
- */
-#if PMOD1_SER0
-&scif2 {
- pinctrl-0 = <&scif2_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-};
-#endif
-
-&ssi0 {
- pinctrl-0 = <&ssi0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&vccq_sdhi1 {
- gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
-};
diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h
index 2abf28e..c0caf57 100644
--- a/arch/arm/include/asm/mach-imx/hab.h
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -132,13 +132,14 @@
HAB_TGT_ANY = 0x55,
};
-struct imx_sec_config_fuse_t {
+struct imx_fuse {
int bank;
int word;
};
#if defined(CONFIG_IMX_HAB)
-extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+extern struct imx_fuse const imx_sec_config_fuse;
+extern struct imx_fuse const imx_field_return_fuse;
#endif
/*Function prototype description*/
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 52f6c9b..dbf9ab4 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -171,7 +171,7 @@
return 3 & (el >> 2);
}
-static inline unsigned int get_sctlr(void)
+static inline unsigned long get_sctlr(void)
{
unsigned int el;
unsigned long val;
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 21d955b..011cca5 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -293,3 +293,5 @@
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
obj-$(CONFIG_IMX8_ROMAPI) += romapi.o
+
+obj-$(CONFIG_MX7)$(CONFIG_IMX8M) += snvs.o
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index a8107f4..6000923 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -26,6 +26,14 @@
#define IS_HAB_ENABLED_BIT \
(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
((is_soc_type(MXC_SOC_MX7) || is_soc_type(MXC_SOC_IMX8M)) ? 0x2000000 : 0x2))
+#define FIELD_RETURN_FUSE_MASK \
+ (is_imx8mp() ? 0xFFFFFFFF : 0x00000001)
+/*
+ * The fuse pattern for i.MX8M Plus is 0x28001401, but bit 2 is already set from factory.
+ * This means when field return is set, the fuse word value reads 0x28001405
+ */
+#define FIELD_RETURN_PATTERN \
+ (is_imx8mp() ? 0x28001405 : 0x00000001)
#ifdef CONFIG_MX7ULP
#define HAB_M4_PERSISTENT_START ((soc_rev() >= CHIP_REV_2_0) ? 0x20008040 : \
@@ -870,18 +878,30 @@
bool imx_hab_is_enabled(void)
{
- struct imx_sec_config_fuse_t *fuse =
- (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
+ struct imx_fuse *sec_config =
+ (struct imx_fuse *)&imx_sec_config_fuse;
+ struct imx_fuse *field_return =
+ (struct imx_fuse *)&imx_field_return_fuse;
uint32_t reg;
+ bool is_enabled;
int ret;
- ret = fuse_read(fuse->bank, fuse->word, ®);
+ ret = fuse_read(sec_config->bank, sec_config->word, ®);
if (ret) {
- puts("\nSecure boot fuse read error\n");
+ puts("Secure boot fuse read error\n");
return ret;
}
+ is_enabled = reg & IS_HAB_ENABLED_BIT;
+ if (is_enabled) {
+ ret = fuse_read(field_return->bank, field_return->word, ®);
+ if (ret) {
+ puts("Field return fuse read error\n");
+ return ret;
+ }
+ is_enabled = (reg & FIELD_RETURN_FUSE_MASK) != FIELD_RETURN_PATTERN;
+ }
- return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
+ return is_enabled;
}
int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a72329e..9588b8b 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -34,13 +34,20 @@
#include <linux/bitfield.h>
#include <linux/sizes.h>
+#include "../snvs.h"
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_IMX_HAB)
-struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+struct imx_fuse const imx_sec_config_fuse = {
.bank = 1,
.word = 3,
};
+
+struct imx_fuse const imx_field_return_fuse = {
+ .bank = 8,
+ .word = 3,
+};
#endif
int timer_init(void)
@@ -571,6 +578,8 @@
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
+
+ init_snvs();
}
static void imx8m_setup_csu_tzasc(void)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7c28fa3..21e0e7d 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -42,12 +42,18 @@
struct rom_api *g_rom_api = (struct rom_api *)0x1980;
-#ifdef CONFIG_ENV_IS_IN_MMC
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
__weak int board_mmc_get_env_dev(int devno)
{
return devno;
}
+#ifdef CONFIG_SYS_MMC_ENV_DEV
+#define IMX9_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_DEV
+#else
+#define IMX9_MMC_ENV_DEV 0
+#endif
+
int mmc_get_env_dev(void)
{
int ret;
@@ -59,7 +65,7 @@
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
- return CONFIG_SYS_MMC_ENV_DEV;
+ return IMX9_MMC_ENV_DEV;
}
boot_type = boot >> 16;
@@ -69,7 +75,7 @@
/* If not boot from sd/mmc, use default value */
if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
- return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+ return env_get_ulong("mmcdev", 10, IMX9_MMC_ENV_DEV);
return board_mmc_get_env_dev(boot_instance);
}
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 9b40fe9..d4a6173 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -51,10 +51,15 @@
#endif
#if defined(CONFIG_IMX_HAB)
-struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+struct imx_fuse const imx_sec_config_fuse = {
.bank = 0,
.word = 6,
};
+
+struct imx_fuse const imx_field_return_fuse = {
+ .bank = 5,
+ .word = 6,
+};
#endif
u32 get_nr_cpus(void)
diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile
index f1436e2..fec228a 100644
--- a/arch/arm/mach-imx/mx7/Makefile
+++ b/arch/arm/mach-imx/mx7/Makefile
@@ -3,5 +3,5 @@
# (C) Copyright 2015 Freescale Semiconductor, Inc.
#
-obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o
+obj-y := soc.o clock.o clock_slice.o ddr.o
obj-$(CONFIG_ARMV7_PSCI) += psci-mx7.o psci-suspend.o
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 1b891a2..e504c1f 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -127,10 +127,15 @@
#endif
#if defined(CONFIG_IMX_HAB)
-struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+struct imx_fuse const imx_sec_config_fuse = {
.bank = 1,
.word = 3,
};
+
+struct imx_fuse const imx_field_return_fuse = {
+ .bank = 8,
+ .word = 3,
+};
#endif
static bool is_mx7d(void)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 980e022..61d331e 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -38,10 +38,15 @@
static char *get_reset_cause(char *);
#if defined(CONFIG_IMX_HAB)
-struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+struct imx_fuse const imx_sec_config_fuse = {
.bank = 29,
.word = 6,
};
+
+struct imx_fuse const imx_field_return_fuse = {
+ .bank = 9,
+ .word = 6,
+};
#endif
#define ROM_VERSION_ADDR 0x80
diff --git a/arch/arm/mach-imx/mx7/snvs.c b/arch/arm/mach-imx/snvs.c
similarity index 100%
rename from arch/arm/mach-imx/mx7/snvs.c
rename to arch/arm/mach-imx/snvs.c
diff --git a/arch/arm/mach-imx/snvs.h b/arch/arm/mach-imx/snvs.h
new file mode 100644
index 0000000..4ce9781
--- /dev/null
+++ b/arch/arm/mach-imx/snvs.h
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Linaro
+ */
+
+void init_snvs(void);
diff --git a/arch/arm/mach-renesas/include/mach/rzg2l.h b/arch/arm/mach-renesas/include/mach/rzg2l.h
index 057df5c..c49a71a 100644
--- a/arch/arm/mach-renesas/include/mach/rzg2l.h
+++ b/arch/arm/mach-renesas/include/mach/rzg2l.h
@@ -8,6 +8,6 @@
#define __ASM_ARCH_RZG2L_H
#define GICD_BASE 0x11900000
-#define GICR_BASE 0x11960000
+#define GICR_BASE 0x11940000
#endif /* __ASM_ARCH_RZG2L_H */
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index edccb2a..0c28241 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -169,15 +169,36 @@
}
#endif
-#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
+#if defined(CONFIG_TPL_BUILD)
static void rk3399_force_power_on_reset(void)
{
+ const struct rockchip_cru *cru = rockchip_get_cru();
ofnode node;
struct gpio_desc sysreset_gpio;
- if (!IS_ENABLED(CONFIG_SPL_GPIO)) {
+ /*
+ * The RK3399 resets only 'almost all logic' (see also in the
+ * TRM "3.9.4 Global software reset"), when issuing a software
+ * reset. This may cause issues during boot-up for some
+ * configurations of the application software stack.
+ *
+ * To work around this, we test whether the last reset reason
+ * was a power-on reset and (if not) issue an overtemp-reset to
+ * reset the entire module.
+ *
+ * While this was previously fixed by modifying the various
+ * places that could generate a software reset (e.g. U-Boot's
+ * sysreset driver, the ATF or Linux), we now have it here to
+ * ensure that we no longer have to track this through the
+ * various components.
+ */
+ if (cru->glb_rst_st == 0)
+ return;
+
+ if (!IS_ENABLED(CONFIG_TPL_GPIO)) {
debug("%s: trying to force a power-on reset but no GPIO "
- "support in SPL!\n", __func__);
+ "support in TPL!\n", __func__);
return;
}
@@ -198,6 +219,11 @@
dm_gpio_set_value(&sysreset_gpio, 1);
}
+void tpl_board_init(void)
+{
+ rk3399_force_power_on_reset();
+}
+# else
void __weak led_setup(void)
{
}
@@ -205,28 +231,6 @@
void spl_board_init(void)
{
led_setup();
-
- if (IS_ENABLED(CONFIG_SPL_GPIO)) {
- struct rockchip_cru *cru = rockchip_get_cru();
-
- /*
- * The RK3399 resets only 'almost all logic' (see also in the
- * TRM "3.9.4 Global software reset"), when issuing a software
- * reset. This may cause issues during boot-up for some
- * configurations of the application software stack.
- *
- * To work around this, we test whether the last reset reason
- * was a power-on reset and (if not) issue an overtemp-reset to
- * reset the entire module.
- *
- * While this was previously fixed by modifying the various
- * places that could generate a software reset (e.g. U-Boot's
- * sysreset driver, the ATF or Linux), we now have it here to
- * ensure that we no longer have to track this through the
- * various components.
- */
- if (cru->glb_rst_st != 0)
- rk3399_force_power_on_reset();
- }
}
#endif
+#endif
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index e646f71..ce327ed 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -32,6 +32,19 @@
help
Powkiddy X55 handheld gaming console with an RK3566 SoC.
+config TARGET_QNAP_TS433_RK3568
+ bool "QNAP-TS433"
+ help
+ Qnap TS433 4-bay NAS with a RK3568 SoC.
+
+ It provides the following featureset:
+ * 4GB LPDDR4
+ * 4GB eMMC
+ * 2 SATA ports connected to two RK3568's SATA controllers
+ * 2 SATA ports connected to a JMicron JMB58x AHCI SATA controller
+ * 1 1G network controller
+ * 1 2.5G Realtek RTL8125 network controller
+
config TARGET_QUARTZ64_RK3566
bool "Pine64 Quartz64"
help
@@ -70,6 +83,7 @@
source "board/hardkernel/odroid_m1s/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
source "board/powkiddy/x55/Kconfig"
+source "board/qnap/ts433/Kconfig"
source "board/radxa/zero3-rk3566/Kconfig"
source "board/xunlong/orangepi-3b-rk3566/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 6f28a31..b5a0e62 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -29,6 +29,24 @@
- 3.5mm Headphone out, 2.0mm PH-2A Mic in
- 5V Fan connector, PWM beeper, IR receiver, RTC battery connector
+config TARGET_GENBOOK_CM5_RK3588
+ bool "Cool Pi CM5 GenBook"
+ select BOARD_LATE_INIT
+ help
+ GeenBook is a notebook based on Rockchip RK3588, and works as a carrier
+ board connect with CM5 SOM.
+
+ Specification:
+ - Rockchip RK3588
+ - LPDDR5X 8/32 GB
+ - eMMC 64 GB
+ - HDMI Type A out x 1
+ - USB 3.0 Host x 1
+ - USB-C 3.0 with DisplayPort AltMode
+ - PCIE M.2 E Key for RTL8852BE Wireless connection
+ - PCIE M.2 M Key for NVME connection
+ - eDP panel with 1920x1080
+
config TARGET_JAGUAR_RK3588
bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)"
select BOARD_LATE_INIT
@@ -367,6 +385,7 @@
default 0x00a00000
source "board/armsom/sige7-rk3588/Kconfig"
+source "board/coolpi/genbook_cm5_rk3588/Kconfig"
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/cm3588-nas-rk3588/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index bbb9329..6b880f1 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -21,6 +21,10 @@
#include <timestamp.h>
#endif
+__weak void tpl_board_init(void)
+{
+}
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
@@ -54,6 +58,8 @@
if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER))
timer_init();
+ tpl_board_init();
+
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index bf32ead..de35658 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -10,6 +10,7 @@
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
+dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
include $(srctree)/scripts/Makefile.dts
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
new file mode 100644
index 0000000..4d65d33
--- /dev/null
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for AMD MicroBlaze V
+ *
+ * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "AMD MicroBlaze V 64bit";
+ compatible = "qemu,mbv", "amd,mbv";
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <100000000>;
+ cpu_0: cpu@0 {
+ compatible = "amd,mbv64", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa = "rv64imafdc";
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ clock-frequency = <100000000>;
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+
+ clk100: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ axi: axi {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ bootph-all;
+
+ axi_intc: interrupt-controller@41200000 {
+ compatible = "xlnx,xps-intc-1.00.a";
+ reg = <0 0x41200000 0 0x1000>;
+ interrupt-controller;
+ interrupt-parent = <&cpu0_intc>;
+ #interrupt-cells = <2>;
+ kind-of-intr = <0>;
+ };
+
+ xlnx_timer0: timer@41c00000 {
+ compatible = "xlnx,xps-timer-1.00.a";
+ reg = <0 0x41c00000 0 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <0 2>;
+ bootph-all;
+ xlnx,one-timer-only = <0>;
+ clock-names = "s_axi_aclk";
+ clocks = <&clk100>;
+ };
+
+ uart0: serial@40600000 {
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ reg = <0 0x40600000 0 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <1 2>;
+ bootph-all;
+ clocks = <&clk100>;
+ current-speed = <115200>;
+ xlnx,data-bits = <8>;
+ xlnx,use-parity = <0>;
+ };
+ };
+};
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 81752ed..2940768 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -449,6 +449,16 @@
gd->ram_size = state->ram_size;
}
+static int sandbox_cmdline_cb_native(struct sandbox_state *state,
+ const char *arg)
+{
+ state->native = true;
+
+ return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(native, 'N', 0,
+ "Use native mode (host-based EFI boot filename)");
+
void state_show(struct sandbox_state *state)
{
char **p;
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 3017b33..dee2801 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1515,7 +1515,7 @@
flash-stick@1 {
reg = <1>;
compatible = "sandbox,usb-flash";
- sandbox,filepath = "testflash1.bin";
+ sandbox,filepath = "flash1.img";
};
flash-stick@2 {
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index e7dc017..dc21a62 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -101,6 +101,7 @@
bool disable_eth; /* Disable Ethernet devices */
bool disable_sf_bootdevs; /* Don't bind SPI flash bootdevs */
bool upl; /* Enable Universal Payload (UPL) */
+ bool native; /* Adjust to reflect host arch */
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
diff --git a/board/coolpi/genbook_cm5_rk3588/Kconfig b/board/coolpi/genbook_cm5_rk3588/Kconfig
new file mode 100644
index 0000000..67086ea
--- /dev/null
+++ b/board/coolpi/genbook_cm5_rk3588/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GENBOOK_CM5_RK3588
+
+config SYS_BOARD
+ default "genbook_cm5_rk3588"
+
+config SYS_VENDOR
+ default "coolpi"
+
+config SYS_CONFIG_NAME
+ default "genbook-cm5-rk3588"
+
+endif
diff --git a/board/coolpi/genbook_cm5_rk3588/MAINTAINERS b/board/coolpi/genbook_cm5_rk3588/MAINTAINERS
new file mode 100644
index 0000000..0496cc9
--- /dev/null
+++ b/board/coolpi/genbook_cm5_rk3588/MAINTAINERS
@@ -0,0 +1,7 @@
+GENBOOK-CM5-RK3588
+M: Andy Yan <andyshrk@163.com>
+S: Maintained
+F: board/coolpi/genbook-cm5-rk3588
+F: include/configs/genbook-cm5-rk3588.h
+F: configs/coolpi-cm5-genbook-rk3588_defconfig
+F: arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi
diff --git a/board/coreboot/coreboot/sysinfo.c b/board/coreboot/coreboot/sysinfo.c
index e0bdc7a..d6b1953 100644
--- a/board/coreboot/coreboot/sysinfo.c
+++ b/board/coreboot/coreboot/sysinfo.c
@@ -24,21 +24,21 @@
const char *str = NULL;
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
if (priv->t1)
str = smbios_string(priv->system,
priv->t1->product_name);
break;
- case SYSINFO_ID_BOARD_MANUFACTURER:
+ case SYSID_BOARD_MANUFACTURER:
if (priv->t1)
str = smbios_string(priv->system,
priv->t1->manufacturer);
break;
- case SYSINFO_ID_PRIOR_STAGE_VERSION:
+ case SYSID_PRIOR_STAGE_VERSION:
if (priv->t0)
str = smbios_string(priv->bios, priv->t0->bios_ver);
break;
- case SYSINFO_ID_PRIOR_STAGE_DATE:
+ case SYSID_PRIOR_STAGE_DATE:
if (priv->t0)
str = smbios_string(priv->bios,
priv->t0->bios_release_date);
diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c
index 341831a..c9171df 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -58,7 +58,7 @@
int board_late_init(void)
{
-#ifdef CONFIG_ENV_IS_IN_MMC
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
board_late_mmc_env_init();
#endif
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 3443dc9..db96534 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -151,8 +151,8 @@
return -ENOSYS;
switch (id) {
- case SYSINFO_ID_SMBIOS_SYSTEM_VERSION:
- case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: {
+ case SYSID_SM_SYSTEM_VERSION:
+ case SYSID_SM_BASEBOARD_VERSION: {
ret = get_skuconfig(dev);
if (ret < 0)
@@ -162,7 +162,7 @@
sprintf(val, "rev%d", ret);
break;
}
- case SYSINFO_ID_BOARD_MODEL: {
+ case SYSID_BOARD_MODEL: {
int mem_config, sku_config;
const char *model;
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c
index 0966e25..8b635ef 100644
--- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -96,15 +96,15 @@
int board_fit_config_name_match(const char *name)
{
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
- !strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
+ !strcmp(name, "r8a774a1-hihope-rzg2m-ex"))
return 0;
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") &&
- !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
+ !strcmp(name, "r8a774b1-hihope-rzg2n-ex"))
return 0;
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") &&
- !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
+ !strcmp(name, "r8a774e1-hihope-rzg2h-ex"))
return 0;
return -1;
diff --git a/board/qnap/ts433/Kconfig b/board/qnap/ts433/Kconfig
new file mode 100644
index 0000000..b00e1f9
--- /dev/null
+++ b/board/qnap/ts433/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_QNAP_TS433_RK3568
+
+config SYS_BOARD
+ default "qnap_ts433"
+
+config SYS_VENDOR
+ default "qnap"
+
+config SYS_CONFIG_NAME
+ default "qnap_ts433"
+
+endif
diff --git a/board/qnap/ts433/MAINTAINERS b/board/qnap/ts433/MAINTAINERS
new file mode 100644
index 0000000..c2b31ad
--- /dev/null
+++ b/board/qnap/ts433/MAINTAINERS
@@ -0,0 +1,8 @@
+QNAP-TS433
+M: Heiko Stuebner <heiko@sntech.de>
+S: Maintained
+F: board/qnap/ts433/
+F: doc/board/qnap/
+F: include/configs/qnap_ts433.h
+F: configs/qnap-ts433-rk3568_defconfig
+F: arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi
diff --git a/board/renesas/rzg2l/MAINTAINERS b/board/renesas/rzg2l/MAINTAINERS
index 0a51391..0e656e2 100644
--- a/board/renesas/rzg2l/MAINTAINERS
+++ b/board/renesas/rzg2l/MAINTAINERS
@@ -1,6 +1,6 @@
RENESAS RZG2L BOARD FAMILY
M: Paul Barker <paul.barker.ct@bp.renesas.com>
S: Supported
-F: arch/arm/dts/rz-smarc-common.dtsi
+N: rz-smarc
N: rzg2l
N: r9a07g044
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
index 8f619e5..5f81be5 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -28,6 +28,12 @@
F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
F: arch/arm/dts/rk3328-nanopi-r2s.dts
+NANOPI-R2S-PLUS-RK3328
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/nanopi-r2s-plus-rk3328_defconfig
+F: arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi
+
ORANGEPI-R1-PLUS-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index a6b45cd..3badeeb 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -193,7 +193,7 @@
int ret = -ENOTSUPP;
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
snprintf(val, size,
"Toradex %04d %s %s",
tdx_hw_tag.prodid,
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index c7df4ab..0ff8440 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -45,7 +45,7 @@
default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default 0x8000 if MICROBLAZE
default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
- default 0x23000000 if TARGET_XILINX_MBV
+ default 0x83000000 if TARGET_XILINX_MBV
depends on OF_BOARD || OF_SEPARATE
help
Offset in the memory where the board configuration DTB is placed.
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index 2ad6d3b..f836aa6 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -13,7 +13,7 @@
#include <bootmeth.h>
#include <command.h>
#include <dm.h>
-#include <efi_default_filename.h>
+#include <efi.h>
#include <efi_loader.h>
#include <fs.h>
#include <malloc.h>
@@ -25,32 +25,11 @@
#define EFI_DIRNAME "/EFI/BOOT/"
-static int get_efi_pxe_arch(void)
-{
- /* http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml */
- if (IS_ENABLED(CONFIG_ARM64))
- return 0xb;
- else if (IS_ENABLED(CONFIG_ARM))
- return 0xa;
- else if (IS_ENABLED(CONFIG_X86_64))
- return 0x6;
- else if (IS_ENABLED(CONFIG_X86))
- return 0x7;
- else if (IS_ENABLED(CONFIG_ARCH_RV32I))
- return 0x19;
- else if (IS_ENABLED(CONFIG_ARCH_RV64I))
- return 0x1b;
- else if (IS_ENABLED(CONFIG_SANDBOX))
- return 0; /* not used */
-
- return -EINVAL;
-}
-
static int get_efi_pxe_vci(char *str, int max_len)
{
int ret;
- ret = get_efi_pxe_arch();
+ ret = efi_get_pxe_arch();
if (ret < 0)
return ret;
@@ -168,7 +147,7 @@
}
strcpy(fname, EFI_DIRNAME);
- strcat(fname, BOOTEFI_NAME);
+ strcat(fname, efi_get_basename());
if (bflow->blk)
desc = dev_get_uclass_plat(bflow->blk);
@@ -239,7 +218,7 @@
ret = get_efi_pxe_vci(str, sizeof(str));
if (ret)
return log_msg_ret("vci", ret);
- ret = get_efi_pxe_arch();
+ ret = efi_get_pxe_arch();
if (ret < 0)
return log_msg_ret("arc", ret);
arch = ret;
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 6368336..8f3ad94 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2115,11 +2115,8 @@
config CMD_WGET
bool "wget"
- depends on CMD_NET
default y if SANDBOX
- select PROT_TCP if NET
- select PROT_TCP_LWIP if NET_LWIP
- select PROT_DNS_LWIP if NET_LWIP
+ select WGET
help
wget is a simple command to download kernel, or other files,
from a http server over TCP.
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 4c0e2ad..ae9e192 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -140,10 +140,6 @@
#endif
bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params);
print_bi_dram(bd);
- if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
- bdinfo_print_num_l("sramstart", (ulong)bd->bi_sramstart);
- bdinfo_print_num_l("sramsize", (ulong)bd->bi_sramsize);
- }
bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart);
bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize);
bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset);
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index e040fe7..02f1e08 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -511,6 +511,27 @@
return CMD_RET_SUCCESS;
}
+/**
+ * do_efi_show_defaults() - show UEFI default filename and PXE architecture
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "defaults" sub-command.
+ * Shows the default EFI filename and PXE architecture
+ */
+static int do_efi_show_defaults(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ printf("Default boot path: EFI\\BOOT\\%s\n", efi_get_basename());
+ printf("PXE arch: 0x%02x\n", efi_get_pxe_arch());
+
+ return CMD_RET_SUCCESS;
+}
+
static const char * const efi_mem_type_string[] = {
[EFI_RESERVED_MEMORY_TYPE] = "RESERVED",
[EFI_LOADER_CODE] = "LOADER CODE",
@@ -1561,6 +1582,8 @@
"", ""),
U_BOOT_CMD_MKENT(dh, CONFIG_SYS_MAXARGS, 1, do_efi_show_handles,
"", ""),
+ U_BOOT_CMD_MKENT(defaults, CONFIG_SYS_MAXARGS, 1, do_efi_show_defaults,
+ "", ""),
U_BOOT_CMD_MKENT(images, CONFIG_SYS_MAXARGS, 1, do_efi_show_images,
"", ""),
U_BOOT_CMD_MKENT(memmap, CONFIG_SYS_MAXARGS, 1, do_efi_show_memmap,
@@ -1653,6 +1676,8 @@
" - show UEFI drivers\n"
"efidebug dh\n"
" - show UEFI handles\n"
+ "efidebug defaults\n"
+ " - show default EFI filename and PXE architecture\n"
"efidebug images\n"
" - show loaded images\n"
"efidebug memmap\n"
diff --git a/cmd/net.c b/cmd/net.c
index c90578e..79525f7 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -196,6 +196,8 @@
#if defined(CONFIG_CMD_WGET)
static int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
+ wget_info = &default_wget_info;
+
return netboot_common(WGET, cmdtp, argc, argv);
}
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 392f90f..1f25980 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -523,6 +523,9 @@
case 'f': /* force */
env_flag |= H_FORCE;
break;
+ case 'k':
+ env_flag |= H_NOCLEAR;
+ break;
default:
return cmd_usage(cmdtp);
}
@@ -1133,8 +1136,9 @@
#if defined(CONFIG_CMD_ENV_CALLBACK)
"callbacks - print callbacks and their associated variables\nenv "
#endif
- "default [-f] -a - [forcibly] reset default environment\n"
- "env default [-f] var [...] - [forcibly] reset variable(s) to their default values\n"
+ "default [-k] [-f] -a - [forcibly] reset default environment\n"
+ "env default [-k] [-f] var [...] - [forcibly] reset variable(s) to their default values\n"
+ " \"-k\": keep variables not defined in default environment\n"
"env delete [-f] var [...] - [forcibly] delete variable(s)\n"
#if defined(CONFIG_CMD_EDITENV)
"env edit name - edit environment variable\n"
diff --git a/common/board_f.c b/common/board_f.c
index 98dc259..ebc934ab 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -637,13 +637,6 @@
int setup_bdinfo(void)
{
- struct bd_info *bd = gd->bd;
-
- if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
- }
-
return arch_setup_bdinfo();
}
diff --git a/common/board_info.c b/common/board_info.c
index 33c260b..dc26e1a 100644
--- a/common/board_info.c
+++ b/common/board_info.c
@@ -18,9 +18,9 @@
const char *name;
enum sysinfo_id id;
} to_show[] = {
- { "Manufacturer", SYSINFO_ID_BOARD_MANUFACTURER},
- { "Prior-stage version", SYSINFO_ID_PRIOR_STAGE_VERSION },
- { "Prior-stage date", SYSINFO_ID_PRIOR_STAGE_DATE },
+ { "Manufacturer", SYSID_BOARD_MANUFACTURER},
+ { "Prior-stage version", SYSID_PRIOR_STAGE_VERSION },
+ { "Prior-stage date", SYSID_PRIOR_STAGE_DATE },
{ /* sentinel */ }
};
@@ -39,7 +39,7 @@
if (ret)
return ret;
- ret = sysinfo_get_str(dev, SYSINFO_ID_BOARD_MODEL, sizeof(str), str);
+ ret = sysinfo_get_str(dev, SYSID_BOARD_MODEL, sizeof(str), str);
if (ret)
return ret;
printf("Model: %s\n", str);
diff --git a/common/console.c b/common/console.c
index 2222470..863ac6a 100644
--- a/common/console.c
+++ b/common/console.c
@@ -745,11 +745,7 @@
}
if (IS_ENABLED(CONFIG_DEBUG_UART) && !(gd->flags & GD_FLG_SERIAL_READY)) {
- while (*s) {
- int ch = *s++;
-
- printch(ch);
- }
+ printascii(s);
return;
}
diff --git a/configs/coolpi-cm5-genbook-rk3588_defconfig b/configs/coolpi-cm5-genbook-rk3588_defconfig
new file mode 100644
index 0000000..3eb5dc9
--- /dev/null
+++ b/configs/coolpi-cm5-genbook-rk3588_defconfig
@@ -0,0 +1,101 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-coolpi-cm5-genbook"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_GENBOOK_CM5_RK3588=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-genbook.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+# CONFIG_CMD_BIND is not set
+# CONFIG_CMD_FASTBOOT is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 468ec38..43ac5a5 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -5,11 +5,12 @@
CONFIG_MX6QDL=y
CONFIG_TARGET_DHCOMIMX6=y
CONFIG_SPL_SYS_L2_PL310=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-dhcom-pdk2"
CONFIG_MX6_DDRCAL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02 imx6dl-dhcom-picoitx"
+CONFIG_OF_LIST="nxp/imx/imx6q-dhcom-pdk2 nxp/imx/imx6dl-dhcom-pdk2 nxp/imx/imx6s-dhcom-drc02 nxp/imx/imx6dl-dhcom-picoitx"
+CONFIG_OF_UPSTREAM=y
CONFIG_FIT_VERBOSE=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_LTO=y
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 1d06f34..f79f0e8 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -22,7 +22,6 @@
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@@ -31,6 +30,7 @@
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index ebe883e..51e31dc 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -18,13 +18,13 @@
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
CONFIG_CMD_MMC=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index 6266f3c..c9753e1 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -8,23 +8,23 @@
CONFIG_TEXT_BASE=0x50000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
-CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m"
+CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m-ex"
CONFIG_TARGET_HIHOPE_RZG2=y
# CONFIG_SPL is not set
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m.dtb; booti 0x48080000 - 0x48000000"
-CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
+CONFIG_BOOTCOMMAND="tftp 0x48080000 Image; tftp 0x48000000 Image-r8a774a1-hihope-rzg2m-ex.dtb; booti 0x48080000 - 0x48000000"
+CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m-ex.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
-CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m renesas/r8a774b1-hihope-rzg2n renesas/r8a774e1-hihope-rzg2h"
+CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m-ex renesas/r8a774b1-hihope-rzg2n-ex renesas/r8a774e1-hihope-rzg2h-ex"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_ENV_DEV=0
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_GPIO_HOG=y
CONFIG_DM_PCA953X=y
diff --git a/configs/nanopi-r2s-plus-rk3328_defconfig b/configs/nanopi-r2s-plus-rk3328_defconfig
new file mode 100644
index 0000000..6e6785f
--- /dev/null
+++ b/configs/nanopi-r2s-plus-rk3328_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2s-plus"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s-plus.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSINFO=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 67c0ee7..7a180b1 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -30,6 +30,7 @@
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
+CONFIG_TPL_GPIO=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
@@ -78,6 +79,8 @@
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_TPL_PINCTRL=y
+CONFIG_TPL_PINCTRL_FULL=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
diff --git a/configs/qnap-ts433-rk3568_defconfig b/configs/qnap-ts433-rk3568_defconfig
new file mode 100644
index 0000000..840da7f
--- /dev/null
+++ b/configs/qnap-ts433-rk3568_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-qnap-ts433"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_QNAP_TS433_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-qnap-ts433.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_FAN53555=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index c350892..11e1332 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -55,6 +55,9 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index 741724f..820681d 100644
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -2,13 +2,13 @@
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
-CONFIG_SPL_STACK=0x20200000
-CONFIG_SPL_BSS_START_ADDR=0x24000000
+CONFIG_SPL_STACK=0x80200000
+CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
-CONFIG_SYS_LOAD_ADDR=0x20200000
+CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
@@ -16,12 +16,12 @@
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_TARGET_XILINX_MBV=y
-CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
CONFIG_RISCV_SMODE=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig
new file mode 100644
index 0000000..aad9c3f
--- /dev/null
+++ b/configs/xilinx_mbv64_defconfig
@@ -0,0 +1,44 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0xe00000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
+CONFIG_SPL_STACK=0x80200000
+CONFIG_SPL_BSS_START_ADDR=0x84000000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0x40600000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SYS_CLK_FREQ=100000000
+CONFIG_BOOT_SCRIPT_OFFSET=0x0
+CONFIG_DEBUG_UART=y
+CONFIG_TARGET_XILINX_MBV=y
+CONFIG_ARCH_RV64I=y
+# CONFIG_SPL_SMP is not set
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_BOARD_LATE_INIT is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_TIMER=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_MTD=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_XILINX_UARTLITE=y
+CONFIG_XILINX_TIMER=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_PANIC_HANG=y
+CONFIG_SPL_GZIP=y
diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig
new file mode 100644
index 0000000..628e0ed
--- /dev/null
+++ b/configs/xilinx_mbv64_smode_defconfig
@@ -0,0 +1,48 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0xe00000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
+CONFIG_SPL_STACK=0x80200000
+CONFIG_SPL_BSS_START_ADDR=0x84000000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0x40600000
+CONFIG_DEBUG_UART_CLOCK=1000000
+CONFIG_SYS_CLK_FREQ=100000000
+CONFIG_BOOT_SCRIPT_OFFSET=0x0
+CONFIG_TARGET_XILINX_MBV=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+# CONFIG_SPL_SMP is not set
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_BOARD_LATE_INIT is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_TIMER=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_MTD=y
+CONFIG_DEBUG_UART_UARTLITE=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_XILINX_UARTLITE=y
+# CONFIG_RISCV_TIMER is not set
+CONFIG_XILINX_TIMER=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_PANIC_HANG=y
+CONFIG_SPL_GZIP=y
diff --git a/doc/board/coolpi/genbook_cm5_rk3588.rst b/doc/board/coolpi/genbook_cm5_rk3588.rst
new file mode 100644
index 0000000..a02e561
--- /dev/null
+++ b/doc/board/coolpi/genbook_cm5_rk3588.rst
@@ -0,0 +1,68 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+GenBook
+=======
+Cool Pi GenBook is a laptop powered by RK3588, it works with a
+carrier board connect with CM5.
+
+Specification:
+* Rockchip RK3588
+* LPDDR5X 8/32 GB
+* eMMC 64 GB
+* SPI Nor 8 MB
+* HDMI Type A out x 1
+* USB 3.0 Host x 1
+* USB-C 3.0 with DisplayPort AltMode
+* PCIE M.2 E Key for RTL8852BE Wireless connection
+* PCIE M.2 M Key for NVME connection
+* eDP panel with 1920x1080
+
+Here is the step-by-step to compile and boot to U-Boot on GenBook.
+
+Get the TF-A and DDR init (TPL) binaries
+----------------------------------------
+
+.. prompt:: bash
+
+ > cd u-boot
+ > export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin
+ > export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf
+ > make coolpi-genbook-cm5-rk3588_defconfig
+ > make CROSS_COMPILE=aarch64-linux-gnu-
+
+This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor.
+
+Write u-boot to eMMC or SPI Nor from a Linux system on the laptop
+-----------------------------------------------------------------
+
+Copy ``u-boot-rockchip.bin`` and ``u-boot-rockchip-spi.bin`` to the laptop.
+
+eMMC
+~~~~
+
+.. prompt:: bash
+
+ dd if=u-boot-rockchip.bin of=/dev/mmcblk0 bs=512 seek=64
+
+SPI Nor
+~~~~~~~
+
+.. prompt:: bash
+
+ dd if=u-boot-rockchip-spi.bin of=/dev/mtdblock0
+
+``upgrade_tool`` allows to flash the on-board SPI Nor via the USB TypeC interface
+with help of the Rockchip loader binary.
+
+To enter the USB flashing mode, connect the laptop and your HOST PC with a USB-C
+cable, reset the laptop with ``Loader Key`` pressed.
+On your PC, check with ``lsusb -d 2207:350b``).
+
+To flash U-Boot on the SPI Nor with ``upgrade_tool``:
+
+.. prompt:: bash
+
+ upgrade_tool db rk3588/MiniLoaderAll.bin
+ upgrade_tool ssd // Input 5 for SPINOR download mode
+ upgrade_tool wl 0 u-boot-rockchip-spi.bin
+ upgrade_tool rd
diff --git a/doc/board/coolpi/index.rst b/doc/board/coolpi/index.rst
new file mode 100644
index 0000000..9c9593f
--- /dev/null
+++ b/doc/board/coolpi/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Cool Pi
+=================
+
+.. toctree::
+ :maxdepth: 2
+
+ genbook_cm5_rk3588
diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst
index 8a5eb1e..8388e13 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -171,3 +171,8 @@
CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_BASE=0x10000000
CONFIG_DEBUG_UART_CLOCK=3686400
+
+To provide a debug UART in main U-Boot the SBI DBCN extension can be used
+instead::
+
+ CONFIG_DEBUG_SBI_CONSOLE=y
diff --git a/doc/board/index.rst b/doc/board/index.rst
index ca5246e..b54c174 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -23,6 +23,7 @@
bsh/index
cloos/index
congatec/index
+ coolpi/index
coreboot/index
emcraft/index
emulation/index
@@ -43,6 +44,7 @@
phytec/index
purism/index
qualcomm/index
+ qnap/index
renesas/index
rockchip/index
samsung/index
diff --git a/doc/board/qnap/index.rst b/doc/board/qnap/index.rst
new file mode 100644
index 0000000..652ea11
--- /dev/null
+++ b/doc/board/qnap/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Qnap
+====
+
+.. toctree::
+ :maxdepth: 2
+
+ ts433.rst
diff --git a/doc/board/qnap/ts433.rst b/doc/board/qnap/ts433.rst
new file mode 100644
index 0000000..1e1bfbb
--- /dev/null
+++ b/doc/board/qnap/ts433.rst
@@ -0,0 +1,91 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Qnap TS433 Devices
+=================================
+
+This allows U-Boot to boot the Qnap TS433 NAS
+
+Preparing the serial
+--------------------
+
+Qnap devices run their serial console with a 115200 baudrate. As the
+binary DDR-init and maskrom-downloader expect a 1500000 rate, it is
+necessary to adapt the binaries if their output is needed.
+
+This can be done with a binary provided in the rkbin repository.
+First the ddrbin_param.txt in the rkbin repo needs to be modified:
+
+.. code-block:: bash
+
+ diff --git a/tools/ddrbin_param.txt b/tools/ddrbin_param.txt
+ index 0dfdd318..82ade7e7 100644
+ --- a/tools/ddrbin_param.txt
+ +++ b/tools/ddrbin_param.txt
+ @@ -11,7 +11,7 @@ lp5_freq=
+
+ uart id=
+ uart iomux=
+ -uart baudrate=
+ +uart baudrate=115200
+
+ sr_idle=
+ pd_idle=
+
+And after that the ddrbin_tool binary can be used to modify apply this
+modification and also a new maskrom downloader can be build:
+
+.. code-block:: bash
+
+ $ tools/ddrbin_tool rk3568 tools/ddrbin_param.txt bin/rk35/rk3568_ddr_1560MHz_v1.21.bin
+ $ tools/boot_merger RKBOOT/RK3568MINIALL.ini
+
+Building U-Boot
+---------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf
+ $ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin
+ $ make qnap-ts433-rk3568_defconfig
+ $ make
+
+This will build ``u-boot-rockchip.bin`` which can be written to the
+on-board eMMC.
+
+Image installation
+------------------
+
+The Qnap thankfully provides an easily accessible serial header as well as
+a very user-friendly jumper-header to bring the device into maskrom mode.
+
+To access both, the drive trays need to be removed. Looking at the board,
+through the upper cutout of the metal frame the white 4-port serial-header
+can be seen next to a barcode sticker. It's pinout is as follows:
+
+.. code-block:: none
+
+ ,_ _.
+ |1234| 1=TX 2=VCC
+ `----' 3=RX 4=GND
+
+
+Directly below it, the mentioned 2-pin jumper header can be seen.
+
+To write your u-boot to the device, it needs to be powered off first. Then
+a jumper or suitable cable needs to be used to connect the two pins of the
+maskrom header. Turning on the device now will start it in maskrom mode.
+
+It is important that the jumper gets removed after that stop and before
+actually trying to write to the emmc.
+
+The front usb-port needs to be connected to the host with an USB-A-to-A
+cable to allow flashing.
+
+The flashing itself is done via rkdeveloptool, which can be found for
+example as package of that name in Debian-based distributions:
+
+.. code-block:: bash
+
+ $ rkdeveloptool db rk356x_spl_loader_v1.21.113.bin
+ $ rkdeveloptool wl 64 u-boot-rockchip.bin
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 7b11a2e..9bab86d 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -65,6 +65,7 @@
- FriendlyElec NanoPi R2C (nanopi-r2c-rk3328)
- FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328)
- FriendlyElec NanoPi R2S (nanopi-r2s-rk3328)
+ - FriendlyElec NanoPi R2S Plus (nanopi-r2s-plus-rk3328)
- Pine64 Rock64 (rock64-rk3328)
- Radxa ROCK Pi E (rock-pi-e-rk3328)
- Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328)
@@ -119,6 +120,7 @@
- FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
- Generic RK3566/RK3568 (generic-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
+ - QNAP TS-433 (qnap-ts433-rk3568)
- Radxa E25 Carrier Board (radxa-e25-rk3568)
- Radxa ROCK 3A (rock-3a-rk3568)
- Radxa ROCK 3B (rock-3b-rk3568)
@@ -147,6 +149,7 @@
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
- Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s)
- Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588)
+ - Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588)
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
diff --git a/doc/conf.py b/doc/conf.py
index ced3a67..c50daf8 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -560,13 +560,9 @@
# Grouping the document tree into PDF files. List of tuples
# (source start file, target name, title, author, options).
#
-# See the Sphinx chapter of https://ralsina.me/static/manual.pdf
-#
-# FIXME: Do not add the index file here; the result will be too big. Adding
-# multiple PDF files here actually tries to get the cross-referencing right
-# *between* PDF files.
+# See https://rst2pdf.org/static/manual.html#sphinx
pdf_documents = [
- ('uboot-documentation', u'U-Boot', u'U-Boot', u'J. Random Bozo'),
+ ('index', u'U-Boot', u'Das U-Boot', u'The U-Boot development community'),
]
# kernel-doc extension configuration for running Sphinx directly (e.g. by Read
diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst
index 211f7e4..0233945 100644
--- a/doc/develop/devicetree/control.rst
+++ b/doc/develop/devicetree/control.rst
@@ -89,7 +89,7 @@
Resyncing with devicetree-rebasing
----------------------------------
-The `devicetree-rebasing repository`_ maintains a fork cum mirror copy of
+The `devicetree-rebasing repository`_ maintains a mirror copy of
devicetree files along with the bindings synced at every Linux kernel major
release or intermediate release candidates. The U-Boot maintainers regularly
sync the `dts/upstream/` subtree from the devicetree-rebasing repo whenever
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index faec644..1548d26 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -51,11 +51,11 @@
Current Status
--------------
-* U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
+* U-Boot v2024.10 was released on Mon 07 October 2024.
* The Merge Window for the next release (v2025.01) is **closed**.
-* The next branch is now **closed**.
+* The next branch is now **open**.
* Release "v2025.01" is scheduled for 06 January 2025.
@@ -69,7 +69,7 @@
* U-Boot v2025.01-rc1 was released on Mon 28 October 2024.
-.. * U-Boot v2025.01-rc2 was released on Mon 11 November 2024.
+* U-Boot v2025.01-rc2 was released on Mon 11 November 2024.
.. * U-Boot v2025.01-rc3 was released on Mon 25 November 2024.
diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h
index 954cd88..739a17c 100644
--- a/drivers/bios_emulator/biosemui.h
+++ b/drivers/bios_emulator/biosemui.h
@@ -128,6 +128,7 @@
u32 finalVal;
} BE_portInfo;
+#if defined(X86EMU_RAW_IO)
#define PM_inpb(port) inb(port)
#define PM_inpw(port) inw(port)
#define PM_inpd(port) inl(port)
@@ -135,6 +136,46 @@
#define PM_outpw(port, val) outw(val, port)
#define PM_outpd(port, val) outl(val, port)
+#else
+
+/*
+ * Until the emulator code is fixed, at least print warnings.
+ */
+
+static inline u8 PM_inpb(u16 port)
+{
+ printf("x86 port 0x%x read attempt, returning 0\n", port);
+ return 0;
+}
+
+static inline u16 PM_inpw(u16 port)
+{
+ printf("x86 port 0x%x read attempt, returning 0\n", port);
+ return 0;
+}
+
+static inline u32 PM_inpd(u16 port)
+{
+ printf("x86 port 0x%x read attempt, returning 0\n", port);
+ return 0;
+}
+
+static inline void PM_outpb(u16 port, u8 val)
+{
+ printf("x86 port 0x%x write attempt, ignoring\n", port);
+}
+
+static inline void PM_outpw(u16 port, u16 val)
+{
+ printf("x86 port 0x%x write attempt, ignoring\n", port);
+}
+
+static inline void PM_outpd(u16 port, u32 val)
+{
+ printf("x86 port 0x%x write attempt, ignoring\n", port);
+}
+#endif
+
#define LOG_inpb(port) PM_inpb(port)
#define LOG_inpw(port) PM_inpw(port)
#define LOG_inpd(port) PM_inpd(port)
diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c
index b426dc3..c63cf3d 100644
--- a/drivers/bios_emulator/x86emu/debug.c
+++ b/drivers/bios_emulator/x86emu/debug.c
@@ -38,6 +38,8 @@
****************************************************************************/
#include <stdarg.h>
+#include <string.h>
+#include <vsprintf.h>
#include <linux/ctype.h>
#include <linux/printk.h>
#include "x86emu/x86emui.h"
diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig
index 3918b05..6cae16f 100644
--- a/drivers/button/Kconfig
+++ b/drivers/button/Kconfig
@@ -9,6 +9,17 @@
can provide access to board-specific buttons. Use of the device tree
for configuration is encouraged.
+config BUTTON_REMAP_PHONE_KEYS
+ bool "Remap phone keys for navigation"
+ depends on BUTTON
+ help
+ Enable remapping of phone keys to navigation keys. This is useful for
+ devices with phone keys that are not used in U-Boot. The phone keys
+ are remapped to the following navigation keys:
+ - Volume up: Up
+ - Volume down: Down
+ - Power: Enter
+
config BUTTON_ADC
bool "Button adc"
depends on BUTTON
diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c
index cda2433..729983d 100644
--- a/drivers/button/button-uclass.c
+++ b/drivers/button/button-uclass.c
@@ -10,6 +10,7 @@
#include <button.h>
#include <dm.h>
#include <dm/uclass-internal.h>
+#include <dt-bindings/input/linux-event-codes.h>
int button_get_by_label(const char *label, struct udevice **devp)
{
@@ -37,14 +38,33 @@
return ops->get_state(dev);
}
+static int button_remap_phone_keys(int code)
+{
+ switch (code) {
+ case KEY_VOLUMEUP:
+ return KEY_UP;
+ case KEY_VOLUMEDOWN:
+ return KEY_DOWN;
+ case KEY_POWER:
+ return KEY_ENTER;
+ default:
+ return code;
+ }
+}
+
int button_get_code(struct udevice *dev)
{
struct button_ops *ops = button_get_ops(dev);
+ int code;
if (!ops->get_code)
return -ENOSYS;
- return ops->get_code(dev);
+ code = ops->get_code(dev);
+ if (CONFIG_IS_ENABLED(BUTTON_REMAP_PHONE_KEYS))
+ return button_remap_phone_keys(code);
+ else
+ return code;
}
UCLASS_DRIVER(button) = {
diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c
index cc00b80..2ff5ca7 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -14,8 +14,17 @@
#define SIFIVE_CCACHE_WAY_ENABLE 0x008
+#define SIFIVE_CCACHE_TRUNKCLOCKGATE 0x1000
+#define SIFIVE_CCACHE_TRUNKCLOCKGATE_DISABLE BIT(0)
+#define SIFIVE_CCACHE_REGIONCLOCKGATE_DISABLE BIT(1)
+
struct sifive_ccache {
void __iomem *base;
+ bool has_cg;
+};
+
+struct sifive_ccache_quirks {
+ bool has_cg;
};
static int sifive_ccache_enable(struct udevice *dev)
@@ -30,6 +39,14 @@
writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+ if (priv->has_cg) {
+ /* enable clock gating bits */
+ config = readl(priv->base + SIFIVE_CCACHE_TRUNKCLOCKGATE);
+ config &= ~(SIFIVE_CCACHE_TRUNKCLOCKGATE_DISABLE |
+ SIFIVE_CCACHE_REGIONCLOCKGATE_DISABLE);
+ writel(config, priv->base + SIFIVE_CCACHE_TRUNKCLOCKGATE);
+ }
+
return 0;
}
@@ -50,7 +67,9 @@
static int sifive_ccache_probe(struct udevice *dev)
{
struct sifive_ccache *priv = dev_get_priv(dev);
+ const struct sifive_ccache_quirks *quirk = (void *)dev_get_driver_data(dev);
+ priv->has_cg = quirk->has_cg;
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;
@@ -58,10 +77,18 @@
return 0;
}
+static const struct sifive_ccache_quirks fu540_ccache = {
+ .has_cg = false,
+};
+
+static const struct sifive_ccache_quirks ccache0 = {
+ .has_cg = true,
+};
+
static const struct udevice_id sifive_ccache_ids[] = {
- { .compatible = "sifive,fu540-c000-ccache" },
- { .compatible = "sifive,fu740-c000-ccache" },
- { .compatible = "sifive,ccache0" },
+ { .compatible = "sifive,fu540-c000-ccache", .data = (ulong)&fu540_ccache },
+ { .compatible = "sifive,fu740-c000-ccache", .data = (ulong)&fu540_ccache },
+ { .compatible = "sifive,ccache0", .data = (ulong)&ccache0 },
{}
};
diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c
index 611ac7c..3e9e7819 100644
--- a/drivers/iommu/apple_dart.c
+++ b/drivers/iommu/apple_dart.c
@@ -73,6 +73,8 @@
u64 *l1, *l2;
int bypass, shift;
+ struct lmb io_lmb;
+
dma_addr_t dvabase;
dma_addr_t dvaend;
@@ -123,7 +125,7 @@
off = (phys_addr_t)addr - paddr;
psize = ALIGN(size + off, DART_PAGE_SIZE);
- dva = lmb_alloc(psize, DART_PAGE_SIZE);
+ dva = io_lmb_alloc(&priv->io_lmb, psize, DART_PAGE_SIZE);
idx = dva / DART_PAGE_SIZE;
for (i = 0; i < psize / DART_PAGE_SIZE; i++) {
@@ -159,7 +161,7 @@
(unsigned long)&priv->l2[idx + i]);
priv->flush_tlb(priv);
- lmb_free(dva, psize);
+ io_lmb_free(&priv->io_lmb, dva, psize);
}
static struct iommu_ops apple_dart_ops = {
@@ -173,7 +175,7 @@
dma_addr_t addr;
phys_addr_t l2;
int ntte, nl1, nl2;
- int sid, i;
+ int ret, sid, i;
u32 params2, params4;
priv->base = dev_read_addr_ptr(dev);
@@ -212,7 +214,13 @@
priv->dvabase = DART_PAGE_SIZE;
priv->dvaend = SZ_4G - DART_PAGE_SIZE;
- lmb_add(priv->dvabase, priv->dvaend - priv->dvabase);
+ ret = io_lmb_setup(&priv->io_lmb);
+ if (ret)
+ return ret;
+ ret = io_lmb_add(&priv->io_lmb, priv->dvabase,
+ priv->dvaend - priv->dvabase);
+ if (ret)
+ return -EINVAL;
/* Disable translations. */
for (sid = 0; sid < priv->nsid; sid++)
@@ -294,6 +302,8 @@
}
priv->flush_tlb(priv);
+ io_lmb_teardown(&priv->io_lmb);
+
return 0;
}
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index a1d53cf..6ee7dc1 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -127,6 +127,14 @@
This option is an SPL-variant of the PINCTRL_GENERIC option.
See the help of PINCTRL_GENERIC for details.
+config TPL_PINCTRL_GENERIC
+ bool "Support generic pin controllers in TPL"
+ depends on TPL_PINCTRL_FULL
+ default y
+ help
+ This option is a TPL-variant of the PINCTRL_GENERIC option.
+ See the help of PINCTRL_GENERIC for details.
+
config SPL_PINMUX
bool "Support pin multiplexing controllers in SPL"
depends on SPL_PINCTRL_GENERIC
diff --git a/drivers/pinctrl/rockchip/Kconfig b/drivers/pinctrl/rockchip/Kconfig
index dc4ba34..8aa9dca 100644
--- a/drivers/pinctrl/rockchip/Kconfig
+++ b/drivers/pinctrl/rockchip/Kconfig
@@ -14,4 +14,11 @@
help
This option is an SPL-variant of the PINCTRL_ROCKCHIP option.
+config TPL_PINCTRL_ROCKCHIP
+ bool "Support Rockchip pin controllers in TPL"
+ depends on ARCH_ROCKCHIP && TPL_PINCTRL_GENERIC
+ default y
+ help
+ This option is a TPL-variant of the PINCTRL_ROCKCHIP option.
+
endif
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 4aad324..e43dbb4 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -813,7 +813,7 @@
priv->is_parallel = false;
priv->is_stacked = false;
- slave->flags &= ~SPI_XFER_MASK;
+ slave->flags &= ~SPI_XFER_LOWER;
spi_release_bus(slave);
return 0;
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 1d19b26..4251bf2 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -870,8 +870,8 @@
priv->bus = 0;
if (priv->is_parallel) {
- if (slave->flags & SPI_XFER_MASK)
- priv->bus = (slave->flags & SPI_XFER_MASK) >> 8;
+ if (slave->flags & SPI_XFER_LOWER)
+ priv->bus = 1;
if (zynqmp_qspi_update_stripe(op))
priv->stripe = 1;
}
@@ -890,7 +890,7 @@
zynqmp_qspi_chipselect(priv, 0);
priv->is_parallel = false;
- slave->flags &= ~SPI_XFER_MASK;
+ slave->flags &= ~SPI_XFER_LOWER;
return ret;
}
diff --git a/drivers/sysinfo/gazerbeam.h b/drivers/sysinfo/gazerbeam.h
index 6bf3c00..047f365 100644
--- a/drivers/sysinfo/gazerbeam.h
+++ b/drivers/sysinfo/gazerbeam.h
@@ -8,8 +8,8 @@
#include <sysinfo.h>
enum {
- BOARD_HWVERSION = SYSINFO_ID_BOARD_MODEL,
- BOARD_MULTICHANNEL = SYSINFO_ID_USER,
+ BOARD_HWVERSION = SYSID_BOARD_MODEL,
+ BOARD_MULTICHANNEL = SYSID_USER,
BOARD_VARIANT
};
diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c
index aaca318..66d2a91 100644
--- a/drivers/sysinfo/gpio.c
+++ b/drivers/sysinfo/gpio.c
@@ -38,7 +38,7 @@
struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
*val = priv->revision;
return 0;
default:
@@ -51,7 +51,7 @@
struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
switch (id) {
- case SYSINFO_ID_BOARD_MODEL: {
+ case SYSID_BOARD_MODEL: {
const char *name = NULL;
int i, ret;
u32 revision;
diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c
index 37e2ccc..2994df9 100644
--- a/drivers/sysinfo/rcar3.c
+++ b/drivers/sysinfo/rcar3.c
@@ -46,7 +46,7 @@
struct sysinfo_rcar_priv *priv = dev_get_priv(dev);
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
strncpy(val, priv->boardmodel, size);
val[size - 1] = '\0';
return 0;
diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h
index d9c5804..a7cbac0 100644
--- a/drivers/sysinfo/sandbox.h
+++ b/drivers/sysinfo/sandbox.h
@@ -5,7 +5,7 @@
*/
enum {
- BOOL_CALLED_DETECT = SYSINFO_ID_USER,
+ BOOL_CALLED_DETECT = SYSID_USER,
INT_TEST1,
INT_TEST2,
STR_VACATIONSPOT,
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-dhcom-pdk2.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-dhcom-pdk2.dts
new file mode 100644
index 0000000..3823592
--- /dev/null
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-dhcom-pdk2.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6DL-C080-R102-F0819-E-SD-RTC-T-HS-I-01D2
+ * DHCOM PCB number: 493-400 or newer
+ * PDK2 PCB number: 516-400 or newer
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-pdk2.dtsi"
+
+/ {
+ model = "DH electronics i.MX6DL DHCOM on Premium Developer Kit (2)";
+ compatible = "dh,imx6dl-dhcom-pdk2", "dh,imx6dl-dhcom-som",
+ "fsl,imx6dl";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s-plus.dts b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s-plus.dts
new file mode 100644
index 0000000..cb81ba3
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s-plus.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+ compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328";
+ model = "FriendlyElec NanoPi R2S Plus";
+
+ aliases {
+ mmc1 = &emmc;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ mmc-hs200-1_8v;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ supports-emmc;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
index 6a99816..e601d92 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
@@ -6,49 +6,474 @@
/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include "rk3568.dtsi"
/ {
model = "Qnap TS-433-4G NAS System 4-Bay";
compatible = "qnap,ts433", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ mmc0 = &sdhci;
+ rtc0 = &rtc_rv8263;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
+ pinctrl-names = "default";
+
+ key-copy {
+ label = "copy";
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_COPY>;
+ };
+
+ key-reset {
+ label = "reset";
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd1_led_pin>;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd2_led_pin>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd3_led_pin>;
+ };
+
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd4_led_pin>;
+ };
+ };
+
+ dc_12v: regulator-dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_pcie: regulator-vcc3v3-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_sys: regulator-vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_host: regulator-vcc5v0-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_otg: regulator-vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_otg_en>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: regulator-vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+};
+
+/* connected to usb_host0_xhci */
+&combphy0 {
+ status = "okay";
+};
+
+/* connected to sata1 */
+&combphy1 {
+ status = "okay";
+};
+
+/* connected to sata2 */
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
};
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
- rx_delay = <0x2f>;
- tx_delay = <0x3c>;
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&i2c0 {
+ status = "okay";
+
pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ /*
+ * turning this off, breaks access to both
+ * PCIe controllers, refclk generator perhaps
+ */
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
};
};
&i2c1 {
status = "okay";
- rtc@51 {
+ rtc_rv8263: rtc@51 {
compatible = "microcrystal,rv8263";
reg = <0x51>;
wakeup-source;
};
+
+ /* eeprom for vital-product-data on the mainboard */
+ eeprom@54 {
+ compatible = "giantec,gt24c04a", "atmel,24c04";
+ reg = <0x54>;
+ label = "VPD_MB";
+ num-addresses = <2>;
+ pagesize = <16>;
+ read-only;
+ };
+
+ /* eeprom for vital-product-data on the backplane */
+ eeprom@56 {
+ compatible = "giantec,gt24c04a", "atmel,24c04";
+ reg = <0x56>;
+ label = "VPD_BP";
+ num-addresses = <2>;
+ pagesize = <16>;
+ read-only;
+ };
};
&mdio0 {
@@ -59,12 +484,82 @@
};
&pcie30phy {
+ data-lanes = <1 2>;
status = "okay";
};
+/* Connected to a JMicron AHCI SATA controller */
&pcie3x1 {
- /* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */
reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+/* Connected to the 2.5G NIC for the upper network jack */
+&pcie3x2 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ keys {
+ copy_button_pin: copy-button-pin {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ hdd1_led_pin: hdd1-led-pin {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ hdd2_led_pin: hdd2-led-pin {
+ rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ hdd3_led_pin: hdd3-led-pin {
+ rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ hdd4_led_pin: hdd4_led-pin {
+ rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_otg_en: vcc5v0-otg-en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ vccio4-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
status = "okay";
};
@@ -75,6 +570,20 @@
status = "okay";
};
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+/*
+ * Connected to an MCU, that provides access to more LEDs,
+ * buzzer, fan control and more.
+ */
+&uart0 {
+ status = "okay";
+};
+
/*
* Pins available on CN3 connector at TTL voltage level (3V3).
* ,_ _.
@@ -84,3 +593,53 @@
&uart2 {
status = "okay";
};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+/* connected to usb_host0_xhci */
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+/* connected to usb_host1_ehci/ohci */
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+/* connected to usb_host0_ehci/ohci */
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+/* right port backside */
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/* front port */
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* left port backside */
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
new file mode 100644
index 0000000..6418286
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+ model = "CoolPi CM5 GenBook";
+ compatible = "coolpi,pi-cm5-genbook", "coolpi,pi-cm5", "rockchip,rk3588";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en>;
+ power-supply = <&vcc12v_dcin>;
+ pwms = <&pwm6 0 25000 0>;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <9800000>;
+ voltage-max-design-microvolt = <4350000>;
+ voltage-min-design-microvolt = <3000000>;
+ };
+
+ charger: dc-charger {
+ compatible = "gpio-charger";
+ charger-type = "mains";
+ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ heartbeat_led: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ wlan_led: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ };
+
+ charging_red: led-2 {
+ function = LED_FUNCTION_CHARGING;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <7000000>;
+ regulator-max-microvolt = <7000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <7000000>;
+ regulator-max-microvolt = <7000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_lcd: vcc3v3-lcd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdpwr_en>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_pwren>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc5v0_usb_host0: vcc5v0_usb30_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m3_xfer>;
+
+ cw2015@62 {
+ compatible = "cellwise,cw2015";
+ reg = <0x62>;
+
+ cellwise,battery-profile = /bits/ 8 <
+ 0x17 0x67 0x69 0x63 0x63 0x62 0x62 0x5F
+ 0x52 0x73 0x4C 0x5A 0x5B 0x4B 0x42 0x3A
+ 0x33 0x2D 0x29 0x28 0x2E 0x31 0x3C 0x49
+ 0x2C 0x2C 0x0C 0xCD 0x30 0x51 0x50 0x66
+ 0x74 0x74 0x75 0x78 0x41 0x1B 0x84 0x5F
+ 0x0B 0x34 0x1C 0x45 0x89 0x92 0xA0 0x13
+ 0x2C 0x55 0xAB 0xCB 0x80 0x5E 0x7B 0xCB
+ 0x2F 0x00 0x64 0xA5 0xB5 0x10 0x18 0x21
+ >;
+
+ cellwise,monitor-interval-ms = <3000>;
+ monitored-battery = <&battery>;
+ power-supplies = <&charger>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m3_xfer>;
+
+ touchpad: touchpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD6 IRQ_TYPE_LEVEL_LOW>;
+ hid-descr-addr = <0x0020>;
+ };
+};
+
+&gmac0 {
+ status = "disabled";
+};
+
+/* M.2 E-Key */
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ status = "disabled";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+/* M.2 M-Key ssd */
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&pinctrl {
+ lcd {
+ lcdpwr_en: lcdpwr-en {
+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bl_en: bl-en {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_pwren: usb-pwren {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ usb_otg_pwren: usb-otg-pwren {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ usb_host_pwren: usb-host-pwren {
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ bt_pwron: bt-pwron {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_clkreq: pcie-clkreq {
+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_rst: pcie-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ wifi_pwron: wifi-pwron {
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_wake: pcie-wake {
+ rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm6 {
+ pinctrl-0 = <&pwm6m1_pins>;
+ status = "okay";
+};
+
+&sdmmc {
+ status = "disabled";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim2_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <100000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_usb_host0>;
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_usb>;
+ status = "okay";
+};
+
+&usbdp_phy1 {
+ status = "okay";
+};
+
+/* For Keypad */
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/* Type C port */
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ status = "okay";
+};
+
+/* connected to a HUB for camera and BT */
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+/* USB A out */
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 70303ac..8c619c1 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -30,8 +30,6 @@
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
#ifdef CONFIG_ARM
unsigned long bi_arm_freq; /* arm frequency */
unsigned long bi_dsp_freq; /* dsp core frequency */
diff --git a/include/configs/genbook-cm5-rk3588.h b/include/configs/genbook-cm5-rk3588.h
new file mode 100644
index 0000000..194f974
--- /dev/null
+++ b/include/configs/genbook-cm5-rk3588.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __GENBOOK_CM5_RK3588_H
+#define __GENBOOK_CM5_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+/*
+ * As a laptop, there is no sdmmc, and we want to
+ * set usb the highest boot priority for third-part
+ * os installation.
+ */
+#define BOOT_TARGETS "usb mmc0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __GENBOOK_CM5_RK3588_H */
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index 53fb8c9..260a504 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -27,6 +27,12 @@
#define BOOTENV
#endif
+#ifdef CONFIG_SYS_MMC_ENV_DEV
+#define IMX93_EVK_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_DEV
+#else
+#define IMX93_EVK_MMC_ENV_DEV 0
+#endif
+
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
@@ -42,7 +48,7 @@
"boot_fit=no\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"bootm_size=0x10000000\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcdev=" __stringify(IMX93_EVK_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 0ae4fc5..8de930e 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -19,8 +19,11 @@
*/
/* Initial RAM for temporary stack, global data */
#define CFG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_SRAM_BASE 0x80000000
+#define CFG_SYS_SRAM_SIZE 0x00080000
+
#define CFG_SYS_INIT_RAM_ADDR \
- (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
+ (CFG_SYS_SRAM_BASE + CFG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */
#define CFG_SYS_SDRAM_BASE 0x88000000
diff --git a/include/configs/qnap_ts433.h b/include/configs/qnap_ts433.h
new file mode 100644
index 0000000..aee4546
--- /dev/null
+++ b/include/configs/qnap_ts433.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __QNAP_TS433_H
+#define __QNAP_TS433_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+
+#include <configs/rk3568_common.h>
+
+#endif
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 9b8ab3c..d5550a4 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -13,7 +13,9 @@
#ifndef CONFIG_XPL_BUILD
+#ifndef BOOT_TARGETS
#define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi"
+#endif
#ifdef CONFIG_ARM64
#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
deleted file mode 100644
index 06f198e..0000000
--- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Jian Hu <jian.hu@amlogic.com>
- *
- * Copyright (c) 2023, SberDevices. All Rights Reserved.
- * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
- */
-
-#ifndef __A1_PERIPHERALS_CLKC_H
-#define __A1_PERIPHERALS_CLKC_H
-
-#define CLKID_XTAL_IN 0
-#define CLKID_FIXPLL_IN 1
-#define CLKID_USB_PHY_IN 2
-#define CLKID_USB_CTRL_IN 3
-#define CLKID_HIFIPLL_IN 4
-#define CLKID_SYSPLL_IN 5
-#define CLKID_DDS_IN 6
-#define CLKID_SYS 7
-#define CLKID_CLKTREE 8
-#define CLKID_RESET_CTRL 9
-#define CLKID_ANALOG_CTRL 10
-#define CLKID_PWR_CTRL 11
-#define CLKID_PAD_CTRL 12
-#define CLKID_SYS_CTRL 13
-#define CLKID_TEMP_SENSOR 14
-#define CLKID_AM2AXI_DIV 15
-#define CLKID_SPICC_B 16
-#define CLKID_SPICC_A 17
-#define CLKID_MSR 18
-#define CLKID_AUDIO 19
-#define CLKID_JTAG_CTRL 20
-#define CLKID_SARADC_EN 21
-#define CLKID_PWM_EF 22
-#define CLKID_PWM_CD 23
-#define CLKID_PWM_AB 24
-#define CLKID_CEC 25
-#define CLKID_I2C_S 26
-#define CLKID_IR_CTRL 27
-#define CLKID_I2C_M_D 28
-#define CLKID_I2C_M_C 29
-#define CLKID_I2C_M_B 30
-#define CLKID_I2C_M_A 31
-#define CLKID_ACODEC 32
-#define CLKID_OTP 33
-#define CLKID_SD_EMMC_A 34
-#define CLKID_USB_PHY 35
-#define CLKID_USB_CTRL 36
-#define CLKID_SYS_DSPB 37
-#define CLKID_SYS_DSPA 38
-#define CLKID_DMA 39
-#define CLKID_IRQ_CTRL 40
-#define CLKID_NIC 41
-#define CLKID_GIC 42
-#define CLKID_UART_C 43
-#define CLKID_UART_B 44
-#define CLKID_UART_A 45
-#define CLKID_SYS_PSRAM 46
-#define CLKID_RSA 47
-#define CLKID_CORESIGHT 48
-#define CLKID_AM2AXI_VAD 49
-#define CLKID_AUDIO_VAD 50
-#define CLKID_AXI_DMC 51
-#define CLKID_AXI_PSRAM 52
-#define CLKID_RAMB 53
-#define CLKID_RAMA 54
-#define CLKID_AXI_SPIFC 55
-#define CLKID_AXI_NIC 56
-#define CLKID_AXI_DMA 57
-#define CLKID_CPU_CTRL 58
-#define CLKID_ROM 59
-#define CLKID_PROC_I2C 60
-#define CLKID_DSPA_SEL 61
-#define CLKID_DSPB_SEL 62
-#define CLKID_DSPA_EN 63
-#define CLKID_DSPA_EN_NIC 64
-#define CLKID_DSPB_EN 65
-#define CLKID_DSPB_EN_NIC 66
-#define CLKID_RTC 67
-#define CLKID_CECA_32K 68
-#define CLKID_CECB_32K 69
-#define CLKID_24M 70
-#define CLKID_12M 71
-#define CLKID_FCLK_DIV2_DIVN 72
-#define CLKID_GEN 73
-#define CLKID_SARADC_SEL 74
-#define CLKID_SARADC 75
-#define CLKID_PWM_A 76
-#define CLKID_PWM_B 77
-#define CLKID_PWM_C 78
-#define CLKID_PWM_D 79
-#define CLKID_PWM_E 80
-#define CLKID_PWM_F 81
-#define CLKID_SPICC 82
-#define CLKID_TS 83
-#define CLKID_SPIFC 84
-#define CLKID_USB_BUS 85
-#define CLKID_SD_EMMC 86
-#define CLKID_PSRAM 87
-#define CLKID_DMC 88
-#define CLKID_SYS_A_SEL 89
-#define CLKID_SYS_A_DIV 90
-#define CLKID_SYS_A 91
-#define CLKID_SYS_B_SEL 92
-#define CLKID_SYS_B_DIV 93
-#define CLKID_SYS_B 94
-#define CLKID_DSPA_A_SEL 95
-#define CLKID_DSPA_A_DIV 96
-#define CLKID_DSPA_A 97
-#define CLKID_DSPA_B_SEL 98
-#define CLKID_DSPA_B_DIV 99
-#define CLKID_DSPA_B 100
-#define CLKID_DSPB_A_SEL 101
-#define CLKID_DSPB_A_DIV 102
-#define CLKID_DSPB_A 103
-#define CLKID_DSPB_B_SEL 104
-#define CLKID_DSPB_B_DIV 105
-#define CLKID_DSPB_B 106
-#define CLKID_RTC_32K_IN 107
-#define CLKID_RTC_32K_DIV 108
-#define CLKID_RTC_32K_XTAL 109
-#define CLKID_RTC_32K_SEL 110
-#define CLKID_CECB_32K_IN 111
-#define CLKID_CECB_32K_DIV 112
-#define CLKID_CECB_32K_SEL_PRE 113
-#define CLKID_CECB_32K_SEL 114
-#define CLKID_CECA_32K_IN 115
-#define CLKID_CECA_32K_DIV 116
-#define CLKID_CECA_32K_SEL_PRE 117
-#define CLKID_CECA_32K_SEL 118
-#define CLKID_DIV2_PRE 119
-#define CLKID_24M_DIV2 120
-#define CLKID_GEN_SEL 121
-#define CLKID_GEN_DIV 122
-#define CLKID_SARADC_DIV 123
-#define CLKID_PWM_A_SEL 124
-#define CLKID_PWM_A_DIV 125
-#define CLKID_PWM_B_SEL 126
-#define CLKID_PWM_B_DIV 127
-#define CLKID_PWM_C_SEL 128
-#define CLKID_PWM_C_DIV 129
-#define CLKID_PWM_D_SEL 130
-#define CLKID_PWM_D_DIV 131
-#define CLKID_PWM_E_SEL 132
-#define CLKID_PWM_E_DIV 133
-#define CLKID_PWM_F_SEL 134
-#define CLKID_PWM_F_DIV 135
-#define CLKID_SPICC_SEL 136
-#define CLKID_SPICC_DIV 137
-#define CLKID_SPICC_SEL2 138
-#define CLKID_TS_DIV 139
-#define CLKID_SPIFC_SEL 140
-#define CLKID_SPIFC_DIV 141
-#define CLKID_SPIFC_SEL2 142
-#define CLKID_USB_BUS_SEL 143
-#define CLKID_USB_BUS_DIV 144
-#define CLKID_SD_EMMC_SEL 145
-#define CLKID_SD_EMMC_DIV 146
-#define CLKID_SD_EMMC_SEL2 147
-#define CLKID_PSRAM_SEL 148
-#define CLKID_PSRAM_DIV 149
-#define CLKID_PSRAM_SEL2 150
-#define CLKID_DMC_SEL 151
-#define CLKID_DMC_DIV 152
-#define CLKID_DMC_SEL2 153
-
-#endif /* __A1_PERIPHERALS_CLKC_H */
diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
deleted file mode 100644
index 2b660c0..0000000
--- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Jian Hu <jian.hu@amlogic.com>
- *
- * Copyright (c) 2023, SberDevices. All Rights Reserved.
- * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
- */
-
-#ifndef __A1_PLL_CLKC_H
-#define __A1_PLL_CLKC_H
-
-#define CLKID_FIXED_PLL_DCO 0
-#define CLKID_FIXED_PLL 1
-#define CLKID_FCLK_DIV2_DIV 2
-#define CLKID_FCLK_DIV3_DIV 3
-#define CLKID_FCLK_DIV5_DIV 4
-#define CLKID_FCLK_DIV7_DIV 5
-#define CLKID_FCLK_DIV2 6
-#define CLKID_FCLK_DIV3 7
-#define CLKID_FCLK_DIV5 8
-#define CLKID_FCLK_DIV7 9
-#define CLKID_HIFI_PLL 10
-
-#endif /* __A1_PLL_CLKC_H */
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
deleted file mode 100644
index f561f5c..0000000
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (c) 2018 Baylibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
-#define __AXG_AUDIO_CLKC_BINDINGS_H
-
-#define AUD_CLKID_DDR_ARB 29
-#define AUD_CLKID_PDM 30
-#define AUD_CLKID_TDMIN_A 31
-#define AUD_CLKID_TDMIN_B 32
-#define AUD_CLKID_TDMIN_C 33
-#define AUD_CLKID_TDMIN_LB 34
-#define AUD_CLKID_TDMOUT_A 35
-#define AUD_CLKID_TDMOUT_B 36
-#define AUD_CLKID_TDMOUT_C 37
-#define AUD_CLKID_FRDDR_A 38
-#define AUD_CLKID_FRDDR_B 39
-#define AUD_CLKID_FRDDR_C 40
-#define AUD_CLKID_TODDR_A 41
-#define AUD_CLKID_TODDR_B 42
-#define AUD_CLKID_TODDR_C 43
-#define AUD_CLKID_LOOPBACK 44
-#define AUD_CLKID_SPDIFIN 45
-#define AUD_CLKID_SPDIFOUT 46
-#define AUD_CLKID_RESAMPLE 47
-#define AUD_CLKID_POWER_DETECT 48
-#define AUD_CLKID_MST_A_MCLK 49
-#define AUD_CLKID_MST_B_MCLK 50
-#define AUD_CLKID_MST_C_MCLK 51
-#define AUD_CLKID_MST_D_MCLK 52
-#define AUD_CLKID_MST_E_MCLK 53
-#define AUD_CLKID_MST_F_MCLK 54
-#define AUD_CLKID_SPDIFOUT_CLK 55
-#define AUD_CLKID_SPDIFIN_CLK 56
-#define AUD_CLKID_PDM_DCLK 57
-#define AUD_CLKID_PDM_SYSCLK 58
-#define AUD_CLKID_MST_A_SCLK 79
-#define AUD_CLKID_MST_B_SCLK 80
-#define AUD_CLKID_MST_C_SCLK 81
-#define AUD_CLKID_MST_D_SCLK 82
-#define AUD_CLKID_MST_E_SCLK 83
-#define AUD_CLKID_MST_F_SCLK 84
-#define AUD_CLKID_MST_A_LRCLK 86
-#define AUD_CLKID_MST_B_LRCLK 87
-#define AUD_CLKID_MST_C_LRCLK 88
-#define AUD_CLKID_MST_D_LRCLK 89
-#define AUD_CLKID_MST_E_LRCLK 90
-#define AUD_CLKID_MST_F_LRCLK 91
-#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
-#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
-#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
-#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
-#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
-#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
-#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
-#define AUD_CLKID_TDMIN_A_SCLK 123
-#define AUD_CLKID_TDMIN_B_SCLK 124
-#define AUD_CLKID_TDMIN_C_SCLK 125
-#define AUD_CLKID_TDMIN_LB_SCLK 126
-#define AUD_CLKID_TDMOUT_A_SCLK 127
-#define AUD_CLKID_TDMOUT_B_SCLK 128
-#define AUD_CLKID_TDMOUT_C_SCLK 129
-#define AUD_CLKID_TDMIN_A_LRCLK 130
-#define AUD_CLKID_TDMIN_B_LRCLK 131
-#define AUD_CLKID_TDMIN_C_LRCLK 132
-#define AUD_CLKID_TDMIN_LB_LRCLK 133
-#define AUD_CLKID_TDMOUT_A_LRCLK 134
-#define AUD_CLKID_TDMOUT_B_LRCLK 135
-#define AUD_CLKID_TDMOUT_C_LRCLK 136
-#define AUD_CLKID_SPDIFOUT_B 151
-#define AUD_CLKID_SPDIFOUT_B_CLK 152
-#define AUD_CLKID_TDM_MCLK_PAD0 155
-#define AUD_CLKID_TDM_MCLK_PAD1 156
-#define AUD_CLKID_TDM_LRCLK_PAD0 157
-#define AUD_CLKID_TDM_LRCLK_PAD1 158
-#define AUD_CLKID_TDM_LRCLK_PAD2 159
-#define AUD_CLKID_TDM_SCLK_PAD0 160
-#define AUD_CLKID_TDM_SCLK_PAD1 161
-#define AUD_CLKID_TDM_SCLK_PAD2 162
-#define AUD_CLKID_TOP 163
-#define AUD_CLKID_TORAM 164
-#define AUD_CLKID_EQDRC 165
-#define AUD_CLKID_RESAMPLE_B 166
-#define AUD_CLKID_TOVAD 167
-#define AUD_CLKID_LOCKER 168
-#define AUD_CLKID_SPDIFIN_LB 169
-#define AUD_CLKID_FRDDR_D 170
-#define AUD_CLKID_TODDR_D 171
-#define AUD_CLKID_LOOPBACK_B 172
-
-#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
deleted file mode 100644
index 93752ea..0000000
--- a/include/dt-bindings/clock/axg-clkc.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Meson-AXG clock tree IDs
- *
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- */
-
-#ifndef __AXG_CLKC_H
-#define __AXG_CLKC_H
-
-#define CLKID_SYS_PLL 0
-#define CLKID_FIXED_PLL 1
-#define CLKID_FCLK_DIV2 2
-#define CLKID_FCLK_DIV3 3
-#define CLKID_FCLK_DIV4 4
-#define CLKID_FCLK_DIV5 5
-#define CLKID_FCLK_DIV7 6
-#define CLKID_GP0_PLL 7
-#define CLKID_CLK81 10
-#define CLKID_MPLL0 11
-#define CLKID_MPLL1 12
-#define CLKID_MPLL2 13
-#define CLKID_MPLL3 14
-#define CLKID_DDR 15
-#define CLKID_AUDIO_LOCKER 16
-#define CLKID_MIPI_DSI_HOST 17
-#define CLKID_ISA 18
-#define CLKID_PL301 19
-#define CLKID_PERIPHS 20
-#define CLKID_SPICC0 21
-#define CLKID_I2C 22
-#define CLKID_RNG0 23
-#define CLKID_UART0 24
-#define CLKID_MIPI_DSI_PHY 25
-#define CLKID_SPICC1 26
-#define CLKID_PCIE_A 27
-#define CLKID_PCIE_B 28
-#define CLKID_HIU_IFACE 29
-#define CLKID_ASSIST_MISC 30
-#define CLKID_SD_EMMC_B 31
-#define CLKID_SD_EMMC_C 32
-#define CLKID_DMA 33
-#define CLKID_SPI 34
-#define CLKID_AUDIO 35
-#define CLKID_ETH 36
-#define CLKID_UART1 37
-#define CLKID_G2D 38
-#define CLKID_USB0 39
-#define CLKID_USB1 40
-#define CLKID_RESET 41
-#define CLKID_USB 42
-#define CLKID_AHB_ARB0 43
-#define CLKID_EFUSE 44
-#define CLKID_BOOT_ROM 45
-#define CLKID_AHB_DATA_BUS 46
-#define CLKID_AHB_CTRL_BUS 47
-#define CLKID_USB1_DDR_BRIDGE 48
-#define CLKID_USB0_DDR_BRIDGE 49
-#define CLKID_MMC_PCLK 50
-#define CLKID_VPU_INTR 51
-#define CLKID_SEC_AHB_AHB3_BRIDGE 52
-#define CLKID_GIC 53
-#define CLKID_AO_MEDIA_CPU 54
-#define CLKID_AO_AHB_SRAM 55
-#define CLKID_AO_AHB_BUS 56
-#define CLKID_AO_IFACE 57
-#define CLKID_AO_I2C 58
-#define CLKID_SD_EMMC_B_CLK0 59
-#define CLKID_SD_EMMC_C_CLK0 60
-#define CLKID_HIFI_PLL 69
-#define CLKID_PCIE_CML_EN0 79
-#define CLKID_PCIE_CML_EN1 80
-#define CLKID_GEN_CLK 84
-#define CLKID_VPU_0_SEL 92
-#define CLKID_VPU_0 93
-#define CLKID_VPU_1_SEL 95
-#define CLKID_VPU_1 96
-#define CLKID_VPU 97
-#define CLKID_VAPB_0_SEL 99
-#define CLKID_VAPB_0 100
-#define CLKID_VAPB_1_SEL 102
-#define CLKID_VAPB_1 103
-#define CLKID_VAPB_SEL 104
-#define CLKID_VAPB 105
-#define CLKID_VCLK 106
-#define CLKID_VCLK2 107
-#define CLKID_VCLK_DIV1 122
-#define CLKID_VCLK_DIV2 123
-#define CLKID_VCLK_DIV4 124
-#define CLKID_VCLK_DIV6 125
-#define CLKID_VCLK_DIV12 126
-#define CLKID_VCLK2_DIV1 127
-#define CLKID_VCLK2_DIV2 128
-#define CLKID_VCLK2_DIV4 129
-#define CLKID_VCLK2_DIV6 130
-#define CLKID_VCLK2_DIV12 131
-#define CLKID_CTS_ENCL 133
-#define CLKID_VDIN_MEAS 136
-
-#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
deleted file mode 100644
index 0bb17ff..0000000
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
-#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
-
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-/* R9A07G044 CPG Core Clocks */
-#define R9A07G044_CLK_I 0
-#define R9A07G044_CLK_I2 1
-#define R9A07G044_CLK_G 2
-#define R9A07G044_CLK_S0 3
-#define R9A07G044_CLK_S1 4
-#define R9A07G044_CLK_SPI0 5
-#define R9A07G044_CLK_SPI1 6
-#define R9A07G044_CLK_SD0 7
-#define R9A07G044_CLK_SD1 8
-#define R9A07G044_CLK_M0 9
-#define R9A07G044_CLK_M1 10
-#define R9A07G044_CLK_M2 11
-#define R9A07G044_CLK_M3 12
-#define R9A07G044_CLK_M4 13
-#define R9A07G044_CLK_HP 14
-#define R9A07G044_CLK_TSU 15
-#define R9A07G044_CLK_ZT 16
-#define R9A07G044_CLK_P0 17
-#define R9A07G044_CLK_P1 18
-#define R9A07G044_CLK_P2 19
-#define R9A07G044_CLK_AT 20
-#define R9A07G044_OSCCLK 21
-#define R9A07G044_CLK_P0_DIV2 22
-
-/* R9A07G044 Module Clocks */
-#define R9A07G044_CA55_SCLK 0
-#define R9A07G044_CA55_PCLK 1
-#define R9A07G044_CA55_ATCLK 2
-#define R9A07G044_CA55_GICCLK 3
-#define R9A07G044_CA55_PERICLK 4
-#define R9A07G044_CA55_ACLK 5
-#define R9A07G044_CA55_TSCLK 6
-#define R9A07G044_GIC600_GICCLK 7
-#define R9A07G044_IA55_CLK 8
-#define R9A07G044_IA55_PCLK 9
-#define R9A07G044_MHU_PCLK 10
-#define R9A07G044_SYC_CNT_CLK 11
-#define R9A07G044_DMAC_ACLK 12
-#define R9A07G044_DMAC_PCLK 13
-#define R9A07G044_OSTM0_PCLK 14
-#define R9A07G044_OSTM1_PCLK 15
-#define R9A07G044_OSTM2_PCLK 16
-#define R9A07G044_MTU_X_MCK_MTU3 17
-#define R9A07G044_POE3_CLKM_POE 18
-#define R9A07G044_GPT_PCLK 19
-#define R9A07G044_POEG_A_CLKP 20
-#define R9A07G044_POEG_B_CLKP 21
-#define R9A07G044_POEG_C_CLKP 22
-#define R9A07G044_POEG_D_CLKP 23
-#define R9A07G044_WDT0_PCLK 24
-#define R9A07G044_WDT0_CLK 25
-#define R9A07G044_WDT1_PCLK 26
-#define R9A07G044_WDT1_CLK 27
-#define R9A07G044_WDT2_PCLK 28
-#define R9A07G044_WDT2_CLK 29
-#define R9A07G044_SPI_CLK2 30
-#define R9A07G044_SPI_CLK 31
-#define R9A07G044_SDHI0_IMCLK 32
-#define R9A07G044_SDHI0_IMCLK2 33
-#define R9A07G044_SDHI0_CLK_HS 34
-#define R9A07G044_SDHI0_ACLK 35
-#define R9A07G044_SDHI1_IMCLK 36
-#define R9A07G044_SDHI1_IMCLK2 37
-#define R9A07G044_SDHI1_CLK_HS 38
-#define R9A07G044_SDHI1_ACLK 39
-#define R9A07G044_GPU_CLK 40
-#define R9A07G044_GPU_AXI_CLK 41
-#define R9A07G044_GPU_ACE_CLK 42
-#define R9A07G044_ISU_ACLK 43
-#define R9A07G044_ISU_PCLK 44
-#define R9A07G044_H264_CLK_A 45
-#define R9A07G044_H264_CLK_P 46
-#define R9A07G044_CRU_SYSCLK 47
-#define R9A07G044_CRU_VCLK 48
-#define R9A07G044_CRU_PCLK 49
-#define R9A07G044_CRU_ACLK 50
-#define R9A07G044_MIPI_DSI_PLLCLK 51
-#define R9A07G044_MIPI_DSI_SYSCLK 52
-#define R9A07G044_MIPI_DSI_ACLK 53
-#define R9A07G044_MIPI_DSI_PCLK 54
-#define R9A07G044_MIPI_DSI_VCLK 55
-#define R9A07G044_MIPI_DSI_LPCLK 56
-#define R9A07G044_LCDC_CLK_A 57
-#define R9A07G044_LCDC_CLK_P 58
-#define R9A07G044_LCDC_CLK_D 59
-#define R9A07G044_SSI0_PCLK2 60
-#define R9A07G044_SSI0_PCLK_SFR 61
-#define R9A07G044_SSI1_PCLK2 62
-#define R9A07G044_SSI1_PCLK_SFR 63
-#define R9A07G044_SSI2_PCLK2 64
-#define R9A07G044_SSI2_PCLK_SFR 65
-#define R9A07G044_SSI3_PCLK2 66
-#define R9A07G044_SSI3_PCLK_SFR 67
-#define R9A07G044_SRC_CLKP 68
-#define R9A07G044_USB_U2H0_HCLK 69
-#define R9A07G044_USB_U2H1_HCLK 70
-#define R9A07G044_USB_U2P_EXR_CPUCLK 71
-#define R9A07G044_USB_PCLK 72
-#define R9A07G044_ETH0_CLK_AXI 73
-#define R9A07G044_ETH0_CLK_CHI 74
-#define R9A07G044_ETH1_CLK_AXI 75
-#define R9A07G044_ETH1_CLK_CHI 76
-#define R9A07G044_I2C0_PCLK 77
-#define R9A07G044_I2C1_PCLK 78
-#define R9A07G044_I2C2_PCLK 79
-#define R9A07G044_I2C3_PCLK 80
-#define R9A07G044_SCIF0_CLK_PCK 81
-#define R9A07G044_SCIF1_CLK_PCK 82
-#define R9A07G044_SCIF2_CLK_PCK 83
-#define R9A07G044_SCIF3_CLK_PCK 84
-#define R9A07G044_SCIF4_CLK_PCK 85
-#define R9A07G044_SCI0_CLKP 86
-#define R9A07G044_SCI1_CLKP 87
-#define R9A07G044_IRDA_CLKP 88
-#define R9A07G044_RSPI0_CLKB 89
-#define R9A07G044_RSPI1_CLKB 90
-#define R9A07G044_RSPI2_CLKB 91
-#define R9A07G044_CANFD_PCLK 92
-#define R9A07G044_GPIO_HCLK 93
-#define R9A07G044_ADC_ADCLK 94
-#define R9A07G044_ADC_PCLK 95
-#define R9A07G044_TSU_PCLK 96
-
-/* R9A07G044 Resets */
-#define R9A07G044_CA55_RST_1_0 0
-#define R9A07G044_CA55_RST_1_1 1
-#define R9A07G044_CA55_RST_3_0 2
-#define R9A07G044_CA55_RST_3_1 3
-#define R9A07G044_CA55_RST_4 4
-#define R9A07G044_CA55_RST_5 5
-#define R9A07G044_CA55_RST_6 6
-#define R9A07G044_CA55_RST_7 7
-#define R9A07G044_CA55_RST_8 8
-#define R9A07G044_CA55_RST_9 9
-#define R9A07G044_CA55_RST_10 10
-#define R9A07G044_CA55_RST_11 11
-#define R9A07G044_CA55_RST_12 12
-#define R9A07G044_GIC600_GICRESET_N 13
-#define R9A07G044_GIC600_DBG_GICRESET_N 14
-#define R9A07G044_IA55_RESETN 15
-#define R9A07G044_MHU_RESETN 16
-#define R9A07G044_DMAC_ARESETN 17
-#define R9A07G044_DMAC_RST_ASYNC 18
-#define R9A07G044_SYC_RESETN 19
-#define R9A07G044_OSTM0_PRESETZ 20
-#define R9A07G044_OSTM1_PRESETZ 21
-#define R9A07G044_OSTM2_PRESETZ 22
-#define R9A07G044_MTU_X_PRESET_MTU3 23
-#define R9A07G044_POE3_RST_M_REG 24
-#define R9A07G044_GPT_RST_C 25
-#define R9A07G044_POEG_A_RST 26
-#define R9A07G044_POEG_B_RST 27
-#define R9A07G044_POEG_C_RST 28
-#define R9A07G044_POEG_D_RST 29
-#define R9A07G044_WDT0_PRESETN 30
-#define R9A07G044_WDT1_PRESETN 31
-#define R9A07G044_WDT2_PRESETN 32
-#define R9A07G044_SPI_RST 33
-#define R9A07G044_SDHI0_IXRST 34
-#define R9A07G044_SDHI1_IXRST 35
-#define R9A07G044_GPU_RESETN 36
-#define R9A07G044_GPU_AXI_RESETN 37
-#define R9A07G044_GPU_ACE_RESETN 38
-#define R9A07G044_ISU_ARESETN 39
-#define R9A07G044_ISU_PRESETN 40
-#define R9A07G044_H264_X_RESET_VCP 41
-#define R9A07G044_H264_CP_PRESET_P 42
-#define R9A07G044_CRU_CMN_RSTB 43
-#define R9A07G044_CRU_PRESETN 44
-#define R9A07G044_CRU_ARESETN 45
-#define R9A07G044_MIPI_DSI_CMN_RSTB 46
-#define R9A07G044_MIPI_DSI_ARESET_N 47
-#define R9A07G044_MIPI_DSI_PRESET_N 48
-#define R9A07G044_LCDC_RESET_N 49
-#define R9A07G044_SSI0_RST_M2_REG 50
-#define R9A07G044_SSI1_RST_M2_REG 51
-#define R9A07G044_SSI2_RST_M2_REG 52
-#define R9A07G044_SSI3_RST_M2_REG 53
-#define R9A07G044_SRC_RST 54
-#define R9A07G044_USB_U2H0_HRESETN 55
-#define R9A07G044_USB_U2H1_HRESETN 56
-#define R9A07G044_USB_U2P_EXL_SYSRST 57
-#define R9A07G044_USB_PRESETN 58
-#define R9A07G044_ETH0_RST_HW_N 59
-#define R9A07G044_ETH1_RST_HW_N 60
-#define R9A07G044_I2C0_MRST 61
-#define R9A07G044_I2C1_MRST 62
-#define R9A07G044_I2C2_MRST 63
-#define R9A07G044_I2C3_MRST 64
-#define R9A07G044_SCIF0_RST_SYSTEM_N 65
-#define R9A07G044_SCIF1_RST_SYSTEM_N 66
-#define R9A07G044_SCIF2_RST_SYSTEM_N 67
-#define R9A07G044_SCIF3_RST_SYSTEM_N 68
-#define R9A07G044_SCIF4_RST_SYSTEM_N 69
-#define R9A07G044_SCI0_RST 70
-#define R9A07G044_SCI1_RST 71
-#define R9A07G044_IRDA_RST 72
-#define R9A07G044_RSPI0_RST 73
-#define R9A07G044_RSPI1_RST 74
-#define R9A07G044_RSPI2_RST 75
-#define R9A07G044_CANFD_RSTP_N 76
-#define R9A07G044_CANFD_RSTC_N 77
-#define R9A07G044_GPIO_RSTN 78
-#define R9A07G044_GPIO_PORT_RESETN 79
-#define R9A07G044_GPIO_SPARE_RESETN 80
-#define R9A07G044_ADC_PRESETN 81
-#define R9A07G044_ADC_ADRST_N 82
-#define R9A07G044_TSU_PRESETN 83
-
-#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h
deleted file mode 100644
index 40e57a5..0000000
--- a/include/dt-bindings/gpio/meson-a1-gpio.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Qianggui Song <qianggui.song@amlogic.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
-#define _DT_BINDINGS_MESON_A1_GPIO_H
-
-#define GPIOP_0 0
-#define GPIOP_1 1
-#define GPIOP_2 2
-#define GPIOP_3 3
-#define GPIOP_4 4
-#define GPIOP_5 5
-#define GPIOP_6 6
-#define GPIOP_7 7
-#define GPIOP_8 8
-#define GPIOP_9 9
-#define GPIOP_10 10
-#define GPIOP_11 11
-#define GPIOP_12 12
-#define GPIOB_0 13
-#define GPIOB_1 14
-#define GPIOB_2 15
-#define GPIOB_3 16
-#define GPIOB_4 17
-#define GPIOB_5 18
-#define GPIOB_6 19
-#define GPIOX_0 20
-#define GPIOX_1 21
-#define GPIOX_2 22
-#define GPIOX_3 23
-#define GPIOX_4 24
-#define GPIOX_5 25
-#define GPIOX_6 26
-#define GPIOX_7 27
-#define GPIOX_8 28
-#define GPIOX_9 29
-#define GPIOX_10 30
-#define GPIOX_11 31
-#define GPIOX_12 32
-#define GPIOX_13 33
-#define GPIOX_14 34
-#define GPIOX_15 35
-#define GPIOX_16 36
-#define GPIOF_0 37
-#define GPIOF_1 38
-#define GPIOF_2 39
-#define GPIOF_3 40
-#define GPIOF_4 41
-#define GPIOF_5 42
-#define GPIOF_6 43
-#define GPIOF_7 44
-#define GPIOF_8 45
-#define GPIOF_9 46
-#define GPIOF_10 47
-#define GPIOF_11 48
-#define GPIOF_12 49
-#define GPIOA_0 50
-#define GPIOA_1 51
-#define GPIOA_2 52
-#define GPIOA_3 53
-#define GPIOA_4 54
-#define GPIOA_5 55
-#define GPIOA_6 56
-#define GPIOA_7 57
-#define GPIOA_8 58
-#define GPIOA_9 59
-#define GPIOA_10 60
-#define GPIOA_11 61
-
-#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
deleted file mode 100644
index 35b6f69..0000000
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/*
- * This header provides constants for the ARM GIC.
- */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/* interrupt specifier cell 0 */
-
-#define GIC_SPI 0
-#define GIC_PPI 1
-
-/*
- * Interrupt specifier cell 2.
- * The flags in irq.h are valid, plus those below.
- */
-#define GIC_CPU_MASK_RAW(x) ((x) << 8)
-#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
-
-#endif
diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
deleted file mode 100644
index 34ce778..0000000
--- a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * This header provides constants for Renesas RZ/G2L family IRQC bindings.
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- *
- */
-
-#ifndef __DT_BINDINGS_IRQC_RZG2L_H
-#define __DT_BINDINGS_IRQC_RZG2L_H
-
-/* NMI maps to SPI0 */
-#define RZG2L_NMI 0
-
-/* IRQ0-7 map to SPI1-8 */
-#define RZG2L_IRQ0 1
-#define RZG2L_IRQ1 2
-#define RZG2L_IRQ2 3
-#define RZG2L_IRQ3 4
-#define RZG2L_IRQ4 5
-#define RZG2L_IRQ5 6
-#define RZG2L_IRQ6 7
-#define RZG2L_IRQ7 8
-
-#endif /* __DT_BINDINGS_IRQC_RZG2L_H */
diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
deleted file mode 100644
index c78ed5e..0000000
--- a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * This header provides constants for Renesas RZ/G2L family pinctrl bindings.
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- *
- */
-
-#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H
-#define __DT_BINDINGS_RZG2L_PINCTRL_H
-
-#define RZG2L_PINS_PER_PORT 8
-
-/*
- * Create the pin index from its bank and position numbers and store in
- * the upper 16 bits the alternate function identifier
- */
-#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
-
-/* Convert a port and pin label to its global pin index */
-#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
-
-#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */
diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h
deleted file mode 100644
index 8e39dfc..0000000
--- a/include/dt-bindings/power/meson-a1-power.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2023 SberDevices, Inc.
- * Author: Alexey Romanov <avromanov@sberdevices.ru>
- */
-
-#ifndef _DT_BINDINGS_MESON_A1_POWER_H
-#define _DT_BINDINGS_MESON_A1_POWER_H
-
-#define PWRC_DSPA_ID 8
-#define PWRC_DSPB_ID 9
-#define PWRC_UART_ID 10
-#define PWRC_DMC_ID 11
-#define PWRC_I2C_ID 12
-#define PWRC_PSRAM_ID 13
-#define PWRC_ACODEC_ID 14
-#define PWRC_AUDIO_ID 15
-#define PWRC_OTP_ID 16
-#define PWRC_DMA_ID 17
-#define PWRC_SD_EMMC_ID 18
-#define PWRC_RAMA_ID 19
-#define PWRC_RAMB_ID 20
-#define PWRC_IR_ID 21
-#define PWRC_SPICC_ID 22
-#define PWRC_SPIFC_ID 23
-#define PWRC_USB_ID 24
-#define PWRC_NIC_ID 25
-#define PWRC_PDMIN_ID 26
-#define PWRC_RSA_ID 27
-#define PWRC_MAX_ID 28
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
deleted file mode 100644
index 2c749c6..0000000
--- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * Copyright (c) 2023, SberDevices, Inc.
- * Author: Alexey Romanov <avromanov@salutedevices.com>
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
-
-/* RESET0 */
-/* 0 */
-#define RESET_AM2AXI_VAD 1
-/* 2-3 */
-#define RESET_PSRAM 4
-#define RESET_PAD_CTRL 5
-/* 6 */
-#define RESET_TEMP_SENSOR 7
-#define RESET_AM2AXI_DEV 8
-/* 9 */
-#define RESET_SPICC_A 10
-#define RESET_MSR_CLK 11
-#define RESET_AUDIO 12
-#define RESET_ANALOG_CTRL 13
-#define RESET_SAR_ADC 14
-#define RESET_AUDIO_VAD 15
-#define RESET_CEC 16
-#define RESET_PWM_EF 17
-#define RESET_PWM_CD 18
-#define RESET_PWM_AB 19
-/* 20 */
-#define RESET_IR_CTRL 21
-#define RESET_I2C_S_A 22
-/* 23 */
-#define RESET_I2C_M_D 24
-#define RESET_I2C_M_C 25
-#define RESET_I2C_M_B 26
-#define RESET_I2C_M_A 27
-#define RESET_I2C_PROD_AHB 28
-#define RESET_I2C_PROD 29
-/* 30-31 */
-
-/* RESET1 */
-#define RESET_ACODEC 32
-#define RESET_DMA 33
-#define RESET_SD_EMMC_A 34
-/* 35 */
-#define RESET_USBCTRL 36
-/* 37 */
-#define RESET_USBPHY 38
-/* 39-41 */
-#define RESET_RSA 42
-#define RESET_DMC 43
-/* 44 */
-#define RESET_IRQ_CTRL 45
-/* 46 */
-#define RESET_NIC_VAD 47
-#define RESET_NIC_AXI 48
-#define RESET_RAMA 49
-#define RESET_RAMB 50
-/* 51-52 */
-#define RESET_ROM 53
-#define RESET_SPIFC 54
-#define RESET_GIC 55
-#define RESET_UART_C 56
-#define RESET_UART_B 57
-#define RESET_UART_A 58
-#define RESET_OSC_RING 59
-/* 60-63 */
-
-/* RESET2 */
-/* 64-95 */
-
-#endif
diff --git a/include/efi.h b/include/efi.h
index 84640cf..c559fda 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -669,4 +669,38 @@
*/
void efi_show_tables(struct efi_system_table *systab);
+/**
+ * efi_get_basename() - Get the default filename to use when loading
+ *
+ * E.g. this function returns BOOTAA64.EFI for an aarch target
+ *
+ * Return: Default EFI filename
+ */
+const char *efi_get_basename(void);
+
+#ifdef CONFIG_SANDBOX
+#include <asm/state.h>
+#endif
+
+static inline bool efi_use_host_arch(void)
+{
+#ifdef CONFIG_SANDBOX
+ struct sandbox_state *state = state_get_current();
+
+ return state->native;
+#else
+ return false;
+#endif
+}
+
+/**
+ * efi_get_pxe_arch() - Get the architecture value for PXE
+ *
+ * See:
+ * http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
+ *
+ * Return: Architecture value
+ */
+int efi_get_pxe_arch(void);
+
#endif /* _LINUX_EFI_H */
diff --git a/include/efi_default_filename.h b/include/efi_default_filename.h
deleted file mode 100644
index 7793298..0000000
--- a/include/efi_default_filename.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * When a boot option does not provide a file path the EFI file to be
- * booted is \EFI\BOOT\$(BOOTEFI_NAME).EFI. The architecture specific
- * file name is defined in this include.
- *
- * Copyright (c) 2022, Heinrich Schuchardt <xypron.glpk@gmx.de>
- * Copyright (c) 2022, Linaro Limited
- */
-
-#ifndef _EFI_DEFAULT_FILENAME_H
-#define _EFI_DEFAULT_FILENAME_H
-
-#include <host_arch.h>
-
-#undef BOOTEFI_NAME
-
-#ifdef CONFIG_SANDBOX
-
-#if HOST_ARCH == HOST_ARCH_X86_64
-#define BOOTEFI_NAME "BOOTX64.EFI"
-#elif HOST_ARCH == HOST_ARCH_X86
-#define BOOTEFI_NAME "BOOTIA32.EFI"
-#elif HOST_ARCH == HOST_ARCH_AARCH64
-#define BOOTEFI_NAME "BOOTAA64.EFI"
-#elif HOST_ARCH == HOST_ARCH_ARM
-#define BOOTEFI_NAME "BOOTARM.EFI"
-#elif HOST_ARCH == HOST_ARCH_RISCV32
-#define BOOTEFI_NAME "BOOTRISCV32.EFI"
-#elif HOST_ARCH == HOST_ARCH_RISCV64
-#define BOOTEFI_NAME "BOOTRISCV64.EFI"
-#else
-#error Unsupported UEFI architecture
-#endif
-
-#else
-
-#if defined(CONFIG_ARM64)
-#define BOOTEFI_NAME "BOOTAA64.EFI"
-#elif defined(CONFIG_ARM)
-#define BOOTEFI_NAME "BOOTARM.EFI"
-#elif defined(CONFIG_X86_64)
-#define BOOTEFI_NAME "BOOTX64.EFI"
-#elif defined(CONFIG_X86)
-#define BOOTEFI_NAME "BOOTIA32.EFI"
-#elif defined(CONFIG_ARCH_RV32I)
-#define BOOTEFI_NAME "BOOTRISCV32.EFI"
-#elif defined(CONFIG_ARCH_RV64I)
-#define BOOTEFI_NAME "BOOTRISCV64.EFI"
-#else
-#error Unsupported UEFI architecture
-#endif
-
-#endif
-
-#endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 291eca5c..39809ea 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -858,7 +858,7 @@
struct efi_device_path *efi_dp_from_eth(void);
struct efi_device_path *efi_dp_from_mem(uint32_t mem_type,
uint64_t start_address,
- uint64_t end_address);
+ size_t size);
/* Determine the last device path node that is not the end node. */
const struct efi_device_path *efi_dp_last_node(
const struct efi_device_path *dp);
diff --git a/include/imx8image.h b/include/imx8image.h
index 85fb642..6b95e93 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -146,6 +146,7 @@
enum imx8image_cmd {
CMD_INVALID,
CMD_BOOT_FROM,
+ CMD_DCD_SKIP,
CMD_FUSE_VERSION,
CMD_SW_VERSION,
CMD_MSG_BLOCK,
diff --git a/include/lmb.h b/include/lmb.h
index 2201d6f..f221f0c 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -156,6 +156,57 @@
return lmb_alloc_addr(addr, len) == addr ? 0 : -1;
}
+/**
+ * io_lmb_setup() - Initialize LMB struct
+ * @io_lmb: IO LMB to initialize
+ *
+ * Returns: 0 on success, negative error code on failure
+ */
+int io_lmb_setup(struct lmb *io_lmb);
+
+/**
+ * io_lmb_teardown() - Tear LMB struct down
+ * @io_lmb: IO LMB to teardown
+ */
+void io_lmb_teardown(struct lmb *io_lmb);
+
+/**
+ * io_lmb_add() - Add an IOVA range for allocations
+ * @io_lmb: LMB to add the space to
+ * @base: Base Address of region to add
+ * @size: Size of the region to add
+ *
+ * Add the IOVA space [base, base + size] to be managed by io_lmb.
+ *
+ * Returns: 0 if the region addition was successful, -1 on failure
+ */
+long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size);
+
+/**
+ * io_lmb_alloc() - Allocate specified IO memory address with specified alignment
+ * @io_lmb: LMB to alloc from
+ * @size: Size of the region requested
+ * @align: Required address and size alignment
+ *
+ * Allocate a region of IO memory. The base parameter is used to specify the
+ * base address of the requested region.
+ *
+ * Return: base IO address on success, 0 on error
+ */
+phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align);
+
+/**
+ * io_lmb_free() - Free up a region of IOVA space
+ * @io_lmb: LMB to return the IO address space to
+ * @base: Base Address of region to be freed
+ * @size: Size of the region to be freed
+ *
+ * Free up a region of IOVA space.
+ *
+ * Return: 0 if successful, -1 on failure
+ */
+long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size);
+
#endif /* __KERNEL__ */
#endif /* _LINUX_LMB_H */
diff --git a/include/net-common.h b/include/net-common.h
index fd7c5e7..b7a519e 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -8,6 +8,7 @@
#include <env.h>
#include <hexdump.h>
#include <linux/if_ether.h>
+#include <linux/sizes.h>
#include <linux/types.h>
#include <rand.h>
#include <time.h>
@@ -425,6 +426,16 @@
*/
struct in_addr string_to_ip(const char *s);
+/**
+ * ip_to_string() - Convert a string to ip address
+ *
+ * Implemented in lib/net_utils.c (built unconditionally)
+ *
+ * @x: Input ip to parse
+ * @s: string containing the parsed ip address
+ */
+void ip_to_string(struct in_addr x, char *s);
+
/* copy a filename (allow for "..." notation, limit length) */
void copy_filename(char *dst, const char *src, int size);
@@ -494,7 +505,7 @@
*
* @dst_addr: destination address to download the file
* @uri: uri string of target file of wget
- * Return: downloaded file size, negative if failed
+ * Return: zero on success, negative if failed
*/
int wget_with_dns(ulong dst_addr, char *uri);
/**
@@ -506,4 +517,55 @@
bool wget_validate_uri(char *uri);
//int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+/**
+ * enum wget_http_method - http method
+ */
+enum wget_http_method {
+ WGET_HTTP_METHOD_GET,
+ WGET_HTTP_METHOD_POST,
+ WGET_HTTP_METHOD_PATCH,
+ WGET_HTTP_METHOD_OPTIONS,
+ WGET_HTTP_METHOD_CONNECT,
+ WGET_HTTP_METHOD_HEAD,
+ WGET_HTTP_METHOD_PUT,
+ WGET_HTTP_METHOD_DELETE,
+ WGET_HTTP_METHOD_TRACE,
+ WGET_HTTP_METHOD_MAX
+};
+
+/**
+ * define MAX_HTTP_HEADERS_SIZE - maximum headers buffer size
+ *
+ * When receiving http headers, wget fills a buffer with up
+ * to MAX_HTTP_HEADERS_SIZE bytes of header information.
+ */
+#define MAX_HTTP_HEADERS_SIZE SZ_64K
+
+/**
+ * struct wget_http_info - wget parameters
+ * @method: HTTP Method. Filled by client.
+ * @status_code: HTTP status code. Filled by wget.
+ * @file_size: download size. Filled by wget.
+ * @buffer_size: size of client-provided buffer. Filled by client.
+ * @set_bootdev: set boot device with download. Filled by client.
+ * @check_buffer_size: check download does not exceed buffer size.
+ * Filled by client.
+ * @hdr_cont_len: content length according to headers. Filled by wget
+ * @headers: buffer for headers. Filled by wget.
+ */
+struct wget_http_info {
+ enum wget_http_method method;
+ u32 status_code;
+ ulong file_size;
+ ulong buffer_size;
+ bool set_bootdev;
+ bool check_buffer_size;
+ u32 hdr_cont_len;
+ char *headers;
+};
+
+extern struct wget_http_info default_wget_info;
+extern struct wget_http_info *wget_info;
+int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info);
+
#endif /* __NET_COMMON_H__ */
diff --git a/include/net-lwip.h b/include/net-lwip.h
index 1c3583f..4d7f938 100644
--- a/include/net-lwip.h
+++ b/include/net-lwip.h
@@ -17,15 +17,6 @@
int net_lwip_rx(struct udevice *udev, struct netif *netif);
/**
- * wget_with_dns() - runs dns host IP address resulution before wget
- *
- * @dst_addr: destination address to download the file
- * @uri: uri string of target file of wget
- * Return: downloaded file size, negative if failed
- */
-
-int wget_with_dns(ulong dst_addr, char *uri);
-/**
* wget_validate_uri() - varidate the uri
*
* @uri: uri string of target file of wget
diff --git a/include/spi.h b/include/spi.h
index 3a92d02..6944773 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -41,12 +41,6 @@
#define SPI_3BYTE_MODE 0x0
#define SPI_4BYTE_MODE 0x1
-/* SPI transfer flags */
-#define SPI_XFER_STRIPE (1 << 6)
-#define SPI_XFER_MASK (3 << 8)
-#define SPI_XFER_LOWER (1 << 8)
-#define SPI_XFER_UPPER (2 << 8)
-
/* Max no. of CS supported per spi device */
#define SPI_CS_CNT_MAX 2
@@ -169,6 +163,8 @@
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
#define SPI_XFER_U_PAGE BIT(4)
#define SPI_XFER_STACKED BIT(5)
+#define SPI_XFER_LOWER BIT(6)
+
/*
* Flag indicating that the spi-controller has multi chip select
* capability and can assert/de-assert more than one chip select
diff --git a/include/sysinfo.h b/include/sysinfo.h
index 8a77ef4..027a463 100644
--- a/include/sysinfo.h
+++ b/include/sysinfo.h
@@ -40,29 +40,29 @@
/** enum sysinfo_id - Standard IDs defined by U-Boot */
enum sysinfo_id {
- SYSINFO_ID_NONE,
+ SYSID_NONE,
/* For SMBIOS tables */
- SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER,
- SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT,
- SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
- SYSINFO_ID_SMBIOS_SYSTEM_SERIAL,
- SYSINFO_ID_SMBIOS_SYSTEM_SKU,
- SYSINFO_ID_SMBIOS_SYSTEM_FAMILY,
- SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER,
- SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT,
- SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
- SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL,
- SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG,
+ SYSID_SM_SYSTEM_MANUFACTURER,
+ SYSID_SM_SYSTEM_PRODUCT,
+ SYSID_SM_SYSTEM_VERSION,
+ SYSID_SM_SYSTEM_SERIAL,
+ SYSID_SM_SYSTEM_SKU,
+ SYSID_SM_SYSTEM_FAMILY,
+ SYSID_SM_BASEBOARD_MANUFACTURER,
+ SYSID_SM_BASEBOARD_PRODUCT,
+ SYSID_SM_BASEBOARD_VERSION,
+ SYSID_SM_BASEBOARD_SERIAL,
+ SYSID_SM_BASEBOARD_ASSET_TAG,
/* For show_board_info() */
- SYSINFO_ID_BOARD_MODEL,
- SYSINFO_ID_BOARD_MANUFACTURER,
- SYSINFO_ID_PRIOR_STAGE_VERSION,
- SYSINFO_ID_PRIOR_STAGE_DATE,
+ SYSID_BOARD_MODEL,
+ SYSID_BOARD_MANUFACTURER,
+ SYSID_PRIOR_STAGE_VERSION,
+ SYSID_PRIOR_STAGE_DATE,
/* First value available for downstream/board used */
- SYSINFO_ID_USER = 0x1000,
+ SYSID_USER = 0x1000,
};
struct sysinfo_ops {
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 066f0ca..58d4978 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -567,6 +567,16 @@
No additional space will be required in the resulting U-Boot binary
when this option is enabled.
+config BOOTEFI_TESTAPP_COMPILE
+ bool "Compile an EFI test app for testing"
+ default y
+ help
+ This compiles an app designed for testing. It is packed into an image
+ by the test.py testing frame in the setup_efi_image() function.
+
+ No additional space will be required in the resulting U-Boot binary
+ when this option is enabled.
+
endif
source "lib/efi/Kconfig"
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 00d1896..87131ab 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -20,6 +20,7 @@
ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
apps-y += dtbdump
endif
+apps-$(CONFIG_BOOTEFI_TESTAPP_COMPILE) += testapp
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-$(CONFIG_EFI_BOOTMGR) += efi_bootmgr.o
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index bf38392..a87006b 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -137,7 +137,6 @@
*/
file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
(uintptr_t)source_buffer,
- (uintptr_t)source_buffer +
source_size);
/*
* Make sure that device for device_path exist
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index f9b5988..8c51a6e 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -11,10 +11,10 @@
#include <blkmap.h>
#include <charset.h>
#include <dm.h>
+#include <efi.h>
#include <log.h>
#include <malloc.h>
#include <net.h>
-#include <efi_default_filename.h>
#include <efi_loader.h>
#include <efi_variable.h>
#include <asm/unaligned.h>
@@ -82,8 +82,12 @@
&efi_simple_file_system_protocol_guid, &rem);
if (handle) {
if (rem->type == DEVICE_PATH_TYPE_END) {
- full_path = efi_dp_from_file(device_path,
- "/EFI/BOOT/" BOOTEFI_NAME);
+ char fname[30];
+
+ snprintf(fname, sizeof(fname), "/EFI/BOOT/%s",
+ efi_get_basename());
+ full_path = efi_dp_from_file(device_path, fname);
+
} else {
full_path = efi_dp_dup(device_path);
}
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index d744458..ee387e1 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -977,7 +977,7 @@
/* Construct a device-path for memory-mapped image */
struct efi_device_path *efi_dp_from_mem(uint32_t memory_type,
uint64_t start_address,
- uint64_t end_address)
+ size_t size)
{
struct efi_device_path_memory *mdp;
void *buf, *start;
@@ -992,7 +992,7 @@
mdp->dp.length = sizeof(*mdp);
mdp->memory_type = memory_type;
mdp->start_address = start_address;
- mdp->end_address = end_address;
+ mdp->end_address = start_address + size;
buf = &mdp[1];
*((struct efi_device_path *)buf) = END;
@@ -1073,8 +1073,7 @@
efi_get_image_parameters(&image_addr, &image_size);
dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
- (uintptr_t)image_addr,
- (uintptr_t)image_addr + image_size);
+ (uintptr_t)image_addr, image_size);
} else if (IS_ENABLED(CONFIG_NETDEVICES) && !strcmp(dev, "Net")) {
dp = efi_dp_from_eth();
} else if (!strcmp(dev, "Uart")) {
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 00167bd..bf96f61 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -12,18 +12,89 @@
#include <mapmem.h>
#include <dm.h>
#include <fs.h>
+#include <efi.h>
#include <efi_api.h>
#include <efi_load_initrd.h>
#include <efi_loader.h>
#include <efi_variable.h>
+#include <host_arch.h>
#include <linux/libfdt.h>
#include <linux/list.h>
+#undef BOOTEFI_NAME
+
+#if HOST_ARCH == HOST_ARCH_X86_64
+#define HOST_BOOTEFI_NAME "BOOTX64.EFI"
+#define HOST_PXE_ARCH 0x6
+#elif HOST_ARCH == HOST_ARCH_X86
+#define HOST_BOOTEFI_NAME "BOOTIA32.EFI"
+#define HOST_PXE_ARCH 0x7
+#elif HOST_ARCH == HOST_ARCH_AARCH64
+#define HOST_BOOTEFI_NAME "BOOTAA64.EFI"
+#define HOST_PXE_ARCH 0xb
+#elif HOST_ARCH == HOST_ARCH_ARM
+#define HOST_BOOTEFI_NAME "BOOTARM.EFI"
+#define HOST_PXE_ARCH 0xa
+#elif HOST_ARCH == HOST_ARCH_RISCV32
+#define HOST_BOOTEFI_NAME "BOOTRISCV32.EFI"
+#define HOST_PXE_ARCH 0x19
+#elif HOST_ARCH == HOST_ARCH_RISCV64
+#define HOST_BOOTEFI_NAME "BOOTRISCV64.EFI"
+#define HOST_PXE_ARCH 0x1b
+#else
+#error Unsupported Host architecture
+#endif
+
+#if defined(CONFIG_SANDBOX)
+#define BOOTEFI_NAME "BOOTSBOX.EFI"
+#elif defined(CONFIG_ARM64)
+#define BOOTEFI_NAME "BOOTAA64.EFI"
+#elif defined(CONFIG_ARM)
+#define BOOTEFI_NAME "BOOTARM.EFI"
+#elif defined(CONFIG_X86_64)
+#define BOOTEFI_NAME "BOOTX64.EFI"
+#elif defined(CONFIG_X86)
+#define BOOTEFI_NAME "BOOTIA32.EFI"
+#elif defined(CONFIG_ARCH_RV32I)
+#define BOOTEFI_NAME "BOOTRISCV32.EFI"
+#elif defined(CONFIG_ARCH_RV64I)
+#define BOOTEFI_NAME "BOOTRISCV64.EFI"
+#else
+#error Unsupported UEFI architecture
+#endif
+
#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI_LOAD_FILE2_INITRD)
/* GUID used by Linux to identify the LoadFile2 protocol with the initrd */
const efi_guid_t efi_lf2_initrd_guid = EFI_INITRD_MEDIA_GUID;
#endif
+const char *efi_get_basename(void)
+{
+ return efi_use_host_arch() ? HOST_BOOTEFI_NAME : BOOTEFI_NAME;
+}
+
+int efi_get_pxe_arch(void)
+{
+ if (efi_use_host_arch())
+ return HOST_PXE_ARCH;
+
+ /* http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml */
+ if (IS_ENABLED(CONFIG_ARM64))
+ return 0xb;
+ else if (IS_ENABLED(CONFIG_ARM))
+ return 0xa;
+ else if (IS_ENABLED(CONFIG_X86_64))
+ return 0x6;
+ else if (IS_ENABLED(CONFIG_X86))
+ return 0x7;
+ else if (IS_ENABLED(CONFIG_ARCH_RV32I))
+ return 0x19;
+ else if (IS_ENABLED(CONFIG_ARCH_RV64I))
+ return 0x1b;
+
+ return -EINVAL;
+}
+
/**
* efi_create_current_boot_var() - Return Boot#### name were #### is replaced by
* the value of BootCurrent
diff --git a/lib/efi_loader/testapp.c b/lib/efi_loader/testapp.c
new file mode 100644
index 0000000..804ca7e
--- /dev/null
+++ b/lib/efi_loader/testapp.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * EFI test application
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * This test program is used to test the invocation of an EFI application.
+ * It writes a few messages to the console and then exits boot services
+ */
+
+#include <efi_api.h>
+
+static const efi_guid_t loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;
+
+static struct efi_system_table *systable;
+static struct efi_boot_services *boottime;
+static struct efi_simple_text_output_protocol *con_out;
+
+/**
+ * efi_main() - entry point of the EFI application.
+ *
+ * @handle: handle of the loaded image
+ * @systab: system table
+ * Return: status code
+ */
+efi_status_t EFIAPI efi_main(efi_handle_t handle,
+ struct efi_system_table *systab)
+{
+ struct efi_loaded_image *loaded_image;
+ efi_status_t ret;
+
+ systable = systab;
+ boottime = systable->boottime;
+ con_out = systable->con_out;
+
+ /* Get the loaded image protocol */
+ ret = boottime->open_protocol(handle, &loaded_image_guid,
+ (void **)&loaded_image, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ con_out->output_string
+ (con_out, u"Cannot open loaded image protocol\r\n");
+ goto out;
+ }
+
+ /* UEFI requires CR LF */
+ con_out->output_string(con_out, u"U-Boot test app for EFI_LOADER\r\n");
+
+out:
+ con_out->output_string(con_out, u"Exiting test app\n");
+ ret = boottime->exit(handle, ret, 0, NULL);
+
+ /* We should never arrive here */
+ return ret;
+}
diff --git a/lib/lmb.c b/lib/lmb.c
index 2ed0da2..74ffa9f 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -27,96 +27,11 @@
#define MAP_OP_FREE (u8)0x2
#define MAP_OP_ADD (u8)0x3
-static struct lmb lmb;
-
-static bool lmb_should_notify(enum lmb_flags flags)
-{
- return !lmb.test && !(flags & LMB_NONOTIFY) &&
- CONFIG_IS_ENABLED(EFI_LOADER);
-}
-
-static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op,
- enum lmb_flags flags)
-{
- u64 efi_addr;
- u64 pages;
- efi_status_t status;
-
- if (op != MAP_OP_RESERVE && op != MAP_OP_FREE && op != MAP_OP_ADD) {
- log_err("Invalid map update op received (%d)\n", op);
- return -1;
- }
-
- if (!lmb_should_notify(flags))
- return 0;
-
- efi_addr = (uintptr_t)map_sysmem(addr, 0);
- pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
- efi_addr &= ~EFI_PAGE_MASK;
-
- status = efi_add_memory_map_pg(efi_addr, pages,
- op == MAP_OP_RESERVE ?
- EFI_BOOT_SERVICES_DATA :
- EFI_CONVENTIONAL_MEMORY,
- false);
- if (status != EFI_SUCCESS) {
- log_err("%s: LMB Map notify failure %lu\n", __func__,
- status & ~EFI_ERROR_MASK);
- return -1;
- }
- unmap_sysmem((void *)(uintptr_t)efi_addr);
-
- return 0;
-}
-
-static void lmb_print_region_flags(enum lmb_flags flags)
-{
- u64 bitpos;
- const char *flag_str[] = { "none", "no-map", "no-overwrite", "no-notify" };
-
- do {
- bitpos = flags ? fls(flags) - 1 : 0;
- assert_noisy(bitpos < ARRAY_SIZE(flag_str));
- printf("%s", flag_str[bitpos]);
- flags &= ~(1ull << bitpos);
- puts(flags ? ", " : "\n");
- } while (flags);
-}
-
-static void lmb_dump_region(struct alist *lmb_rgn_lst, char *name)
-{
- struct lmb_region *rgn = lmb_rgn_lst->data;
- unsigned long long base, size, end;
- enum lmb_flags flags;
- int i;
-
- printf(" %s.count = 0x%x\n", name, lmb_rgn_lst->count);
-
- for (i = 0; i < lmb_rgn_lst->count; i++) {
- base = rgn[i].base;
- size = rgn[i].size;
- end = base + size - 1;
- flags = rgn[i].flags;
-
- printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ",
- name, i, base, end, size);
- lmb_print_region_flags(flags);
- }
-}
-
-void lmb_dump_all_force(void)
-{
- printf("lmb_dump_all:\n");
- lmb_dump_region(&lmb.free_mem, "memory");
- lmb_dump_region(&lmb.used_mem, "reserved");
-}
-
-void lmb_dump_all(void)
-{
-#ifdef DEBUG
- lmb_dump_all_force();
-#endif
-}
+/*
+ * The following low level LMB functions must not access the global LMB memory
+ * map since they are also used to manage IOVA memory maps in iommu drivers like
+ * apple_dart.
+ */
static long lmb_addrs_overlap(phys_addr_t base1, phys_size_t size1,
phys_addr_t base2, phys_size_t size2)
@@ -205,117 +120,6 @@
lmb_remove_region(lmb_rgn_lst, r2);
}
-static void lmb_reserve_uboot_region(void)
-{
- int bank;
- ulong end, bank_end;
- phys_addr_t rsv_start;
-
- rsv_start = gd->start_addr_sp - CONFIG_STACK_SIZE;
- end = gd->ram_top;
-
- /*
- * Reserve memory from aligned address below the bottom of U-Boot stack
- * until end of RAM area to prevent LMB from overwriting that memory.
- */
- debug("## Current stack ends at 0x%08lx ", (ulong)rsv_start);
-
- /* adjust sp by 16K to be safe */
- rsv_start -= SZ_16K;
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (!gd->bd->bi_dram[bank].size ||
- rsv_start < gd->bd->bi_dram[bank].start)
- continue;
- /* Watch out for RAM at end of address space! */
- bank_end = gd->bd->bi_dram[bank].start +
- gd->bd->bi_dram[bank].size - 1;
- if (rsv_start > bank_end)
- continue;
- if (bank_end > end)
- bank_end = end - 1;
-
- lmb_reserve_flags(rsv_start, bank_end - rsv_start + 1,
- LMB_NOOVERWRITE);
-
- if (gd->flags & GD_FLG_SKIP_RELOC)
- lmb_reserve_flags((phys_addr_t)(uintptr_t)_start,
- gd->mon_len, LMB_NOOVERWRITE);
-
- break;
- }
-}
-
-static void lmb_reserve_common(void *fdt_blob)
-{
- lmb_reserve_uboot_region();
-
- if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob)
- boot_fdt_add_mem_rsv_regions(fdt_blob);
-}
-
-static __maybe_unused void lmb_reserve_common_spl(void)
-{
- phys_addr_t rsv_start;
- phys_size_t rsv_size;
-
- /*
- * Assume a SPL stack of 16KB. This must be
- * more than enough for the SPL stage.
- */
- if (IS_ENABLED(CONFIG_SPL_STACK_R_ADDR)) {
- rsv_start = gd->start_addr_sp - 16384;
- rsv_size = 16384;
- lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE);
- }
-
- if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) {
- /* Reserve the bss region */
- rsv_start = (phys_addr_t)(uintptr_t)__bss_start;
- rsv_size = (phys_addr_t)(uintptr_t)__bss_end -
- (phys_addr_t)(uintptr_t)__bss_start;
- lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE);
- }
-}
-
-/**
- * lmb_add_memory() - Add memory range for LMB allocations
- *
- * Add the entire available memory range to the pool of memory that
- * can be used by the LMB module for allocations.
- *
- * Return: None
- */
-void lmb_add_memory(void)
-{
- int i;
- phys_size_t size;
- u64 ram_top = gd->ram_top;
- struct bd_info *bd = gd->bd;
-
- if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP))
- return lmb_arch_add_memory();
-
- /* Assume a 4GB ram_top if not defined */
- if (!ram_top)
- ram_top = 0x100000000ULL;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- size = bd->bi_dram[i].size;
- if (size) {
- lmb_add(bd->bi_dram[i].start, size);
-
- /*
- * Reserve memory above ram_top as
- * no-overwrite so that it cannot be
- * allocated
- */
- if (bd->bi_dram[i].start >= ram_top)
- lmb_reserve_flags(bd->bi_dram[i].start, size,
- LMB_NOOVERWRITE);
- }
- }
-}
-
static long lmb_resize_regions(struct alist *lmb_rgn_lst,
unsigned long idx_start,
phys_addr_t base, phys_size_t size)
@@ -475,29 +279,10 @@
return 0;
}
-static long lmb_add_region(struct alist *lmb_rgn_lst, phys_addr_t base,
- phys_size_t size)
-{
- return lmb_add_region_flags(lmb_rgn_lst, base, size, LMB_NONE);
-}
-
-/* This routine may be called with relocation disabled. */
-long lmb_add(phys_addr_t base, phys_size_t size)
-{
- long ret;
- struct alist *lmb_rgn_lst = &lmb.free_mem;
-
- ret = lmb_add_region(lmb_rgn_lst, base, size);
- if (ret)
- return ret;
-
- return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE);
-}
-
-static long _lmb_free(phys_addr_t base, phys_size_t size)
+static long _lmb_free(struct alist *lmb_rgn_lst, phys_addr_t base,
+ phys_size_t size)
{
struct lmb_region *rgn;
- struct alist *lmb_rgn_lst = &lmb.used_mem;
phys_addr_t rgnbegin, rgnend;
phys_addr_t end = base + size - 1;
int i;
@@ -545,69 +330,374 @@
rgn[i].flags);
}
-/**
- * lmb_free_flags() - Free up a region of memory
- * @base: Base Address of region to be freed
- * @size: Size of the region to be freed
- * @flags: Memory region attributes
- *
- * Free up a region of memory.
- *
- * Return: 0 if successful, -1 on failure
- */
-long lmb_free_flags(phys_addr_t base, phys_size_t size,
- uint flags)
+static long lmb_overlaps_region(struct alist *lmb_rgn_lst, phys_addr_t base,
+ phys_size_t size)
{
- long ret;
+ unsigned long i;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
- ret = _lmb_free(base, size);
- if (ret < 0)
- return ret;
+ for (i = 0; i < lmb_rgn_lst->count; i++) {
+ phys_addr_t rgnbase = rgn[i].base;
+ phys_size_t rgnsize = rgn[i].size;
+ if (lmb_addrs_overlap(base, size, rgnbase, rgnsize))
+ break;
+ }
- return lmb_map_update_notify(base, size, MAP_OP_FREE, flags);
+ return (i < lmb_rgn_lst->count) ? i : -1;
}
-long lmb_free(phys_addr_t base, phys_size_t size)
+static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size)
{
- return lmb_free_flags(base, size, LMB_NONE);
+ return addr & ~(size - 1);
}
-long lmb_reserve_flags(phys_addr_t base, phys_size_t size, enum lmb_flags flags)
+/*
+ * IOVA LMB memory maps using lmb pointers instead of the global LMB memory map.
+ */
+
+int io_lmb_setup(struct lmb *io_lmb)
{
- long ret = 0;
- struct alist *lmb_rgn_lst = &lmb.used_mem;
+ int ret;
- ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags);
- if (ret)
- return ret;
+ ret = alist_init(&io_lmb->free_mem, sizeof(struct lmb_region),
+ (uint)LMB_ALIST_INITIAL_SIZE);
+ if (!ret) {
+ log_debug("Unable to initialise the list for LMB free IOVA\n");
+ return -ENOMEM;
+ }
- return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags);
+ ret = alist_init(&io_lmb->used_mem, sizeof(struct lmb_region),
+ (uint)LMB_ALIST_INITIAL_SIZE);
+ if (!ret) {
+ log_debug("Unable to initialise the list for LMB used IOVA\n");
+ return -ENOMEM;
+ }
+
+ io_lmb->test = false;
+
+ return 0;
}
-long lmb_reserve(phys_addr_t base, phys_size_t size)
+void io_lmb_teardown(struct lmb *io_lmb)
{
- return lmb_reserve_flags(base, size, LMB_NONE);
+ alist_uninit(&io_lmb->free_mem);
+ alist_uninit(&io_lmb->used_mem);
}
-static long lmb_overlaps_region(struct alist *lmb_rgn_lst, phys_addr_t base,
- phys_size_t size)
+long io_lmb_add(struct lmb *io_lmb, phys_addr_t base, phys_size_t size)
{
- unsigned long i;
+ return lmb_add_region_flags(&io_lmb->free_mem, base, size, LMB_NONE);
+}
+
+/* derived and simplified from _lmb_alloc_base() */
+phys_addr_t io_lmb_alloc(struct lmb *io_lmb, phys_size_t size, ulong align)
+{
+ long i, rgn;
+ phys_addr_t base = 0;
+ phys_addr_t res_base;
+ struct lmb_region *lmb_used = io_lmb->used_mem.data;
+ struct lmb_region *lmb_memory = io_lmb->free_mem.data;
+
+ for (i = io_lmb->free_mem.count - 1; i >= 0; i--) {
+ phys_addr_t lmbbase = lmb_memory[i].base;
+ phys_size_t lmbsize = lmb_memory[i].size;
+
+ if (lmbsize < size)
+ continue;
+ base = lmb_align_down(lmbbase + lmbsize - size, align);
+
+ while (base && lmbbase <= base) {
+ rgn = lmb_overlaps_region(&io_lmb->used_mem, base, size);
+ if (rgn < 0) {
+ /* This area isn't reserved, take it */
+ if (lmb_add_region_flags(&io_lmb->used_mem, base,
+ size, LMB_NONE) < 0)
+ return 0;
+
+ return base;
+ }
+
+ res_base = lmb_used[rgn].base;
+ if (res_base < size)
+ break;
+ base = lmb_align_down(res_base - size, align);
+ }
+ }
+ return 0;
+}
+
+long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size)
+{
+ return _lmb_free(&io_lmb->used_mem, base, size);
+}
+
+/*
+ * Low level LMB functions are used to manage IOVA memory maps for the Apple
+ * dart iommu. They must not access the global LMB memory map.
+ * So keep the global LMB variable declaration unreachable from them.
+ */
+
+static struct lmb lmb;
+
+static bool lmb_should_notify(enum lmb_flags flags)
+{
+ return !lmb.test && !(flags & LMB_NONOTIFY) &&
+ CONFIG_IS_ENABLED(EFI_LOADER);
+}
+
+static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op,
+ enum lmb_flags flags)
+{
+ u64 efi_addr;
+ u64 pages;
+ efi_status_t status;
+
+ if (op != MAP_OP_RESERVE && op != MAP_OP_FREE && op != MAP_OP_ADD) {
+ log_err("Invalid map update op received (%d)\n", op);
+ return -1;
+ }
+
+ if (!lmb_should_notify(flags))
+ return 0;
+
+ efi_addr = (uintptr_t)map_sysmem(addr, 0);
+ pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
+ efi_addr &= ~EFI_PAGE_MASK;
+
+ status = efi_add_memory_map_pg(efi_addr, pages,
+ op == MAP_OP_RESERVE ?
+ EFI_BOOT_SERVICES_DATA :
+ EFI_CONVENTIONAL_MEMORY,
+ false);
+ if (status != EFI_SUCCESS) {
+ log_err("%s: LMB Map notify failure %lu\n", __func__,
+ status & ~EFI_ERROR_MASK);
+ return -1;
+ }
+ unmap_sysmem((void *)(uintptr_t)efi_addr);
+
+ return 0;
+}
+
+static void lmb_print_region_flags(enum lmb_flags flags)
+{
+ u64 bitpos;
+ const char *flag_str[] = { "none", "no-map", "no-overwrite", "no-notify" };
+
+ do {
+ bitpos = flags ? fls(flags) - 1 : 0;
+ assert_noisy(bitpos < ARRAY_SIZE(flag_str));
+ printf("%s", flag_str[bitpos]);
+ flags &= ~(1ull << bitpos);
+ puts(flags ? ", " : "\n");
+ } while (flags);
+}
+
+static void lmb_dump_region(struct alist *lmb_rgn_lst, char *name)
+{
struct lmb_region *rgn = lmb_rgn_lst->data;
+ unsigned long long base, size, end;
+ enum lmb_flags flags;
+ int i;
+
+ printf(" %s.count = 0x%x\n", name, lmb_rgn_lst->count);
for (i = 0; i < lmb_rgn_lst->count; i++) {
- phys_addr_t rgnbase = rgn[i].base;
- phys_size_t rgnsize = rgn[i].size;
- if (lmb_addrs_overlap(base, size, rgnbase, rgnsize))
- break;
+ base = rgn[i].base;
+ size = rgn[i].size;
+ end = base + size - 1;
+ flags = rgn[i].flags;
+
+ printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ",
+ name, i, base, end, size);
+ lmb_print_region_flags(flags);
}
+}
- return (i < lmb_rgn_lst->count) ? i : -1;
+void lmb_dump_all_force(void)
+{
+ printf("lmb_dump_all:\n");
+ lmb_dump_region(&lmb.free_mem, "memory");
+ lmb_dump_region(&lmb.used_mem, "reserved");
}
-static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size)
+void lmb_dump_all(void)
{
- return addr & ~(size - 1);
+#ifdef DEBUG
+ lmb_dump_all_force();
+#endif
+}
+
+static void lmb_reserve_uboot_region(void)
+{
+ int bank;
+ ulong end, bank_end;
+ phys_addr_t rsv_start;
+
+ rsv_start = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ end = gd->ram_top;
+
+ /*
+ * Reserve memory from aligned address below the bottom of U-Boot stack
+ * until end of RAM area to prevent LMB from overwriting that memory.
+ */
+ debug("## Current stack ends at 0x%08lx ", (ulong)rsv_start);
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (!gd->bd->bi_dram[bank].size ||
+ rsv_start < gd->bd->bi_dram[bank].start)
+ continue;
+ /* Watch out for RAM at end of address space! */
+ bank_end = gd->bd->bi_dram[bank].start +
+ gd->bd->bi_dram[bank].size - 1;
+ if (rsv_start > bank_end)
+ continue;
+ if (bank_end > end)
+ bank_end = end - 1;
+
+ lmb_reserve_flags(rsv_start, bank_end - rsv_start + 1,
+ LMB_NOOVERWRITE);
+
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ lmb_reserve_flags((phys_addr_t)(uintptr_t)_start,
+ gd->mon_len, LMB_NOOVERWRITE);
+
+ break;
+ }
+}
+
+static void lmb_reserve_common(void *fdt_blob)
+{
+ lmb_reserve_uboot_region();
+
+ if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob)
+ boot_fdt_add_mem_rsv_regions(fdt_blob);
+}
+
+static __maybe_unused void lmb_reserve_common_spl(void)
+{
+ phys_addr_t rsv_start;
+ phys_size_t rsv_size;
+
+ /*
+ * Assume a SPL stack of 16KB. This must be
+ * more than enough for the SPL stage.
+ */
+ if (IS_ENABLED(CONFIG_SPL_STACK_R_ADDR)) {
+ rsv_start = gd->start_addr_sp - 16384;
+ rsv_size = 16384;
+ lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) {
+ /* Reserve the bss region */
+ rsv_start = (phys_addr_t)(uintptr_t)__bss_start;
+ rsv_size = (phys_addr_t)(uintptr_t)__bss_end -
+ (phys_addr_t)(uintptr_t)__bss_start;
+ lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE);
+ }
+}
+
+/**
+ * lmb_add_memory() - Add memory range for LMB allocations
+ *
+ * Add the entire available memory range to the pool of memory that
+ * can be used by the LMB module for allocations.
+ *
+ * Return: None
+ */
+void lmb_add_memory(void)
+{
+ int i;
+ phys_size_t size;
+ u64 ram_top = gd->ram_top;
+ struct bd_info *bd = gd->bd;
+
+ if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP))
+ return lmb_arch_add_memory();
+
+ /* Assume a 4GB ram_top if not defined */
+ if (!ram_top)
+ ram_top = 0x100000000ULL;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ size = bd->bi_dram[i].size;
+ if (size) {
+ lmb_add(bd->bi_dram[i].start, size);
+
+ /*
+ * Reserve memory above ram_top as
+ * no-overwrite so that it cannot be
+ * allocated
+ */
+ if (bd->bi_dram[i].start >= ram_top)
+ lmb_reserve_flags(bd->bi_dram[i].start, size,
+ LMB_NOOVERWRITE);
+ }
+ }
+}
+
+static long lmb_add_region(struct alist *lmb_rgn_lst, phys_addr_t base,
+ phys_size_t size)
+{
+ return lmb_add_region_flags(lmb_rgn_lst, base, size, LMB_NONE);
+}
+
+/* This routine may be called with relocation disabled. */
+long lmb_add(phys_addr_t base, phys_size_t size)
+{
+ long ret;
+ struct alist *lmb_rgn_lst = &lmb.free_mem;
+
+ ret = lmb_add_region(lmb_rgn_lst, base, size);
+ if (ret)
+ return ret;
+
+ return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE);
+}
+
+/**
+ * lmb_free_flags() - Free up a region of memory
+ * @base: Base Address of region to be freed
+ * @size: Size of the region to be freed
+ * @flags: Memory region attributes
+ *
+ * Free up a region of memory.
+ *
+ * Return: 0 if successful, -1 on failure
+ */
+long lmb_free_flags(phys_addr_t base, phys_size_t size,
+ uint flags)
+{
+ long ret;
+
+ ret = _lmb_free(&lmb.used_mem, base, size);
+ if (ret < 0)
+ return ret;
+
+ return lmb_map_update_notify(base, size, MAP_OP_FREE, flags);
+}
+
+long lmb_free(phys_addr_t base, phys_size_t size)
+{
+ return lmb_free_flags(base, size, LMB_NONE);
+}
+
+long lmb_reserve_flags(phys_addr_t base, phys_size_t size, enum lmb_flags flags)
+{
+ long ret = 0;
+ struct alist *lmb_rgn_lst = &lmb.used_mem;
+
+ ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags);
+ if (ret)
+ return ret;
+
+ return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags);
+}
+
+long lmb_reserve(phys_addr_t base, phys_size_t size)
+{
+ return lmb_reserve_flags(base, size, LMB_NONE);
}
static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align,
diff --git a/lib/net_utils.c b/lib/net_utils.c
index c70fef0..621f651 100644
--- a/lib/net_utils.c
+++ b/lib/net_utils.c
@@ -152,6 +152,17 @@
}
#endif
+void ip_to_string(struct in_addr x, char *s)
+{
+ x.s_addr = ntohl(x.s_addr);
+ sprintf(s, "%d.%d.%d.%d",
+ (int) ((x.s_addr >> 24) & 0xff),
+ (int) ((x.s_addr >> 16) & 0xff),
+ (int) ((x.s_addr >> 8) & 0xff),
+ (int) ((x.s_addr >> 0) & 0xff)
+ );
+}
+
void string_to_enetaddr(const char *addr, uint8_t *enetaddr)
{
char *end;
diff --git a/lib/smbios.c b/lib/smbios.c
index 7c24ea1..a36d4b4 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -270,7 +270,7 @@
static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop,
const char *dval)
{
- return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE, dval);
+ return smbios_add_prop_si(ctx, prop, SYSID_NONE, dval);
}
static void smbios_set_eos(struct smbios_ctx *ctx, char *eos)
@@ -393,27 +393,27 @@
fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
t->manufacturer = smbios_add_prop_si(ctx, "manufacturer",
- SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER,
+ SYSID_SM_SYSTEM_MANUFACTURER,
NULL);
t->product_name = smbios_add_prop_si(ctx, "product",
- SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT,
+ SYSID_SM_SYSTEM_PRODUCT,
NULL);
t->version = smbios_add_prop_si(ctx, "version",
- SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
+ SYSID_SM_SYSTEM_VERSION,
NULL);
if (serial_str) {
t->serial_number = smbios_add_prop(ctx, NULL, serial_str);
strncpy((char *)t->uuid, serial_str, sizeof(t->uuid));
} else {
t->serial_number = smbios_add_prop_si(ctx, "serial",
- SYSINFO_ID_SMBIOS_SYSTEM_SERIAL,
+ SYSID_SM_SYSTEM_SERIAL,
NULL);
}
t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN;
t->sku_number = smbios_add_prop_si(ctx, "sku",
- SYSINFO_ID_SMBIOS_SYSTEM_SKU, NULL);
+ SYSID_SM_SYSTEM_SKU, NULL);
t->family = smbios_add_prop_si(ctx, "family",
- SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, NULL);
+ SYSID_SM_SYSTEM_FAMILY, NULL);
len = t->length + smbios_string_table_len(ctx);
*current += len;
@@ -433,20 +433,20 @@
fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
t->manufacturer = smbios_add_prop_si(ctx, "manufacturer",
- SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER,
+ SYSID_SM_BASEBOARD_MANUFACTURER,
NULL);
t->product_name = smbios_add_prop_si(ctx, "product",
- SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT,
+ SYSID_SM_BASEBOARD_PRODUCT,
NULL);
t->version = smbios_add_prop_si(ctx, "version",
- SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
+ SYSID_SM_BASEBOARD_VERSION,
NULL);
t->serial_number = smbios_add_prop_si(ctx, "serial",
- SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL,
+ SYSID_SM_BASEBOARD_SERIAL,
NULL);
t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag",
- SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG,
+ SYSID_SM_BASEBOARD_ASSET_TAG,
NULL);
t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
t->board_type = SMBIOS_BOARD_MOTHERBOARD;
diff --git a/net/Kconfig b/net/Kconfig
index 76ab7d9..b4bb68d 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -244,6 +244,15 @@
generated. It will be saved to the appropriate environment variable,
too.
+config WGET
+ bool "Enable wget"
+ select PROT_TCP if NET
+ select PROT_TCP_LWIP if NET_LWIP
+ select PROT_DNS_LWIP if NET_LWIP
+ help
+ Selecting this will enable wget, an interface to send HTTP requests
+ via the network stack.
+
config TFTP_BLOCKSIZE
int "TFTP block size"
default 1468
diff --git a/net/Makefile b/net/Makefile
index 209377a..7c917b3 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -29,7 +29,7 @@
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_PROT_UDP) += udp.o
obj-$(CONFIG_PROT_TCP) += tcp.o
-obj-$(CONFIG_CMD_WGET) += wget.o
+obj-$(CONFIG_WGET) += wget.o
# Disable this warning as it is triggered by:
# sprintf(buf, index ? "foo%d" : "foo", index)
diff --git a/net/lwip/Makefile b/net/lwip/Makefile
index f2558f8..79dd6b3 100644
--- a/net/lwip/Makefile
+++ b/net/lwip/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_CMD_DNS) += dns.o
obj-$(CONFIG_CMD_PING) += ping.o
obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
-obj-$(CONFIG_CMD_WGET) += wget.o
+obj-$(CONFIG_WGET) += wget.o
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
index b495ebd..53c3b16 100644
--- a/net/lwip/wget.c
+++ b/net/lwip/wget.c
@@ -23,6 +23,8 @@
};
struct wget_ctx {
+ char server_name[SERVER_NAME_SIZE];
+ u16 port;
char *path;
ulong daddr;
ulong saved_daddr;
@@ -32,6 +34,18 @@
enum done_state done;
};
+static void wget_lwip_fill_info(struct pbuf *hdr, u16_t hdr_len, u32_t hdr_cont_len)
+{
+ if (wget_info->headers && hdr_len < MAX_HTTP_HEADERS_SIZE)
+ pbuf_copy_partial(hdr, (void *)wget_info->headers, hdr_len, 0);
+ wget_info->hdr_cont_len = (u32)hdr_cont_len;
+}
+
+static void wget_lwip_set_file_size(u32_t rx_content_len)
+{
+ wget_info->file_size = (ulong)rx_content_len;
+}
+
static int parse_url(char *url, char *host, u16 *port, char **path)
{
char *p, *pp;
@@ -176,6 +190,13 @@
struct wget_ctx *ctx = arg;
ulong elapsed;
+ wget_info->status_code = (u32)srv_res;
+
+ if (err == ERR_BUF) {
+ ctx->done = FAILURE;
+ return;
+ }
+
if (httpc_result != HTTPC_RESULT_OK) {
log_err("\nHTTP client error %d\n", httpc_result);
ctx->done = FAILURE;
@@ -195,8 +216,11 @@
printf("%u bytes transferred in %lu ms (", rx_content_len, elapsed);
print_size(rx_content_len / elapsed * 1000, "/s)\n");
printf("Bytes transferred = %lu (%lx hex)\n", ctx->size, ctx->size);
- efi_set_bootdev("Net", "", ctx->path, map_sysmem(ctx->saved_daddr, 0),
- rx_content_len);
+ if (wget_info->set_bootdev) {
+ efi_set_bootdev("Net", "", ctx->path, map_sysmem(ctx->saved_daddr, 0),
+ rx_content_len);
+ }
+ wget_lwip_set_file_size(rx_content_len);
if (env_set_hex("filesize", rx_content_len) ||
env_set_hex("fileaddr", ctx->saved_daddr)) {
log_err("Could not set filesize or fileaddr\n");
@@ -207,15 +231,24 @@
ctx->done = SUCCESS;
}
+static err_t httpc_headers_done_cb(httpc_state_t *connection, void *arg, struct pbuf *hdr,
+ u16_t hdr_len, u32_t content_len)
+{
+ wget_lwip_fill_info(hdr, hdr_len, content_len);
+
+ if (wget_info->check_buffer_size && (ulong)content_len > wget_info->buffer_size)
+ return ERR_BUF;
+
+ return ERR_OK;
+}
+
static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri)
{
- char server_name[SERVER_NAME_SIZE];
httpc_connection_t conn;
httpc_state_t *state;
struct netif *netif;
struct wget_ctx ctx;
char *path;
- u16 port;
ctx.daddr = dst_addr;
ctx.saved_daddr = dst_addr;
@@ -224,7 +257,7 @@
ctx.prevsize = 0;
ctx.start_time = 0;
- if (parse_url(uri, server_name, &port, &path))
+ if (parse_url(uri, ctx.server_name, &ctx.port, &path))
return CMD_RET_USAGE;
netif = net_lwip_new_netif(udev);
@@ -233,8 +266,9 @@
memset(&conn, 0, sizeof(conn));
conn.result_fn = httpc_result_cb;
+ conn.headers_done_fn = httpc_headers_done_cb;
ctx.path = path;
- if (httpc_get_file_dns(server_name, port, path, &conn, httpc_recv_cb,
+ if (httpc_get_file_dns(ctx.server_name, ctx.port, path, &conn, httpc_recv_cb,
&ctx, &state)) {
net_lwip_remove_netif(netif);
return CMD_RET_FAILURE;
@@ -259,6 +293,9 @@
{
eth_set_current();
+ if (!wget_info)
+ wget_info = &default_wget_info;
+
return wget_loop(eth_get_dev(), dst_addr, uri);
}
@@ -285,6 +322,7 @@
if (parse_legacy_arg(url, nurl, sizeof(nurl)))
return CMD_RET_FAILURE;
+ wget_info = &default_wget_info;
if (wget_with_dns(dst_addr, nurl))
return CMD_RET_FAILURE;
diff --git a/net/net-common.c b/net/net-common.c
index a7f767d..45288fe 100644
--- a/net/net-common.c
+++ b/net/net-common.c
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
+#include <net-common.h>
void copy_filename(char *dst, const char *src, int size)
{
@@ -11,3 +12,16 @@
*dst++ = *src++;
*dst = '\0';
}
+
+struct wget_http_info default_wget_info = {
+ .method = WGET_HTTP_METHOD_GET,
+ .set_bootdev = true,
+};
+
+struct wget_http_info *wget_info;
+
+int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info)
+{
+ wget_info = info ? info : &default_wget_info;
+ return wget_with_dns(dst_addr, uri);
+}
diff --git a/net/net.c b/net/net.c
index f47e9fb..ca35704 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1723,17 +1723,6 @@
return 1;
}
-void ip_to_string(struct in_addr x, char *s)
-{
- x.s_addr = ntohl(x.s_addr);
- sprintf(s, "%d.%d.%d.%d",
- (int) ((x.s_addr >> 24) & 0xff),
- (int) ((x.s_addr >> 16) & 0xff),
- (int) ((x.s_addr >> 8) & 0xff),
- (int) ((x.s_addr >> 0) & 0xff)
- );
-}
-
void vlan_to_string(ushort x, char *s)
{
x = ntohs(x);
diff --git a/net/wget.c b/net/wget.c
index 635f82e..3bc2522 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -22,10 +22,10 @@
/* The default, change with environment variable 'httpdstp' */
#define SERVER_PORT 80
-static const char bootfile1[] = "GET ";
+static const char bootfileGET[] = "GET ";
+static const char bootfileHEAD[] = "HEAD ";
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
static const char http_eom[] = "\r\n\r\n";
-static const char http_ok[] = "200";
static const char content_len[] = "Content-Length";
static const char linefeed[] = "\r\n";
static struct in_addr web_server_ip;
@@ -77,7 +77,7 @@
ulong newsize = offset + len;
uchar *ptr;
- if (CONFIG_IS_ENABLED(LMB)) {
+ if (CONFIG_IS_ENABLED(LMB) && wget_info->set_bootdev) {
if (store_addr < image_load_addr ||
lmb_read_check(store_addr, len)) {
printf("\nwget error: ");
@@ -132,8 +132,17 @@
IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2;
offset = ptr;
- memcpy(offset, &bootfile1, strlen(bootfile1));
- offset += strlen(bootfile1);
+ switch (wget_info->method) {
+ case WGET_HTTP_METHOD_HEAD:
+ memcpy(offset, &bootfileHEAD, strlen(bootfileHEAD));
+ offset += strlen(bootfileHEAD);
+ break;
+ case WGET_HTTP_METHOD_GET:
+ default:
+ memcpy(offset, &bootfileGET, strlen(bootfileGET));
+ offset += strlen(bootfileGET);
+ break;
+ }
memcpy(offset, image_url, strlen(image_url));
offset += strlen(image_url);
@@ -193,6 +202,47 @@
#define PKT_QUEUE_OFFSET 0x20000
#define PKT_QUEUE_PACKET_SIZE 0x800
+static void wget_fill_info(const uchar *pkt, int hlen)
+{
+ const char *first_space;
+ const char *second_space;
+ char *pos, *end;
+
+ if (wget_info->headers && hlen < MAX_HTTP_HEADERS_SIZE)
+ strncpy(wget_info->headers, pkt, hlen);
+
+ //Get status code
+ first_space = strchr(pkt, ' ');
+ if (!first_space) {
+ wget_info->status_code = -1;
+ return;
+ }
+
+ second_space = strchr(first_space + 1, ' ');
+ if (!second_space) {
+ wget_info->status_code = -1;
+ return;
+ }
+
+ wget_info->status_code = (u32)simple_strtoul(first_space + 1, &end, 10);
+
+ if (second_space != end)
+ wget_info->status_code = -1;
+
+ pos = strstr((char *)pkt, content_len);
+
+ if (pos) {
+ pos += sizeof(content_len) + 1;
+ while (*pos == ' ')
+ pos++;
+ content_length = simple_strtoul(pos, &end, 10);
+ debug_cond(DEBUG_WGET,
+ "wget: Connected Len %lu\n",
+ content_length);
+ wget_info->hdr_cont_len = content_length;
+ }
+}
+
static void wget_connected(uchar *pkt, unsigned int tcp_seq_num,
u8 action, unsigned int tcp_ack_num, unsigned int len)
{
@@ -241,7 +291,11 @@
initial_data_seq_num = tcp_seq_num + hlen;
next_data_seq_num = tcp_seq_num + len;
+ wget_fill_info(pkt, hlen);
+ debug_cond(DEBUG_WGET,
+ "wget: HTTP Status Code %d\n", wget_info->status_code);
+
- if (strstr((char *)pkt, http_ok) == 0) {
+ if (wget_info->status_code != 200) {
debug_cond(DEBUG_WGET,
"wget: Connected Bad Xfer\n");
wget_loop_state = NETLOOP_FAIL;
@@ -251,17 +305,6 @@
"wget: Connected Pkt %p hlen %x\n",
pkt, hlen);
- pos = strstr((char *)pkt, content_len);
- if (!pos) {
- content_length = -1;
- } else {
- pos += sizeof(content_len) + 2;
- strict_strtoul(pos, 10, &content_length);
- debug_cond(DEBUG_WGET,
- "wget: Connected Len %lu\n",
- content_length);
- }
-
net_boot_file_size = 0;
if (len > hlen) {
@@ -397,10 +440,13 @@
case WGET_TRANSFERRED:
printf("Packets received %d, Transfer Successful\n", packets);
net_set_state(wget_loop_state);
- efi_set_bootdev("Net", "", image_url,
- map_sysmem(image_load_addr, 0),
- net_boot_file_size);
- env_set_hex("filesize", net_boot_file_size);
+ wget_info->file_size = net_boot_file_size;
+ if (wget_info->method == WGET_HTTP_METHOD_GET && wget_info->set_bootdev) {
+ efi_set_bootdev("Net", "", image_url,
+ map_sysmem(image_load_addr, 0),
+ net_boot_file_size);
+ env_set_hex("filesize", net_boot_file_size);
+ }
break;
}
}
@@ -425,6 +471,9 @@
void wget_start(void)
{
+ if (!wget_info)
+ wget_info = &default_wget_info;
+
image_url = strchr(net_boot_file_name, ':');
if (image_url > 0) {
web_server_ip = string_to_ip(net_boot_file_name);
@@ -530,7 +579,7 @@
out:
free(str_copy);
- return ret;
+ return ret < 0 ? ret : 0;
}
#endif
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 369c611..8c44afd 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -221,6 +221,10 @@
/* Use the environment variable to override it */
ut_assertok(env_set("boot_targets", "mmc1 mmc2 usb"));
ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
+
+ /* get the usb device which has a backing file (flash1.img) */
+ ut_asserteq(0, bootflow_scan_next(&iter, &bflow));
+
ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
ut_asserteq(5, iter.num_devs);
ut_asserteq_str("mmc1.bootdev", iter.dev_used[0]->name);
@@ -260,7 +264,11 @@
ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
ut_asserteq(2, iter.num_devs);
- /* Now scan past mmc1 and make sure that the 3 USB devices show up */
+ /*
+ * Now scan past mmc1 and make sure that the 3 USB devices show up. The
+ * first one has a backing file so returns success
+ */
+ ut_asserteq(0, bootflow_scan_next(&iter, &bflow));
ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
ut_asserteq(6, iter.num_devs);
ut_asserteq_str("mmc2.bootdev", iter.dev_used[0]->name);
@@ -322,6 +330,10 @@
/* 3 MMC and 3 USB bootdevs: MMC should come before USB */
ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
+
+ /* get the usb device which has a backing file (flash1.img) */
+ ut_asserteq(0, bootflow_scan_next(&iter, &bflow));
+
ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
ut_asserteq(6, iter.num_devs);
ut_asserteq_str("mmc2.bootdev", iter.dev_used[0]->name);
@@ -339,6 +351,10 @@
bootflow_iter_uninit(&iter);
ut_assertok(bootflow_scan_first(NULL, NULL, &iter, BOOTFLOWIF_HUNT,
&bflow));
+
+ /* get the usb device which has a backing file (flash1.img) */
+ ut_asserteq(0, bootflow_scan_next(&iter, &bflow));
+
ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
ut_asserteq(7, iter.num_devs);
ut_asserteq_str("usb_mass_storage.lun0.bootdev",
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 2f859c4..9397328 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -12,7 +12,8 @@
#include <bootstd.h>
#include <cli.h>
#include <dm.h>
-#include <efi_default_filename.h>
+#include <efi.h>
+#include <efi_loader.h>
#include <expo.h>
#ifdef CONFIG_SANDBOX
#include <asm/test.h>
@@ -31,6 +32,9 @@
extern U_BOOT_DRIVER(bootmeth_cros);
extern U_BOOT_DRIVER(bootmeth_2script);
+/* Use this as the vendor for EFI to tell the app to exit boot services */
+static u16 __efi_runtime_data test_vendor[] = u"U-Boot testing";
+
static int inject_response(struct unit_test_state *uts)
{
/*
@@ -184,8 +188,9 @@
ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-2: No such file or directory");
ut_assert_nextline(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
- ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 /EFI/BOOT/"
- BOOTEFI_NAME);
+ ut_assert_nextline(
+ " 5 efi fs mmc 1 mmc1.bootdev.part_1 /EFI/BOOT/%s",
+ efi_get_basename());
ut_assert_skip_to_line("Scanning bootdev 'mmc0.bootdev':");
ut_assert_skip_to_line(
@@ -533,7 +538,7 @@
order[2] = mmc_dev;
- /* Enable the mmc4 node since we need a second bootflow */
+ /* Enable the requested mmc node since we need a second bootflow */
root = oftree_root(oftree_default());
node = ofnode_find_subnode(root, mmc_dev);
ut_assert(ofnode_valid(node));
@@ -1216,3 +1221,66 @@
return 0;
}
BOOTSTD_TEST(bootflow_android, UTF_CONSOLE);
+
+/* Test EFI bootmeth */
+static int bootflow_efi(struct unit_test_state *uts)
+{
+ static const char *order[] = {"mmc1", "usb", NULL};
+ struct bootstd_priv *std;
+ struct udevice *bootstd;
+ const char **old_order;
+
+ ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
+ std = dev_get_priv(bootstd);
+ old_order = std->bootdev_order;
+ std->bootdev_order = order;
+
+ /* disable ethernet since the hunter will run dhcp */
+ test_set_eth_enable(false);
+
+ /* make USB scan without delays */
+ test_set_skip_delays(true);
+
+ bootstd_reset_usb();
+
+ ut_assertok(run_command("bootflow scan", 0));
+ ut_assert_skip_to_line(
+ "Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found");
+
+ ut_assertok(run_command("bootflow list", 0));
+
+ ut_assert_nextlinen("Showing all");
+ ut_assert_nextlinen("Seq");
+ ut_assert_nextlinen("---");
+ ut_assert_nextlinen(" 0 extlinux");
+ ut_assert_nextlinen(
+ " 1 efi ready usb_mass_ 1 usb_mass_storage.lun0.boo /EFI/BOOT/BOOTSBOX.EFI");
+ ut_assert_nextlinen("---");
+ ut_assert_skip_to_line("(2 bootflows, 2 valid)");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("bootflow select 1", 0));
+ ut_assert_console_end();
+
+ systab.fw_vendor = test_vendor;
+
+ ut_asserteq(1, run_command("bootflow boot", 0));
+ ut_assert_nextline(
+ "** Booting bootflow 'usb_mass_storage.lun0.bootdev.part_1' with efi");
+ if (IS_ENABLED(CONFIG_LOGF_FUNC))
+ ut_assert_skip_to_line(" efi_run_image() Booting /\\EFI\\BOOT\\BOOTSBOX.EFI");
+ else
+ ut_assert_skip_to_line("Booting /\\EFI\\BOOT\\BOOTSBOX.EFI");
+
+ /* TODO: Why the \r ? */
+ ut_assert_nextline("U-Boot test app for EFI_LOADER\r");
+ ut_assert_nextline("Exiting test app");
+ ut_assert_nextline("Boot failed (err=-14)");
+
+ ut_assert_console_end();
+
+ ut_assertok(bootstd_test_drop_bootdev_order(uts));
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_efi, UTF_CONSOLE);
diff --git a/test/bootm.c b/test/bootm.c
index 52b83f1..9455f44 100644
--- a/test/bootm.c
+++ b/test/bootm.c
@@ -28,6 +28,7 @@
/* This tests relies on GD_FLG_SILENT not being set */
gd->flags &= ~GD_FLG_SILENT;
+ env_set("silent_linux", NULL);
*buf = '\0';
ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL));
@@ -183,6 +184,7 @@
ut_asserteq(0, bootm_process_cmdline(buf, 22, BOOTM_CL_SUBST));
/* Check multiple substitutions */
+ ut_assertok(env_set("bvar", NULL));
ut_assertok(env_set("var", "abc"));
strcpy(buf, "some${var}thing${bvar}else");
ut_asserteq(0, bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_SUBST));
@@ -201,6 +203,7 @@
/* Test silent processing in the bootargs variable */
static int bootm_test_silent_var(struct unit_test_state *uts)
{
+ ut_assertok(env_set("var", NULL));
env_set("bootargs", NULL);
ut_assertok(bootm_process_cmdline_env(BOOTM_CL_SUBST));
ut_assertnull(env_get("bootargs"));
diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c
index 155da3b..de9483c 100644
--- a/test/dm/sysinfo-gpio.c
+++ b/test/dm/sysinfo-gpio.c
@@ -29,9 +29,9 @@
sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_DOWN);
sandbox_gpio_set_flags(gpio, 17, 0);
ut_assertok(sysinfo_detect(sysinfo));
- ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val));
ut_asserteq(19, val);
- ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf),
buf));
ut_asserteq_str("rev_a", buf);
@@ -43,9 +43,9 @@
sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_UP);
sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_DOWN);
ut_assertok(sysinfo_detect(sysinfo));
- ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val));
ut_asserteq(5, val);
- ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf),
buf));
ut_asserteq_str("foo", buf);
@@ -57,9 +57,9 @@
sandbox_gpio_set_flags(gpio, 16, 0);
sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_UP);
ut_assertok(sysinfo_detect(sysinfo));
- ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val));
ut_asserteq(15, val);
- ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf),
buf));
ut_asserteq_str("unknown", buf);
diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c
index 4af0576..9f16a97 100644
--- a/test/env/cmd_ut_env.c
+++ b/test/env/cmd_ut_env.c
@@ -14,23 +14,62 @@
ut_assertok(run_command("setenv non_default_var1 1", 0));
ut_assert_console_end();
- ut_assertok(run_command("setenv non_default_var2 1", 0));
+ ut_assertok(run_command("setenv non_default_var2 2", 0));
ut_assert_console_end();
ut_assertok(run_command("env print non_default_var1", 0));
ut_assert_nextline("non_default_var1=1");
ut_assert_console_end();
- ut_assertok(run_command("env default non_default_var1 non_default_var2", 0));
+ ut_assertok(run_command("env default non_default_var1", 0));
ut_assert_nextline("WARNING: 'non_default_var1' not in imported env, deleting it!");
- ut_assert_nextline("WARNING: 'non_default_var2' not in imported env, deleting it!");
ut_assert_console_end();
ut_asserteq(1, run_command("env exists non_default_var1", 0));
ut_assert_console_end();
+ ut_asserteq(0, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("setenv non_default_var1 3", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env default -k non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env default -k -a -f", 0));
+ ut_assert_nextline("## Resetting to default environment");
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ /*
+ * While the following test of "env default -a" by itself
+ * works, it unfortunately causes an unrelated test case,
+ * env_test_fdt_import(), to fail, because the "from_fdt"
+ * variable would be removed.
+ */
+#if 0
+ ut_assertok(run_command("env default -a", 0));
+ ut_assert_nextline("## Resetting to default environment");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
ut_asserteq(1, run_command("env exists non_default_var2", 0));
ut_assert_console_end();
+#endif
return 0;
}
diff --git a/test/py/tests/bootstd/flash1.img.xz b/test/py/tests/bootstd/flash1.img.xz
new file mode 100644
index 0000000..29b78c6
--- /dev/null
+++ b/test/py/tests/bootstd/flash1.img.xz
Binary files differ
diff --git a/test/py/tests/test_mmc.py b/test/py/tests/test_mmc.py
index a96c4e8..4624043 100644
--- a/test/py/tests/test_mmc.py
+++ b/test/py/tests/test_mmc.py
@@ -18,16 +18,55 @@
# Setup env__mmc_device_test_skip to not skipping the test. By default, its
# value is set to True. Set it to False to run all tests for MMC device.
env__mmc_device_test_skip = False
+
+# Setup env__mmc_device to set the supported mmc modes to be tested
+env__mmc_device {
+ 'mmc_modes': ['MMC_LEGACY', 'SD_HS'],
+}
+
"""
mmc_set_up = False
controllers = 0
devices = {}
+mmc_modes_name = []
+mmc_modes = []
+
+def setup_mmc_modes(cons):
+ global mmc_modes, mmc_modes_name
+ f = cons.config.env.get('env__mmc_device', None)
+ if f:
+ mmc_modes_name = f.get('mmc_modes', None)
+
+ # Set mmc mode to default mode (legacy), if speed mode config isn't enabled
+ if cons.config.buildconfig.get('config_mmc_speed_mode_set', 'n') != 'y':
+ mmc_modes = [0]
+ return
+
+ if mmc_modes_name:
+ mmc_help = cons.run_command('mmc -help')
+ m = re.search(r"\[MMC_LEGACY(.*\n.+])", mmc_help)
+ modes = [
+ x.strip()
+ for x in m.group()
+ .replace('\n', '')
+ .replace('[', '')
+ .replace(']', '')
+ .split(',')
+ ]
+
+ for mode in mmc_modes_name:
+ mmc_modes += [modes.index(mode)]
+ else:
+ # Set mmc mode to default mode (legacy), if it is not defined in env
+ mmc_modes = [0]
def setup_mmc(u_boot_console):
if u_boot_console.config.env.get('env__mmc_device_test_skip', True):
pytest.skip('MMC device test is not enabled')
+ setup_mmc_modes(u_boot_console)
+
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_list(u_boot_console):
setup_mmc(u_boot_console)
@@ -58,21 +97,22 @@
fail = 0
for x in range(0, controllers):
devices[x]['detected'] = 'yes'
- output = u_boot_console.run_command('mmc dev %d' % x)
- # Some sort of switch here
- if 'Card did not respond to voltage select' in output:
- fail = 1
- devices[x]['detected'] = 'no'
+ for y in mmc_modes:
+ output = u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
- if 'no mmc device at slot' in output:
- devices[x]['detected'] = 'no'
+ if 'Card did not respond to voltage select' in output:
+ fail = 1
+ devices[x]['detected'] = 'no'
- if 'MMC: no card present' in output:
- devices[x]['detected'] = 'no'
+ if 'no mmc device at slot' in output:
+ devices[x]['detected'] = 'no'
- if fail:
- pytest.fail('Card not present')
+ if 'MMC: no card present' in output:
+ devices[x]['detected'] = 'no'
+
+ if fail:
+ pytest.fail('Card not present')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmcinfo(u_boot_console):
@@ -81,19 +121,22 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- output = u_boot_console.run_command('mmcinfo')
- if 'busy timeout' in output:
- pytest.skip('No SD/MMC/eMMC device present')
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+ output = u_boot_console.run_command('mmcinfo')
+ if 'busy timeout' in output:
+ pytest.skip('No SD/MMC/eMMC device present')
- obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
- try:
- capacity = float(obj.groups()[0])
- print(capacity)
- devices[x]['capacity'] = capacity
- print('Capacity of dev %d is: %g GiB' % (x, capacity))
- except ValueError:
- pytest.fail('MMC capacity not recognized')
+ assert mmc_modes_name[mmc_modes.index(y)] in output
+
+ obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
+ try:
+ capacity = float(obj.groups()[0])
+ print(capacity)
+ devices[x]['capacity'] = capacity
+ print('Capacity of dev %d is: %g GiB' % (x, capacity))
+ except ValueError:
+ pytest.fail('MMC capacity not recognized')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_info(u_boot_console):
@@ -102,19 +145,21 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
- output = u_boot_console.run_command('mmc info')
+ output = u_boot_console.run_command('mmc info')
+ assert mmc_modes_name[mmc_modes.index(y)] in output
- obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
- try:
- capacity = float(obj.groups()[0])
- print(capacity)
- if devices[x]['capacity'] != capacity:
- pytest.fail("MMC capacity doesn't match mmcinfo")
+ obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
+ try:
+ capacity = float(obj.groups()[0])
+ print(capacity)
+ if devices[x]['capacity'] != capacity:
+ pytest.fail("MMC capacity doesn't match mmcinfo")
- except ValueError:
- pytest.fail('MMC capacity not recognized')
+ except ValueError:
+ pytest.fail('MMC capacity not recognized')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_rescan(u_boot_console):
@@ -126,12 +171,13 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- output = u_boot_console.run_command('mmc rescan')
- if output:
- pytest.fail('mmc rescan has something to check')
- output = u_boot_console.run_command('echo $?')
- assert output.endswith('0')
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+ output = u_boot_console.run_command('mmc rescan')
+ if output:
+ pytest.fail('mmc rescan has something to check')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_part(u_boot_console):
@@ -148,7 +194,8 @@
lines = output.split('\n')
part_fat = []
- part_ext = []
+ part_ext2 = []
+ part_ext4 = []
for line in lines:
obj = re.search(
r'(\d)\s+\d+\s+\d+\s+\w+\d+\w+-\d+\s+(\d+\w+)', line)
@@ -161,15 +208,21 @@
print('Fat detected')
part_fat.append(part_id)
elif part_type == '83':
- print('ext detected')
- part_ext.append(part_id)
+ print('ext(2/4) detected')
+ output = u_boot_console.run_command(
+ 'fstype mmc %d:%d' % x, part_id
+ )
+ if 'ext2' in output:
+ part_ext2.append(part_id)
+ elif 'ext4' in output:
+ part_ext4.append(part_id)
else:
pytest.fail('Unsupported Filesystem on device %d' % x)
- devices[x]['ext4'] = part_ext
- devices[x]['ext2'] = part_ext
+ devices[x]['ext4'] = part_ext4
+ devices[x]['ext2'] = part_ext2
devices[x]['fat'] = part_fat
- if not part_ext and not part_fat:
+ if not part_ext2 and not part_ext4 and not part_fat:
pytest.fail('No partition detected on device %d' % x)
@pytest.mark.buildconfigspec('cmd_mmc')
@@ -185,7 +238,6 @@
fs = 'fat'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -193,20 +245,22 @@
continue
for part in partitions:
- output = u_boot_console.run_command(
- 'fatls mmc %d:%s' % (x, part))
- if 'Unrecognized filesystem type' in output:
- partitions.remove(part)
- pytest.fail('Unrecognized filesystem')
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ output = u_boot_console.run_command(
+ 'fatls mmc %d:%s' % (x, part))
+ if 'Unrecognized filesystem type' in output:
+ partitions.remove(part)
+ pytest.fail('Unrecognized filesystem')
- if not re.search(r'\d file\(s\), \d dir\(s\)', output):
- pytest.fail('%s read failed on device %d' % (fs.upper, x))
- output = u_boot_console.run_command(
- 'fatinfo mmc %d:%s' % (x, part))
- string = 'Filesystem: %s' % fs.upper
- if re.search(string, output):
- pytest.fail('%s FS failed on device %d' % (fs.upper(), x))
- part_detect = 1
+ if not re.search(r'\d file\(s\), \d dir\(s\)', output):
+ pytest.fail('%s read failed on device %d' % (fs.upper, x))
+ output = u_boot_console.run_command(
+ 'fatinfo mmc %d:%s' % (x, part))
+ string = 'Filesystem: %s' % fs.upper
+ if re.search(string, output):
+ pytest.fail('%s FS failed on device %d' % (fs.upper(), x))
+ part_detect = 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -226,7 +280,6 @@
fs = 'fat'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -234,49 +287,51 @@
continue
for part in partitions:
- part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- devices[x]['addr_%d' % part] = addr
- size = random.randint(4, 1 * 1024 * 1024)
- devices[x]['size_%d' % part] = size
- # count CRC32
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
- devices[x]['expected_crc32_%d' % part] = expected_crc32
- # do write
- file = '%s_%d' % ('uboot_test', size)
- devices[x]['file_%d' % part] = file
- output = u_boot_console.run_command(
- '%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size
- assert expected_text in output
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ devices[x]['addr_%d' % part] = addr
+ size = random.randint(4, 1 * 1024 * 1024)
+ devices[x]['size_%d' % part] = size
+ # count CRC32
+ output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+ devices[x]['expected_crc32_%d' % part] = expected_crc32
+ # do write
+ file = '%s_%d' % ('uboot_test', size)
+ devices[x]['file_%d' % part] = file
+ output = u_boot_console.run_command(
+ '%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size)
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
- alignment = int(
- u_boot_console.config.buildconfig.get(
- 'config_sys_cacheline_size', 128
+ alignment = int(
+ u_boot_console.config.buildconfig.get(
+ 'config_sys_cacheline_size', 128
+ )
+ )
+ offset = random.randrange(alignment, 1024, alignment)
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file)
)
- )
- offset = random.randrange(alignment, 1024, alignment)
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file)
- )
- assert 'Invalid FAT entry' not in output
- assert 'Unable to read file' not in output
- assert 'Misaligned buffer address' not in output
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ assert 'Invalid FAT entry' not in output
+ assert 'Unable to read file' not in output
+ assert 'Misaligned buffer address' not in output
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -300,13 +355,16 @@
print('No %s table on this device' % fs.upper())
continue
- u_boot_console.run_command('mmc dev %d' % x)
for part in partitions:
- output = u_boot_console.run_command('%sls mmc %d:%s' % (fs, x, part))
- if 'Unrecognized filesystem type' in output:
- partitions.remove(part)
- pytest.fail('Unrecognized filesystem')
- part_detect = 1
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ output = u_boot_console.run_command(
+ '%sls mmc %d:%s' % (fs, x, part)
+ )
+ if 'Unrecognized filesystem type' in output:
+ partitions.remove(part)
+ pytest.fail('Unrecognized filesystem')
+ part_detect = 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -326,7 +384,6 @@
fs = 'ext4'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -334,42 +391,44 @@
continue
for part in partitions:
- part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- devices[x]['addr_%d' % part] = addr
- size = random.randint(4, 1 * 1024 * 1024)
- devices[x]['size_%d' % part] = size
- # count CRC32
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
- devices[x]['expected_crc32_%d' % part] = expected_crc32
- # do write
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ devices[x]['addr_%d' % part] = addr
+ size = random.randint(4, 1 * 1024 * 1024)
+ devices[x]['size_%d' % part] = size
+ # count CRC32
+ output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+ devices[x]['expected_crc32_%d' % part] = expected_crc32
- file = '%s_%d' % ('uboot_test', size)
- devices[x]['file_%d' % part] = file
- output = u_boot_console.run_command(
- '%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size
- assert expected_text in output
+ # do write
+ file = '%s_%d' % ('uboot_test', size)
+ devices[x]['file_%d' % part] = file
+ output = u_boot_console.run_command(
+ '%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
- )
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
+ )
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -387,7 +446,6 @@
fs = 'ext2'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -395,12 +453,16 @@
continue
for part in partitions:
- part_detect = 1
- output = u_boot_console.run_command('%sls mmc %d:%s' % (fs, x, part))
- if 'Unrecognized filesystem type' in output:
- partitions.remove(part)
- pytest.fail('Unrecognized filesystem')
- part_detect = 1
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ output = u_boot_console.run_command(
+ '%sls mmc %d:%s' % (fs, x, part)
+ )
+ if 'Unrecognized filesystem type' in output:
+ partitions.remove(part)
+ pytest.fail('Unrecognized filesystem')
+ part_detect = 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -421,7 +483,6 @@
fs = 'ext2'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -429,23 +490,25 @@
continue
for part in partitions:
- part_detect = 1
- addr = devices[x]['addr_%d' % part]
- size = devices[x]['size_%d' % part]
- expected_crc32 = devices[x]['expected_crc32_%d' % part]
- file = devices[x]['file_%d' % part]
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = devices[x]['addr_%d' % part]
+ size = devices[x]['size_%d' % part]
+ expected_crc32 = devices[x]['expected_crc32_%d' % part]
+ file = devices[x]['file_%d' % part]
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
- )
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
+ )
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -462,8 +525,7 @@
part_detect = 0
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext4', 'ext2']:
try:
partitions = devices[x][fs]
except:
@@ -471,12 +533,14 @@
continue
for part in partitions:
- part_detect = 1
- output = u_boot_console.run_command('ls mmc %d:%s' % (x, part))
- if re.search(r'No \w+ table on this device', output):
- pytest.fail(
- '%s: Partition table not found %d' % (fs.upper(), x)
- )
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ output = u_boot_console.run_command('ls mmc %d:%s' % (x, part))
+ if re.search(r'No \w+ table on this device', output):
+ pytest.fail(
+ '%s: Partition table not found %d' % (fs.upper(), x)
+ )
if not part_detect:
pytest.skip('No partition detected')
@@ -493,8 +557,7 @@
part_detect = 0
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext4', 'ext2']:
try:
partitions = devices[x][fs]
except:
@@ -502,23 +565,25 @@
continue
for part in partitions:
- part_detect = 1
- addr = devices[x]['addr_%d' % part]
- size = devices[x]['size_%d' % part]
- expected_crc32 = devices[x]['expected_crc32_%d' % part]
- file = devices[x]['file_%d' % part]
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = devices[x]['addr_%d' % part]
+ size = devices[x]['size_%d' % part]
+ expected_crc32 = devices[x]['expected_crc32_%d' % part]
+ file = devices[x]['file_%d' % part]
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- 'load mmc %d:%s %x /%s' % (x, part, addr + offset, file)
- )
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ 'load mmc %d:%s %x /%s' % (x, part, addr + offset, file)
+ )
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No partition detected')
@@ -535,8 +600,7 @@
part_detect = 0
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext4', 'ext2']:
try:
partitions = devices[x][fs]
except:
@@ -544,18 +608,20 @@
continue
for part in partitions:
- part_detect = 1
- addr = devices[x]['addr_%d' % part]
- size = 0
- file = devices[x]['file_%d' % part]
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = devices[x]['addr_%d' % part]
+ size = 0
+ file = devices[x]['file_%d' % part]
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- 'save mmc %d:%s %x /%s %d'
- % (x, part, addr + offset, file, size)
- )
- expected_text = '%d bytes written' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ 'save mmc %d:%s %x /%s %d'
+ % (x, part, addr + offset, file, size)
+ )
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
if not part_detect:
pytest.skip('No partition detected')
@@ -582,7 +648,6 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -590,82 +655,86 @@
continue
for part in partitions:
- part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- count_f = 0
- addr_l = []
- size_l = []
- file_l = []
- crc32_l = []
- offset_l = []
- addr_l.append(addr)
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ count_f = 0
+ addr_l = []
+ size_l = []
+ file_l = []
+ crc32_l = []
+ offset_l = []
+ addr_l.append(addr)
- while count_f < num_files:
- size_l.append(random.randint(4, 1 * 1024 * 1024))
+ while count_f < num_files:
+ size_l.append(random.randint(4, 1 * 1024 * 1024))
- # CRC32 count
- output = u_boot_console.run_command(
- 'crc32 %x %x' % (addr_l[count_f], size_l[count_f])
- )
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- crc32_l.append(m.group(1))
+ # CRC32 count
+ output = u_boot_console.run_command(
+ 'crc32 %x %x' % (addr_l[count_f], size_l[count_f])
+ )
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ crc32_l.append(m.group(1))
- # Write operation
- file_l.append('%s_%d_%d' % ('uboot_test', count_f, size_l[count_f]))
- output = u_boot_console.run_command(
- '%swrite mmc %d:%s %x %s %x'
- % (
- fs,
- x,
- part,
- addr_l[count_f],
- file_l[count_f],
- size_l[count_f],
+ # Write operation
+ file_l.append(
+ '%s_%d_%d' % ('uboot_test', count_f, size_l[count_f])
)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size_l[count_f]
- assert expected_text in output
+ output = u_boot_console.run_command(
+ '%swrite mmc %d:%s %x %s %x'
+ % (
+ fs,
+ x,
+ part,
+ addr_l[count_f],
+ file_l[count_f],
+ size_l[count_f],
+ )
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size_l[count_f]
+ assert expected_text in output
- addr_l.append(addr_l[count_f] + size_l[count_f] + 1048576)
- count_f += 1
+ addr_l.append(addr_l[count_f] + size_l[count_f] + 1048576)
+ count_f += 1
- count_f = 0
- while count_f < num_files:
- alignment = int(
- u_boot_console.config.buildconfig.get(
- 'config_sys_cacheline_size', 128
+ count_f = 0
+ while count_f < num_files:
+ alignment = int(
+ u_boot_console.config.buildconfig.get(
+ 'config_sys_cacheline_size', 128
+ )
)
- )
- offset_l.append(random.randrange(alignment, 1024, alignment))
+ offset_l.append(random.randrange(alignment, 1024, alignment))
- # Read operation
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x %s'
- % (
- fs,
- x,
- part,
- addr_l[count_f] + offset_l[count_f],
- file_l[count_f],
+ # Read operation
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x %s'
+ % (
+ fs,
+ x,
+ part,
+ addr_l[count_f] + offset_l[count_f],
+ file_l[count_f],
+ )
)
- )
- assert 'Invalid FAT entry' not in output
- assert 'Unable to read file' not in output
- assert 'Misaligned buffer address' not in output
- expected_text = '%d bytes read' % size_l[count_f]
- assert expected_text in output
+ assert 'Invalid FAT entry' not in output
+ assert 'Unable to read file' not in output
+ assert 'Misaligned buffer address' not in output
+ expected_text = '%d bytes read' % size_l[count_f]
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f])
- )
- assert crc32_l[count_f] in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f])
+ )
+ assert crc32_l[count_f] in output
- count_f += 1
+ count_f += 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py
index 2397fd3..e1f203b 100644
--- a/test/py/tests/test_usb.py
+++ b/test/py/tests/test_usb.py
@@ -227,7 +227,8 @@
lines = output.split('\n')
part_fat = []
- part_ext = []
+ part_ext2 = []
+ part_ext4 = []
for line in lines:
obj = re.search(r'(\d)\s+\d+\s+\d+\s+\w+\d+\w+-\d+\s+(\d+\w+)', line)
if obj:
@@ -239,15 +240,21 @@
print('Fat detected')
part_fat.append(part_id)
elif part_type == '83':
- print('ext detected')
- part_ext.append(part_id)
+ print('ext(2/4) detected')
+ output = u_boot_console.run_command(
+ 'fstype usb %d:%d' % i, part_id
+ )
+ if 'ext2' in output:
+ part_ext2.append(part_id)
+ elif 'ext4' in output:
+ part_ext4.append(part_id)
else:
pytest.fail('Unsupported Filesystem on device %d' % i)
- devices[i]['ext4'] = part_ext
- devices[i]['ext2'] = part_ext
+ devices[i]['ext4'] = part_ext4
+ devices[i]['ext2'] = part_ext2
devices[i]['fat'] = part_fat
- if not part_ext and not part_fat:
+ if not part_ext2 and not part_ext4 and not part_fat:
pytest.fail('No partition detected on device %d' % i)
return devices, controllers, storage_device
@@ -497,7 +504,7 @@
for part in partitions:
part_detect = 1
file, size, expected_crc32 = \
- usb_ext4load_ext4write(u_boot_console, 'ext4', x, part)
+ usb_ext4load_ext4write(u_boot_console, fs, x, part)
addr = u_boot_utils.find_ram_base(u_boot_console)
offset = random.randrange(128, 1024, 128)
@@ -526,7 +533,7 @@
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
u_boot_console.run_command('usb dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
except:
@@ -556,7 +563,7 @@
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
u_boot_console.run_command('usb dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
except:
@@ -570,7 +577,7 @@
if fs == 'fat':
file, size, expected_crc32 = \
usb_fatload_fatwrite(u_boot_console, fs, x, part)
- elif fs == 'ext4':
+ elif fs in ['ext4', 'ext2']:
file, size, expected_crc32 = \
usb_ext4load_ext4write(u_boot_console, fs, x, part)
@@ -600,7 +607,7 @@
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
u_boot_console.run_command('usb dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
except:
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 9166c8f..6d44191 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -28,21 +28,22 @@
if not os.path.exists(dirname):
os.mkdir(dirname)
-def setup_image(cons, mmc_dev, part_type, second_part=False):
+def setup_image(cons, devnum, part_type, second_part=False, basename='mmc'):
"""Create a 20MB disk image with a single partition
Args:
cons (ConsoleBase): Console to use
- mmc_dev (int): MMC device number to use, e.g. 1
+ devnum (int): Device number to use, e.g. 1
part_type (int): Partition type, e.g. 0xc for FAT32
second_part (bool): True to contain a small second partition
+ basename (str): Base name to use in the filename, e.g. 'mmc'
Returns:
tuple:
str: Filename of MMC image
str: Directory name of 'mnt' directory
"""
- fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
+ fname = os.path.join(cons.config.source_dir, f'{basename}{devnum}.img')
mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
mkdir_cond(mnt)
@@ -78,16 +79,17 @@
u_boot_utils.run_and_log(cons, f'sudo chown {getpass.getuser()} {mnt}')
return loop
-def copy_prepared_image(cons, mmc_dev, fname):
+def copy_prepared_image(cons, devnum, fname, basename='mmc'):
"""Use a prepared image since we cannot create one
Args:
cons (ConsoleBase): Console touse
- mmc_dev (int): MMC device number
+ devnum (int): device number
fname (str): Filename of MMC image
+ basename (str): Base name to use in the filename, e.g. 'mmc'
"""
infname = os.path.join(cons.config.source_dir,
- f'test/py/tests/bootstd/mmc{mmc_dev}.img.xz')
+ f'test/py/tests/bootstd/{basename}{devnum}.img.xz')
u_boot_utils.run_and_log(cons, ['sh', '-c', f'xz -dc {infname} >{fname}'])
def setup_bootmenu_image(cons):
@@ -547,6 +549,44 @@
with open(fn, 'wb') as fh:
fh.write(data)
+
+def setup_efi_image(cons):
+ """Create a 20MB disk image with an EFI app on it"""
+ devnum = 1
+ basename = 'flash'
+ fname, mnt = setup_image(cons, devnum, 0xc, second_part=True,
+ basename=basename)
+
+ loop = None
+ mounted = False
+ complete = False
+ try:
+ loop = mount_image(cons, fname, mnt, 'ext4')
+ mounted = True
+ efi_dir = os.path.join(mnt, 'EFI')
+ mkdir_cond(efi_dir)
+ bootdir = os.path.join(efi_dir, 'BOOT')
+ mkdir_cond(bootdir)
+ efi_src = os.path.join(cons.config.build_dir,
+ f'lib/efi_loader/testapp.efi')
+ efi_dst = os.path.join(bootdir, 'BOOTSBOX.EFI')
+ with open(efi_src, 'rb') as inf:
+ with open(efi_dst, 'wb') as outf:
+ outf.write(inf.read())
+ complete = True
+ except ValueError as exc:
+ print(f'Falled to create image, failing back to prepared copy: {exc}')
+
+ finally:
+ if mounted:
+ u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
+ if loop:
+ u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
+
+ if not complete:
+ copy_prepared_image(cons, devnum, fname, basename)
+
+
@pytest.mark.buildconfigspec('cmd_bootflow')
@pytest.mark.buildconfigspec('sandbox')
def test_ut_dm_init_bootstd(u_boot_console):
@@ -557,6 +597,7 @@
setup_cedit_file(u_boot_console)
setup_cros_image(u_boot_console)
setup_android_image(u_boot_console)
+ setup_efi_image(u_boot_console)
# Restart so that the new mmc1.img is picked up
u_boot_console.restart_uboot()
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 5eb4b96..96ece28 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -14,6 +14,7 @@
static int container = -1;
static int32_t core_type = CFG_CORE_INVALID;
static bool emmc_fastboot;
+static bool dcd_skip;
static image_t param_stack[IMG_STACK_SIZE];
static uint8_t fuse_version;
static uint16_t sw_version;
@@ -41,6 +42,7 @@
static table_entry_t imx8image_cmds[] = {
{CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
+ {CMD_DCD_SKIP, "DCD_SKIP", "skip DCD init", },
{CMD_FUSE_VERSION, "FUSE_VERSION", "fuse version", },
{CMD_SW_VERSION, "SW_VERSION", "sw version", },
{CMD_MSG_BLOCK, "MSG_BLOCK", "msg block", },
@@ -88,6 +90,9 @@
if (!strncmp("emmc_fastboot", token, 13))
emmc_fastboot = true;
break;
+ case CMD_DCD_SKIP:
+ if (!strncmp("true", token, 4))
+ dcd_skip = true;
case CMD_FUSE_VERSION:
fuse_version = (uint8_t)(strtoll(token, NULL, 0) & 0xFF);
break;
@@ -1024,7 +1029,7 @@
fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version);
build_container(soc, sector_size, emmc_fastboot,
- img_sp, false, fuse_version, sw_version, outfd);
+ img_sp, dcd_skip, fuse_version, sw_version, outfd);
return 0;
}
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 49f5b78..fb6c57f 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -866,12 +866,12 @@
dtb = malloc(dtb_size);
if (!dtb) {
- fprintf(stderr, "Can't allocated %ld\n", dtb_size);
+ fprintf(stderr, "Can't allocated %zd\n", dtb_size);
return NULL;
}
if (fread(dtb, dtb_size, 1, f) != 1) {
- fprintf(stderr, "Can't read %ld bytes from %s\n",
+ fprintf(stderr, "Can't read %zd bytes from %s\n",
dtb_size, path);
free(dtb);
return NULL;