| commit | b696424d3caef7c86c3a343eefcb5443347a67ab | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Wed Jun 15 11:56:55 2022 +0200 |
| committer | Michal Simek <michal.simek@amd.com> | Fri Jun 24 14:14:33 2022 +0200 |
| tree | 613596318541bd34ebfa6f4c98a04dc4f3a04dfe | |
| parent | d42dec0657f9d484d779526e3bd821ef5a7f871f [diff] [blame] |
arm64: zynqmp: Update tps53681 i2c address TI manual (https://www.ti.com/lit/gpn/TPS53681) is saying that i2c address is 7bit where c0h is 1100000 which is 0x60. This will fix issues reported by make dtbs that 0xc0 is above 7bit regular i2c address range. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2f50c1cd258f6b05deb2a6a9af7fa92952f3f8cb.1655287013.git.michal.simek@amd.com
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 7b3722f..1fa023f 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -247,9 +247,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - reg_vccint: tps53681@c0 { /* u69 */ + reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; - reg = <0xc0>; + reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25";