tree 1a2b5826d92e13bfae2232ef0c5c13000a966648
parent 7240fa7027c37cffe8d5443339015b9064731d79
author Bin Meng <bmeng.cn@gmail.com> 1585405529 -0700
committer Tom Rini <trini@konsulko.com> 1586548456 -0400

azure/gitlab/travis: Add RISC-V SPL testing

This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
we test SPL running in M-mode and U-Boot proper running in S-mode,
with a 4-core SMP configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>