commit b68d9d67eb013d179b6b46d27f6d8097d2adeeba
author Bin Meng <bmeng.cn@gmail.com> Sat Mar 28 07:25:29 2020 -0700
committer Tom Rini <trini@konsulko.com> Fri Apr 10 15:54:16 2020 -0400
tree 1a2b5826d92e13bfae2232ef0c5c13000a966648
parent 7240fa7027c37cffe8d5443339015b9064731d79

azure/gitlab/travis: Add RISC-V SPL testing

This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
we test SPL running in M-mode and U-Boot proper running in S-mode,
with a 4-core SMP configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

.gitlab-ci.yml

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index d414140..bf39435 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -24,6 +24,14 @@
     - cp /opt/grub/grubriscv32.efi ~/grub_riscv32.efi
     - cp /opt/grub/grubaa64.efi ~/grub_arm64.efi
     - cp /opt/grub/grubarm.efi ~/grub_arm.efi
+    - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
+        wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv32-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-0.6-rv32-bin/platform/qemu/virt/firmware/fw_dynamic.bin;
+      fi
+    - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
+        wget -O - https://github.com/riscv/opensbi/releases/download/v0.6/opensbi-0.6-rv64-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-0.6-rv64-bin/platform/qemu/virt/firmware/fw_dynamic.bin;
+      fi
 
   after_script:
     - rm -rf /tmp/uboot-test-hooks /tmp/venv
@@ -314,6 +322,22 @@
     BUILDMAN: "^qemu-riscv64$"
   <<: *buildman_and_testpy_dfn
 
+qemu-riscv32_spl test.py:
+  tags: [ 'all' ]
+  variables:
+    TEST_PY_BD: "qemu-riscv32_spl"
+    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu-riscv32_spl$"
+  <<: *buildman_and_testpy_dfn
+
+qemu-riscv64_spl test.py:
+  tags: [ 'all' ]
+  variables:
+    TEST_PY_BD: "qemu-riscv64_spl"
+    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu-riscv64_spl$"
+  <<: *buildman_and_testpy_dfn
+
 qemu-x86 test.py:
   tags: [ 'all' ]
   variables: