commit b5c087b4f1f9c73433e49a3c652e88855208d9cf
author Marek Vasut <marex@denx.de> Tue May 08 18:44:43 2018 +0200
committer Marek Vasut <marex@denx.de> Sat Mar 09 17:59:14 2019 +0100
tree 1da56b2c374dbf3a72806923ffcd040b510ca95b
parent bb6e32a30c925c60201f5ac7964e1c2d82591c92

ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset

The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

include/configs/socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f182e9e..181af9b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -275,12 +275,20 @@
 
 /* SPL QSPI boot support */
 #ifdef CONFIG_SPL_SPI_SUPPORT
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
+#endif
 #endif
 
 /* SPL NAND boot support */
 #ifdef CONFIG_SPL_NAND_SUPPORT
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#endif
 #endif
 
 /*