NET: Move MDIO regs out of TSEC Space
Moved the mdio regs out of the tsec structure,and
provided different offsets for tsec base and mdio
base so that provision for etsec2.0 can be provided.
This patch helps in providing the support for etsec2.0
In etsec2.0, the MDIO register space and the etsec reg
space are different.
Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
platform specific files.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 3f74118..d8b6619 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -5,7 +5,7 @@
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
@@ -80,7 +80,7 @@
#ifdef CONFIG_MPC85XX_FEC
{
.regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
- .miiregs = (tsec_t *)(TSEC_BASE_ADDR),
+ .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
.devname = CONFIG_MPC85XX_FEC_NAME,
.phyaddr = FEC_PHY_ADDR,
.flags = FEC_FLAGS
@@ -133,6 +133,7 @@
privlist[num_tsecs++] = priv;
priv->regs = tsec_info->regs;
priv->phyregs = tsec_info->miiregs;
+ priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
priv->flags = tsec_info->flags;
@@ -219,7 +220,7 @@
}
/* Writes the given phy's reg with value, using the specified MDIO regs */
-static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
+static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
uint reg, uint value)
{
int timeout = 1000000;
@@ -242,7 +243,7 @@
* notvalid bit cleared), and the bus to cease activity (miimind
* busy bit cleared), and then returns the value
*/
-uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
+uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum)
{
uint value;
@@ -287,11 +288,11 @@
{
/* Access TBI PHY registers at given TSEC register offset as opposed to the
* register offset used for external PHY accesses */
- tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
+ tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
TBIANA_SETTINGS);
- tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
+ tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
TBICON_CLK_SELECT);
- tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
+ tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
TBICR_SETTINGS);
}
@@ -303,12 +304,10 @@
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_info *curphy;
- volatile tsec_t *phyregs = priv->phyregs;
volatile tsec_t *regs = priv->regs;
/* Assign a Physical address to the TBI */
regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
- phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE;
asm("sync");
/* Reset MII (due to new addresses) */
@@ -733,7 +732,7 @@
uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
{
uint phyid;
- volatile tsec_t *regbase = priv->phyregs;
+ volatile tsec_mdio_t *regbase = priv->phyregs;
int timeout = 1000000;
for (phyid = 0; phyid < 4; phyid++) {
@@ -1766,7 +1765,7 @@
{
int i;
uint result;
- volatile tsec_t *phyregs = priv->phyregs;
+ volatile tsec_mdio_t *phyregs = priv->phyregs;
phyregs->miimcfg = MIIMCFG_RESET;
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index c60a7d2..3a144f0 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
*
* MPC83xx Internal Memory Map
*
@@ -868,4 +868,10 @@
#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
+
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_MDIO1_OFFSET 0x24520
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
#endif /* __IMMAP_83xx__ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 8c80650..3d24ebe 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1959,6 +1959,8 @@
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_MDIO1_OFFSET 0x24520
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
@@ -2019,4 +2021,7 @@
#define CONFIG_SYS_MPC85xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
#endif /*__IMMAP_85xx__*/
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index fdfc654..41892b4 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1,7 +1,7 @@
/*
* MPC86xx Internal Memory Map
*
- * Copyright(c) 2004 Freescale Semiconductor
+ * Copyright 2004 Freescale Semiconductor
* Jeff Brown (Jeffrey@freescale.com)
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@@ -1298,4 +1298,10 @@
#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_MDIO1_OFFSET 0x24520
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
#endif /*__IMMAP_86xx__*/
diff --git a/include/tsec.h b/include/tsec.h
index 0ac3034..92bd028 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -7,7 +7,7 @@
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
@@ -20,22 +20,15 @@
#include <net.h>
#include <config.h>
-#ifndef CONFIG_SYS_TSEC1_OFFSET
- #define CONFIG_SYS_TSEC1_OFFSET (0x24000)
-#endif
-
-#define TSEC_SIZE 0x01000
-
-/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
- || defined(CONFIG_MPC83xx)
- #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#endif
+#define TSEC_SIZE 0x01000
+#define TSEC_MDIO_OFFSET 0x01000
#define STD_TSEC_INFO(num) \
{ \
.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
- .miiregs = (tsec_t *)TSEC_BASE_ADDR, \
+ .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
+ .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ + (num - 1) * TSEC_MDIO_OFFSET), \
.devname = CONFIG_TSEC##num##_NAME, \
.phyaddr = TSEC##num##_PHY_ADDR, \
.flags = TSEC##num##_FLAGS \
@@ -44,7 +37,9 @@
#define SET_STD_TSEC_INFO(x, num) \
{ \
x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
- x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \
+ x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
+ x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ + (num - 1) * TSEC_MDIO_OFFSET); \
x.devname = CONFIG_TSEC##num##_NAME; \
x.phyaddr = TSEC##num##_PHY_ADDR; \
x.flags = TSEC##num##_FLAGS;\
@@ -461,6 +456,15 @@
uint res2[24];
} tsec_hash_t;
+typedef struct tsec_mdio {
+ uint miimcfg; /* MII Management: Configuration */
+ uint miimcom; /* MII Management: Command */
+ uint miimadd; /* MII Management: Address */
+ uint miimcon; /* MII Management: Control */
+ uint miimstat; /* MII Management: Status */
+ uint miimind; /* MII Management: Indicators */
+} tsec_mdio_t;
+
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
@@ -526,12 +530,7 @@
uint res51c;
- uint miimcfg; /* MII Management: Configuration */
- uint miimcom; /* MII Management: Command */
- uint miimadd; /* MII Management: Address */
- uint miimcon; /* MII Management: Control */
- uint miimstat; /* MII Management: Status */
- uint miimind; /* MII Management: Indicators */
+ uint resmdio[6];
uint res538;
@@ -571,7 +570,8 @@
struct tsec_private {
volatile tsec_t *regs;
- volatile tsec_t *phyregs;
+ volatile tsec_mdio_t *phyregs;
+ volatile tsec_mdio_t *phyregs_sgmii;
struct phy_info *phyinfo;
uint phyaddr;
u32 flags;
@@ -630,7 +630,8 @@
struct tsec_info_struct {
tsec_t *regs;
- tsec_t *miiregs;
+ tsec_mdio_t *miiregs;
+ tsec_mdio_t *miiregs_sgmii;
char *devname;
unsigned int phyaddr;
u32 flags;