Merge patch series "mediatek: final preparation for OF_UPSTREAM support"
Christian Marangi <ansuelsmth@gmail.com> says:
This is the last batch of part to push actual support of
OF_UPSTREAM for the mediatek SoC.
The plan is to make the current downstream DTS on part with
upstream implementation so we can permit a gradual transition to
it while we don't cause any regression to any user.
This is to have the same node downstream and upstream.
Mediatek is working hard upstream to also push all the remaining
nodes.
All patch are the final changes after the pinctrl patch
merged previously.
All patch pass CI tests
Link: https://github.com/u-boot/u-boot/pull/731
Link: https://lore.kernel.org/r/20250127134046.26345-1-ansuelsmth@gmail.com
diff --git a/arch/arm/dts/mt7981-emmc-rfb.dts b/arch/arm/dts/mt7981-emmc-rfb.dts
index d6590f0..67f178b 100644
--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
@@ -48,7 +48,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -56,7 +56,7 @@
};
};
-&pinctrl {
+&pio {
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts
index d6ebd65..08e1b76 100644
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -39,7 +39,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -47,7 +47,7 @@
};
};
-&pinctrl {
+&pio {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts
index 2adbc37..2f43e65 100644
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -48,7 +48,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -56,7 +56,7 @@
};
};
-&pinctrl {
+&pio {
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 2844ab0..5b4cadc 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/clock/mt7981-clk.h>
#include <dt-bindings/reset/mt7629-reset.h>
#include <dt-bindings/pinctrl/mt65xx.h>
@@ -106,7 +107,7 @@
bootph-all;
};
- pinctrl: pinctrl@11d00000 {
+ pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0x11d00000 0x1000>,
<0x11c00000 0x1000>,
@@ -117,13 +118,11 @@
<0x11f00000 0x1000>,
<0x11f10000 0x1000>,
<0x1000b000 0x1000>;
- reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
- "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
- "iocfg_tm_base", "iocfg_tl_base", "eint";
- gpio: gpio-controller {
- gpio-controller;
- #gpio-cells = <2>;
- };
+ reg-names = "gpio", "iocfg_rt", "iocfg_rm",
+ "iocfg_rb", "iocfg_lb", "iocfg_bl",
+ "iocfg_tm", "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
};
pwm: pwm@10048000 {
@@ -317,4 +316,86 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt7981-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0x11200000 0x2e00>,
+ <0x11203e00 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
+ <&infracfg CLK_INFRA_IUSB_CK>,
+ <&infracfg CLK_INFRA_IUSB_133_CK>,
+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
+ clock-names = "sys_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck",
+ "xhci_ck";
+ mediatek,u3p-dis-msk = <0x1>;
+ status = "okay";
+ };
+
+ pcie: pcie@11280000 {
+ compatible = "mediatek,mt8192-pcie";
+ device_type = "pci";
+ reg = <0x11280000 0x4000>;
+ reg-names = "pcie-mac";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
+ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
+ <&infracfg CLK_INFRA_IPCIER_CK>,
+ <&infracfg CLK_INFRA_IPCIEB_CK>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
+ phys = <&u3port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
+
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+
+ status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ };
+ };
+
+ usbtphy: usb-phy@11e10000 {
+ compatible = "mediatek,mt7981",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ u2port0: usb-phy@11e10000 {
+ reg = <0x11e10000 0x700>;
+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@11e10700 {
+ reg = <0x11e10700 0x900>;
+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,syscon-type = <&topmisc 0x218 0>;
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index f871f23..b2c5709 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -122,7 +122,7 @@
#clock-cells = <1>;
};
- pinctrl: pinctrl@1001f000 {
+ pio: pinctrl@1001f000 {
compatible = "mediatek,mt7986-pinctrl";
reg = <0x1001f000 0x1000>,
<0x11c30000 0x1000>,
@@ -132,13 +132,11 @@
<0x11f00000 0x1000>,
<0x11f10000 0x1000>,
<0x1000b000 0x1000>;
- reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
- "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
- "iocfg_tl_base", "eint";
- gpio: gpio-controller {
- gpio-controller;
- #gpio-cells = <2>;
- };
+ reg-names = "gpio", "iocfg_rt", "iocfg_rb",
+ "iocfg_lt", "iocfg_lb", "iocfg_tr",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
};
pwm: pwm@10048000 {
diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
index c156a81..e01ae4c 100644
--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
@@ -38,12 +38,12 @@
factory {
label = "reset";
- gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
- gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
@@ -52,12 +52,12 @@
led_status_green: green {
label = "green:status";
- gpios = <&gpio 69 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
};
led_status_blue: blue {
label = "blue:status";
- gpios = <&gpio 86 GPIO_ACTIVE_HIGH>;
+ gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
};
};
@@ -78,7 +78,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -86,7 +86,7 @@
};
};
-&pinctrl {
+&pio {
spic_pins: spi1-pins-func-1 {
mux {
function = "spi";
diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts
index 67d14a9..d4bbb23 100644
--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
@@ -57,7 +57,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -65,7 +65,7 @@
};
};
-&pinctrl {
+&pio {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts
index 4f8fa70..11823e0 100644
--- a/arch/arm/dts/mt7986a-sd-rfb.dts
+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
@@ -49,7 +49,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -57,7 +57,7 @@
};
};
-&pinctrl {
+&pio {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts
index f98b04a..0a731fe 100644
--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
@@ -48,7 +48,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -56,7 +56,7 @@
};
};
-&pinctrl {
+&pio {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts
index ec80a2f..e5fb4d7 100644
--- a/arch/arm/dts/mt7986b-sd-rfb.dts
+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
@@ -49,7 +49,7 @@
mediatek,gmac-id = <0>;
phy-mode = "2500base-x";
mediatek,switch = "mt7531";
- reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
@@ -57,7 +57,7 @@
};
};
-&pinctrl {
+&pio {
spi_flash_pins: spi0-pins-func-1 {
mux {
function = "flash";
diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts
index 2579d70..1694ef8d 100644
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -80,7 +80,7 @@
status = "disabled";
};
-&pinctrl {
+&pio {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts
index 38727a2..63e9231 100644
--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -53,7 +53,7 @@
};
};
-&pinctrl {
+&pio {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index f2bfde5..2d57c6f 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -110,7 +110,7 @@
#clock-cells = <1>;
};
- pinctrl: pinctrl@1001f000 {
+ pio: pinctrl@1001f000 {
compatible = "mediatek,mt7988-pinctrl";
reg = <0 0x1001f000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
@@ -119,13 +119,11 @@
<0 0x11e00000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
- reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
- "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
+ reg-names = "gpio", "iocfg_tr", "iocfg_br",
+ "iocfg_rb", "iocfg_lb", "iocfg_tl",
"eint";
- gpio: gpio-controller {
- gpio-controller;
- #gpio-cells = <2>;
- };
+ gpio-controller;
+ #gpio-cells = <2>;
};
sgmiisys0: syscon@10060000 {
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
index 84c3996..6b97690 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -1051,8 +1051,9 @@
};
static const char *const mt7981_pinctrl_register_base_names[] = {
- "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base",
- "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
+ "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
+ "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
+ "eint",
};
static const struct mtk_pinctrl_soc mt7981_data = {