commit b513166ffecd992dfb3d1bd711a8feb7cc1bf8a0
author Wolfgang Denk <wd@denx.de> Thu May 12 19:26:45 2011 +0200
committer Wolfgang Denk <wd@denx.de> Thu May 12 19:26:45 2011 +0200
tree 80463960431e5e2c57bc329f53fe18ec9f6b1870
parent 00dceba2f94e629cb42e987083cb7ac9510a3099
parent f639eadeb133e3a262a30279aba98078a8d6aa48

Merge branch 'master' of git://git.denx.de/u-boot-arm

README

diff --git a/README b/README
index 76b1500..68ef2b2 100644
--- a/README
+++ b/README
@@ -475,6 +475,18 @@
 		define this to a list of base addresses for each (supported)
 		port. See e.g. include/configs/versatile.h
 
+		CONFIG_PL011_SERIAL_RLCR
+
+		Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
+		have separate receive and transmit line control registers.  Set
+		this variable to initialize the extra register.
+
+		CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+
+		On some platforms (e.g. U8500) U-Boot is loaded by a second stage
+		boot loader that has already initialized the UART.  Define this
+		variable to flush the UART at init time.
+
 
 - Console Interface:
 		Depending on board, define exactly one serial port

drivers/serial/serial_pl01x.c

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 5dfcde8..7a064ff 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -111,6 +111,15 @@
 	unsigned int divider;
 	unsigned int remainder;
 	unsigned int fraction;
+	unsigned int lcr;
+
+#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+	/* Empty RX fifo if necessary */
+	if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
+		while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
+			readl(&regs->dr);
+	}
+#endif
 
 	/* First, disable everything */
 	writel(0, &regs->pl011_cr);
@@ -131,9 +140,24 @@
 	writel(fraction, &regs->pl011_fbrd);
 
 	/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
-	writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN,
-	       &regs->pl011_lcrh);
+	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+	writel(lcr, &regs->pl011_lcrh);
+
+#ifdef CONFIG_PL011_SERIAL_RLCR
+	{
+		int i;
+
+		/*
+		 * Program receive line control register after waiting
+		 * 10 bus cycles.  Delay be writing to readonly register
+		 * 10 times
+		 */
+		for (i = 0; i < 10; i++)
+			writel(lcr, &regs->fr);
 
+		writel(lcr, &regs->pl011_rlcr);
+	}
+#endif
 	/* Finally, enable the UART */
 	writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
 	       &regs->pl011_cr);

drivers/serial/serial_pl01x.h

diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h
index b670c24..96ee381 100644
--- a/drivers/serial/serial_pl01x.h
+++ b/drivers/serial/serial_pl01x.h
@@ -43,7 +43,11 @@
 	u32	pl010_lcrl;	/* 0x10 Line control register, low byte */
 	u32	pl010_cr;	/* 0x14 Control register */
 	u32	fr;		/* 0x18 Flag register (Read only) */
+#ifdef CONFIG_PL011_SERIAL_RLCR
+	u32	pl011_rlcr;	/* 0x1c Receive line control register */
+#else
 	u32	reserved;
+#endif
 	u32	ilpr;		/* 0x20 IrDA low-power counter register */
 	u32	pl011_ibrd;	/* 0x24 Integer baud rate register */
 	u32	pl011_fbrd;	/* 0x28 Fractional baud rate register */

net/net.c

diff --git a/net/net.c b/net/net.c
index e50bdf1..19ac019 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1718,7 +1718,6 @@
 #if defined(CONFIG_CMD_NFS)
 	case NFS:
 #endif
-	case NETCONS:
 	case TFTP:
 		if (NetServerIP == 0) {
 			puts ("*** ERROR: `serverip' not set\n");
@@ -1728,7 +1727,9 @@
     defined(CONFIG_CMD_DNS)
     common:
 #endif
+		/* Fall through */
 
+	case NETCONS:
 		if (NetOurIP == 0) {
 			puts ("*** ERROR: `ipaddr' not set\n");
 			return (1);