rockchip: rk3399-gru: Enable dcache and signature validation in SPL
With TPL being used to init DRAM, SPL being used to load FIT and the
adjusted FIT payload offset it is now possible to increase the size
limit of SPL to 256 KB and enable uses of dcache and FIT signature
validation.
Drop SPL_SYS_DCACHE_OFF=y to enable use of dcache in SPL.
Drop SPL_FIT_SIGNATURE=n to enable signature validation of FIT in SPL.
Change SPL_MAX_SIZE to 256 KB now that payload offset has moved in SPI
and TF-A may be loaded to 0x40000 in DRAM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index b16bc3a..03fd117 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
@@ -19,7 +18,6 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
-# CONFIG_SPL_FIT_SIGNATURE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -28,7 +26,7 @@
# CONFIG_TPL_BLOBLIST is not set
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
-CONFIG_SPL_MAX_SIZE=0x1e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_HANDOFF=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set