| commit | b45fc40c9f0906bf9d3e701462d940410d6c71ad | [log] [tgz] |
|---|---|---|
| author | Kever Yang <kever.yang@rock-chips.com> | Mon May 15 20:52:16 2017 +0800 |
| committer | Simon Glass <sjg@chromium.org> | Wed Jun 07 07:29:20 2017 -0600 |
| tree | 30f953ef8d11259b60f5603cdd4bd4ad4d2a9b71 | |
| parent | cb04ad2e0c9085bacb312aaf5265a77fd4de7dce [diff] |
rockchip: clock: rk3036: some fix according TRM - hclk/pclk_div range　should use '<=' instead of '<' - use GPLL for pd_bus clock source - pd_bus HCLK/PCLK clock rate should not bigger than ACLK Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>