diff --git a/README b/README
index f24decf..f540757 100644
--- a/README
+++ b/README
@@ -1364,18 +1364,18 @@
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
-		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
-		CONFIG_SYS_NAND_ECCBYTES
+		CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+		CFG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
-		CONFIG_SYS_NAND_U_BOOT_DST
+		CFG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 
-		CONFIG_SYS_NAND_U_BOOT_SIZE
+		CFG_SYS_NAND_U_BOOT_SIZE
 		Size of image to load
 
-		CONFIG_SYS_NAND_U_BOOT_START
+		CFG_SYS_NAND_U_BOOT_START
 		Entry point in loaded image to jump to
 
 		CONFIG_SPL_RAM_DEVICE
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index dc414c7..5dd90b4 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -32,17 +32,17 @@
 #define NAND_SMALL_BLOCK_PAGE_SIZE	0x200
 
 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS		{ 10, 11, 12, 13, 14, 15, }
+#define CFG_SYS_NAND_ECCPOS		{ 10, 11, 12, 13, 14, 15, }
 #else
 #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
 #endif
 
-#define CONFIG_SYS_NAND_ECCSIZE		0x100
-#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCSIZE		0x100
+#define CFG_SYS_NAND_ECCBYTES	3
 #endif	/* CONFIG_NAND_LPC32XX_SLC */
 
 /* NOR Flash */
diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index a4cc27e..38a1a6e 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -18,13 +18,13 @@
 #define MASK_CLE		0x10
 #define MASK_ALE		0x08
 
-#ifdef CONFIG_SYS_NAND_MASK_CLE
+#ifdef CFG_SYS_NAND_MASK_CLE
 #undef MASK_CLE
-#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#define MASK_CLE CFG_SYS_NAND_MASK_CLE
 #endif
-#ifdef CONFIG_SYS_NAND_MASK_ALE
+#ifdef CFG_SYS_NAND_MASK_ALE
 #undef MASK_ALE
-#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#define MASK_ALE CFG_SYS_NAND_MASK_ALE
 #endif
 
 struct davinci_emif_regs {
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index d877be1..ae1f6fe 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -35,7 +35,7 @@
  */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define CFG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
 #define NAND_ALLOW_ERASE_ALL		1
 #endif
 
diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c
index 2dcf0cf..803dc7f 100644
--- a/arch/arm/mach-omap2/mem-common.c
+++ b/arch/arm/mach-omap2/mem-common.c
@@ -135,7 +135,7 @@
 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
 	case MTD_DEV_TYPE_NAND:
 		gpmc_regs = gpmc_regs_nand;
-		base = CONFIG_SYS_NAND_BASE;
+		base = CFG_SYS_NAND_BASE;
 		size = GPMC_SIZE_16M;
 		break;
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
index e795cd1..b0b9a1e 100644
--- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
@@ -1,16 +1,16 @@
 #if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index d8f6cfe..8fcf208 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -71,16 +71,16 @@
 	 * has been determined
 	 */
 
-#if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
-	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
+#if defined(CFG_SYS_NAND_BR_PRELIM)  \
+	&& defined(CFG_SYS_NAND_OR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
 	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
 	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
 #else
-#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
 #endif
 }
 
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index a9ea9b5..d2c6ada 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -56,10 +56,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 }
 #endif
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 0c53325..2992353 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -78,10 +78,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
 	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 3e232aa..b2b7093 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -69,10 +69,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 3af7097..2f3a772 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -63,10 +63,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index f05ee322..bca7c8d 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -64,10 +64,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOD);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
 	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index b5af35b..817aa2f 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -65,9 +65,9 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCD);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c
index 7035fab..786de18 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -36,9 +36,9 @@
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0);	/* NAND ALE */
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* NAND CLE */
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index f547ce3..35c74ba 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c
@@ -100,16 +100,16 @@
 	       AT91_SMC_MODE_TDF_CYCLE(3),
 	       &smc->cs[3].mode);
 
-	ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+	ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy");
 	if (ret)
 		return ret;
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+	ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce");
 	if (ret)
 		return ret;
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	return 0;
 }
diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
index c0a5c51..c89ad0b 100644
--- a/board/calao/usb_a9263/usb_a9263.c
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -54,12 +54,12 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 
 	/* Configure RDY/BSY */
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_request(CFG_SYS_NAND_READY_PIN, "NAND ready/busy");
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable");
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
index 559fdd2..a5d79d8 100644
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c
@@ -117,11 +117,11 @@
 		AT91_SMC_MODE_TDF_CYCLE(2),
 		&smc->cs[3].mode);
 
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	/* Ready pin is optional. */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1);
 #endif
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index a3eee63..98043b0 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -84,10 +84,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 603384a..8951fae 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -28,8 +28,8 @@
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
 };
 
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index c0ab1a5..ef46353 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -135,13 +135,13 @@
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_4M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 16, BOOKE_PAGESZ_1M, 1),
 #endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index b02f649..481d3a5 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -84,15 +84,15 @@
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
@@ -113,15 +113,15 @@
 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 799900e..7f32128 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -47,15 +47,15 @@
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
@@ -76,15 +76,15 @@
 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
@@ -355,7 +355,7 @@
 		return;
 
     /* Change NAND Flash PGS/SPRZ configuration */
-	csor = CONFIG_SYS_NAND_CSOR;
+	csor = CFG_SYS_NAND_CSOR;
 	if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
 		csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
 
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index dfdc9f0..de68286 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -68,15 +68,15 @@
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
@@ -97,15 +97,15 @@
 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index ae81740..b70c198 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -73,15 +73,15 @@
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
@@ -105,15 +105,15 @@
 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
index debf571..2dcee79 100644
--- a/board/freescale/p1010rdb/law.c
+++ b/board/freescale/p1010rdb/law.c
@@ -10,7 +10,7 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index a262d5c..9cd46c9 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -22,9 +22,9 @@
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 7992666..aa7517a 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -68,7 +68,7 @@
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_256K, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
 
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 6bdfb35..8f3f484 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -13,8 +13,8 @@
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
 #endif
 };
 
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index e467c7a..2fd8a28 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -21,9 +21,9 @@
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 65cedd4..85d4132 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -67,9 +67,9 @@
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
 
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
index 04a4239..850ece0 100644
--- a/board/freescale/t102xrdb/law.c
+++ b/board/freescale/t102xrdb/law.c
@@ -23,8 +23,8 @@
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 
diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
index 97080eb..8fdff75 100644
--- a/board/freescale/t102xrdb/tlb.c
+++ b/board/freescale/t102xrdb/tlb.c
@@ -88,8 +88,8 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+#ifdef CFG_SYS_NAND_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
index 0f6b71a..2f00d80 100644
--- a/board/freescale/t104xrdb/law.c
+++ b/board/freescale/t104xrdb/law.c
@@ -23,8 +23,8 @@
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 9dcba79..8a3d674 100644
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -101,13 +101,13 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
index 40fdcf6..f97467e 100644
--- a/board/freescale/t208xqds/law.c
+++ b/board/freescale/t208xqds/law.c
@@ -25,8 +25,8 @@
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 #endif
 };
 
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index 1e501da..f27faf5 100644
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -116,13 +116,13 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c
index d3b263f..3ff4c77 100644
--- a/board/freescale/t208xrdb/law.c
+++ b/board/freescale/t208xrdb/law.c
@@ -25,8 +25,8 @@
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 #endif
 };
 
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 542ab1e..da03aad 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -116,13 +116,13 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
index 038f605..4385896 100644
--- a/board/freescale/t4rdb/law.c
+++ b/board/freescale/t4rdb/law.c
@@ -22,8 +22,8 @@
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index b927dd8..059449a 100644
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -98,13 +98,13 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c
index 3ab6760..2807c4e 100644
--- a/board/gardena/smart-gateway-at91sam/spl.c
+++ b/board/gardena/smart-gateway-at91sam/spl.c
@@ -53,10 +53,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCD);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c
index aa0f29f..b04a8e2 100644
--- a/board/keymile/kmcent2/law.c
+++ b/board/keymile/kmcent2/law.c
@@ -14,7 +14,7 @@
 	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 	SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
 /* other application LAW are not used in u-boot */
diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c
index dbd3b9b..095fc7e 100644
--- a/board/keymile/kmcent2/tlb.c
+++ b/board/keymile/kmcent2/tlb.c
@@ -76,7 +76,7 @@
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 
 	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 	/* QRIO */
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index fe52c7c..07febe6 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -66,10 +66,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 84926cd..76f62dd 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -62,10 +62,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 8d5825c..23b55e3 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -65,13 +65,13 @@
 
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 #endif
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 90fece7..d876280 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -40,8 +40,8 @@
 
 static void corvus_request_gpio(void)
 {
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
 	gpio_request(AT91_PIN_PD7, "d0");
 	gpio_request(AT91_PIN_PD8, "d1");
 	gpio_request(AT91_PIN_PA12, "d2");
@@ -110,8 +110,8 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOA);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 }
 
 #if defined(CONFIG_SPL_BUILD)
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index d500a62..ce6c877 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -42,8 +42,8 @@
 
 static void smartweb_request_gpio(void)
 {
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
 	gpio_request(AT91_PIN_PA26, "ena PHY");
 }
 
@@ -72,10 +72,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 
 static void smartweb_macb_hw_init(void)
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 6c44afb..47d3f6a 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -41,8 +41,8 @@
 
 static void taurus_request_gpio(void)
 {
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
 	gpio_request(AT91_PIN_PA25, "ena PHY");
 }
 
@@ -73,10 +73,10 @@
 	       &smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 
 #if defined(CONFIG_SPL_BUILD)
@@ -149,7 +149,7 @@
 		} else {
 			puts("erase spi flash sector 0\n");
 			spi_flash_erase(flash, 0,
-					CONFIG_SYS_NAND_U_BOOT_SIZE);
+					CFG_SYS_NAND_U_BOOT_SIZE);
 		}
 	}
 }
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 9b7ffee..b1e38c5 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_SYS_NAND_BASE)
+#if defined(CFG_SYS_NAND_BASE)
 #include <nand.h>
 #include <linux/errno.h>
 #include <linux/mtd/rawnand.h>
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 25a38be..dc45204 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -26,12 +26,12 @@
 	nand_init();
 
 	printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n",
-	       CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
-	       CONFIG_SYS_NAND_U_BOOT_DST);
+	       CONFIG_SYS_NAND_U_BOOT_OFFS, CFG_SYS_NAND_U_BOOT_SIZE,
+	       CFG_SYS_NAND_U_BOOT_DST);
 
 	nand_spl_load_image(spl_nand_get_uboot_raw_page(),
-			    CONFIG_SYS_NAND_U_BOOT_SIZE,
-			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+			    CFG_SYS_NAND_U_BOOT_SIZE,
+			    (void *)CFG_SYS_NAND_U_BOOT_DST);
 	spl_set_header_raw_uboot(spl_image);
 	nand_deselect();
 
diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
index 6bb4e17..69882a7 100644
--- a/doc/README.arm-relocation
+++ b/doc/README.arm-relocation
@@ -53,8 +53,8 @@
 d) this initialize CPU, RAM, ... and copy itself to RAM
    (this bin must fit in one page, so board_init_f()
     don;t fit in it ... )
-e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
-   starts this image @ CONFIG_SYS_NAND_U_BOOT_START
+e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and
+   starts this image @ CFG_SYS_NAND_U_BOOT_START
 f) u-boot code steps through board_init_f() and calculates
    the relocation address and copy itself to it
 
@@ -86,8 +86,8 @@
 
 - The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
   which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE	and loads
-  the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
-  @CONFIG_SYS_NAND_U_BOOT_START
+  the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution
+  @CFG_SYS_NAND_U_BOOT_START
 
 - This u-boot does no RAM init, nor CPU register setup. Just look
   where it has to copy and relocate itself to this address. If
diff --git a/doc/README.omap3 b/doc/README.omap3
index 208714a..3a1ac81 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -146,11 +146,11 @@
 When you require the SPL to read with BCH8 there are two more configs to
 change:
 
- * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
+ * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in
    GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
    arch/arm/include/asm/arch-omap3/omap_gpmc.h)
- * CONFIG_SYS_NAND_ECCSIZE must be 512
- * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
+ * CFG_SYS_NAND_ECCSIZE must be 512
+ * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
 
 Acknowledgements
 ================
diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index a90f32d..0b230cf 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst
@@ -54,7 +54,7 @@
 	CONFIG_SYS_NAND_PAGE_SIZE	number of main bytes in NAND page
 	CONFIG_SYS_NAND_OOBSIZE		number of OOB bytes in NAND page
 	CONFIG_SYS_NAND_BLOCK_SIZE	number of bytes in NAND erase-block
-	CONFIG_SYS_NAND_ECCPOS		ECC map for NAND page
+	CFG_SYS_NAND_ECCPOS		ECC map for NAND page
 	CONFIG_NAND_OMAP_ECCSCHEME	(refer doc/README.nand)
 
 Step-2: Flashing NAND via MMC/SD
diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c
index 83590a6..6ab3f1f 100644
--- a/drivers/mtd/nand/raw/am335x_spl_bch.c
+++ b/drivers/mtd/nand/raw/am335x_spl_bch.c
@@ -16,13 +16,13 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/rawnand.h>
 
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
 static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
-					CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+					CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL	(ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
 
 
 /*
@@ -155,8 +155,8 @@
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 	int i;
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	uint8_t *p = dst;
 	uint32_t data_pos = 0;
@@ -207,7 +207,7 @@
 	 */
 	mtd = nand_to_mtd(&nand_chip);
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
-		(void  __iomem *)CONFIG_SYS_NAND_BASE;
+		(void  __iomem *)CFG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 	if (nand_chip.select_chip)
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index a541af6..9fbb0b5 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -1227,16 +1227,16 @@
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
-		IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
-			     | CONFIG_SYS_NAND_MASK_CLE);
+		IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE
+			     | CFG_SYS_NAND_MASK_CLE);
 
 		if (ctrl & NAND_CLE)
-			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
+			IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE;
 		if (ctrl & NAND_ALE)
-			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
+			IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE;
 
-#ifdef CONFIG_SYS_NAND_ENABLE_PIN
-		at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+#ifdef CFG_SYS_NAND_ENABLE_PIN
+		at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN,
 				    !(ctrl & NAND_NCE));
 #endif
 		this->IO_ADDR_W = (void *) IO_ADDR_W;
@@ -1246,10 +1246,10 @@
 		writeb(cmd, this->IO_ADDR_W);
 }
 
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 static int at91_nand_ready(struct mtd_info *mtd)
 {
-	return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+	return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN);
 }
 #endif
 
@@ -1314,10 +1314,10 @@
 }
 
 #ifdef CONFIG_SPL_NAND_ECC
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
-		  CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+		  CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
 
 static int nand_read_page(int block, int page, void *dst)
 {
@@ -1325,8 +1325,8 @@
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	int i;
 	uint8_t *p = dst;
@@ -1415,7 +1415,7 @@
 	nand->read_buf = nand_read_buf;
 #endif
 	nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	nand->dev_ready = at91_nand_ready;
 #else
 	nand->dev_ready = at91_nand_wait_ready;
@@ -1439,8 +1439,8 @@
 	mtd = nand_to_mtd(&nand_chip);
 	mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
 	mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
-	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
-	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+	nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 #ifdef CONFIG_SPL_NAND_ECC
@@ -1464,11 +1464,11 @@
 
 #else
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
 
 int atmel_nand_chip_init(int devnum, ulong base_addr)
 {
@@ -1487,7 +1487,7 @@
 	nand->options = NAND_BUSWIDTH_16;
 #endif
 	nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	nand->dev_ready = at91_nand_ready;
 #endif
 	nand->chip_delay = 75;
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 54aed13..e4e144b 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -170,7 +170,7 @@
 	u_int32_t	ecc = 0;
 
 	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
-				CONFIG_SYS_NAND_CS - 2]));
+				CFG_SYS_NAND_CS - 2]));
 
 	return ecc;
 }
@@ -183,8 +183,8 @@
 	nand_davinci_readecc(mtd);
 
 	val = __raw_readl(&davinci_emif_regs->nandfcr);
-	val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
-	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+	val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
 	__raw_writel(val, &davinci_emif_regs->nandfcr);
 }
 
@@ -486,8 +486,8 @@
 		 */
 		val = __raw_readl(&davinci_emif_regs->nandfcr);
 		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
-		val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
-		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+		val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
 		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
 		__raw_writel(val, &davinci_emif_regs->nandfcr);
 		break;
@@ -794,8 +794,8 @@
 	struct mtd_info *mtd = nand_to_mtd(nand);
 	int ret;
 
-	nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
-	nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+	nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
 
 	davinci_nand_init(nand);
 
diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c
index f721428..690279c 100644
--- a/drivers/mtd/nand/raw/denali_spl.c
+++ b/drivers/mtd/nand/raw/denali_spl.c
@@ -25,9 +25,9 @@
 #define BANK(x) ((x) << 24)
 
 static void __iomem *denali_flash_mem =
-			(void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+			(void __iomem *)CFG_SYS_NAND_DATA_BASE;
 static void __iomem *denali_flash_reg =
-			(void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+			(void __iomem *)CFG_SYS_NAND_REGS_BASE;
 
 static const int flash_bank;
 static int page_size, oob_size, pages_per_block;
diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index 4f0acd7..7853c3f 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -819,12 +819,12 @@
 
 #ifndef CONFIG_NAND_FSL_ELBC_DT
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 
 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
-	CONFIG_SYS_NAND_BASE_LIST;
+	CFG_SYS_NAND_BASE_LIST;
 
 void board_nand_init(void)
 {
diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c
index e55b40f..26aaab08 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c
@@ -46,8 +46,8 @@
 #endif
 {
 	fsl_lbc_t *regs = LBC_BASE_ADDR;
-	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
-	const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+	uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
+	const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
 	const int block_shift = large ? 17 : 14;
 	const int block_size = 1 << block_shift;
 	const int page_size = large ? 2048 : 512;
@@ -143,8 +143,8 @@
 	 * Load U-Boot image from NAND into RAM
 	 */
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			    CONFIG_SYS_NAND_U_BOOT_SIZE,
-			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+			    CFG_SYS_NAND_U_BOOT_SIZE,
+			    (void *)CFG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -161,13 +161,13 @@
 	 * Clean d-cache and invalidate i-cache, to
 	 * make sure that no stale data is executed.
 	 */
-	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+	flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
 #endif
 
 	puts("transfering control\n");
 	/*
 	 * Jump to U-Boot image
 	 */
-	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 	(*uboot)();
 }
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index e5ff937..59de325 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -1053,12 +1053,12 @@
 	return 0;
 }
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 
 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
-	CONFIG_SYS_NAND_BASE_LIST;
+	CFG_SYS_NAND_BASE_LIST;
 
 void board_nand_init(void)
 {
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 4d11922..7d4b77d 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -110,7 +110,7 @@
 {
 	struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
 	struct fsl_ifc_runtime *ifc = NULL;
-	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+	uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
 	int page_size;
 	int port_size;
 	int pages_per_blk;
@@ -129,8 +129,8 @@
 	ifc = runtime_regs_address();
 
 	/* Get NAND Flash configuration */
-	csor = CONFIG_SYS_NAND_CSOR;
-	cspr = CONFIG_SYS_NAND_CSPR;
+	csor = CFG_SYS_NAND_CSOR;
+	cspr = CFG_SYS_NAND_CSPR;
 
 	port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
 
@@ -250,8 +250,8 @@
 	 * Load U-Boot image from NAND into RAM
 	 */
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			    CONFIG_SYS_NAND_U_BOOT_SIZE,
-			    (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+			    CFG_SYS_NAND_U_BOOT_SIZE,
+			    (uchar *)CFG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -270,7 +270,7 @@
 	 * Clean d-cache and invalidate i-cache, to
 	 * make sure that no stale data is executed.
 	 */
-	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+	flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
 #endif
 
 #ifdef CONFIG_CHAIN_OF_TRUST
@@ -279,11 +279,11 @@
 	 * calculate U-boot header address using U-boot header size.
 	 */
 #define CONFIG_U_BOOT_HDR_ADDR \
-		((CONFIG_SYS_NAND_U_BOOT_START + \
-		  CONFIG_SYS_NAND_U_BOOT_SIZE) - \
+		((CFG_SYS_NAND_U_BOOT_START + \
+		  CFG_SYS_NAND_U_BOOT_SIZE) - \
 		 CONFIG_U_BOOT_HDR_SIZE)
 	spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
-			   CONFIG_SYS_NAND_U_BOOT_START);
+			   CFG_SYS_NAND_U_BOOT_START);
 	/*
 	 * In case of failure in validation, spl_validate_uboot would
 	 * not return back in case of Production environment with ITS=1.
@@ -293,7 +293,7 @@
 	 */
 #endif
 
-	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 	uboot();
 }
 
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index a92c625..d795864 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -427,7 +427,7 @@
 	nand->ecc.hwctl = fsmc_enable_hwecc;
 	nand->cmd_ctrl = fsmc_nand_hwcontrol;
 	nand->IO_ADDR_R = nand->IO_ADDR_W =
-		(void  __iomem *)CONFIG_SYS_NAND_BASE;
+		(void  __iomem *)CFG_SYS_NAND_BASE;
 	nand->badblockbits = 7;
 
 	mtd = nand_to_mtd(nand);
diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c
index b838164..84564b2 100644
--- a/drivers/mtd/nand/raw/kmeter1_nand.c
+++ b/drivers/mtd/nand/raw/kmeter1_nand.c
@@ -10,8 +10,8 @@
 #include <linux/delay.h>
 #include <linux/mtd/rawnand.h>
 
-#define CONFIG_NAND_MODE_REG	(void *)(CONFIG_SYS_NAND_BASE + 0x20000)
-#define CONFIG_NAND_DATA_REG	(void *)(CONFIG_SYS_NAND_BASE + 0x30000)
+#define CONFIG_NAND_MODE_REG	(void *)(CFG_SYS_NAND_BASE + 0x20000)
+#define CONFIG_NAND_DATA_REG	(void *)(CFG_SYS_NAND_BASE + 0x30000)
 
 #define read_mode()	in_8(CONFIG_NAND_MODE_REG)
 #define write_mode(val)	out_8(CONFIG_NAND_MODE_REG, val)
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 3d6cb1d..f4f1b22 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -84,7 +84,7 @@
 };
 
 #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
-#define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
 
 /*
  * DMA Descriptors
@@ -187,7 +187,7 @@
 			DMAC_CHAN_DEST_AHB1;
 
 	/* CTRL descriptor entry for reading/writing Data */
-	ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
+	ctrl = (CFG_SYS_NAND_ECCSIZE / 4) |
 			DMAC_CHAN_SRC_BURST_4 |
 			DMAC_CHAN_DEST_BURST_4 |
 			DMAC_CHAN_SRC_WIDTH_32 |
@@ -241,7 +241,7 @@
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
 	 */
 
-	for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
+	for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) {
 		dmalist_cur = &dmalist[i * 2];
 		dmalist_cur_ecc = &dmalist[(i * 2) + 1];
 
@@ -337,9 +337,9 @@
 static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
 {
 	int i;
-	for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
-	     i += CONFIG_SYS_NAND_ECCBYTES) {
-		u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
+	for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES);
+	     i += CFG_SYS_NAND_ECCBYTES) {
+		u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES];
 		ce = ~(ce << 2) & 0xFFFFFF;
 		spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
 		spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
@@ -386,9 +386,9 @@
 	u16 data_offset = 0;
 
 	for (i = 0 ; i < ECCSTEPS ; i++) {
-		r += CONFIG_SYS_NAND_ECCBYTES;
-		c += CONFIG_SYS_NAND_ECCBYTES;
-		data_offset += CONFIG_SYS_NAND_ECCSIZE;
+		r += CFG_SYS_NAND_ECCBYTES;
+		c += CFG_SYS_NAND_ECCBYTES;
+		data_offset += CFG_SYS_NAND_ECCSIZE;
 
 		ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
 		if (ret1 < 0)
@@ -568,8 +568,8 @@
 	 * These values are predefined
 	 * for both small and large page NAND flash devices.
 	 */
-	lpc32xx_chip->ecc.size     = CONFIG_SYS_NAND_ECCSIZE;
-	lpc32xx_chip->ecc.bytes    = CONFIG_SYS_NAND_ECCBYTES;
+	lpc32xx_chip->ecc.size     = CFG_SYS_NAND_ECCSIZE;
+	lpc32xx_chip->ecc.bytes    = CFG_SYS_NAND_ECCBYTES;
 	lpc32xx_chip->ecc.strength = 1;
 
 	if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 2b8a132..fa903e3 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -50,7 +50,7 @@
 
 /* OOB placement block for use with hardware ecc generation */
 #if defined(MXC_NFC_V1)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
 static struct nand_ecclayout nand_hw_eccoob = {
 	.eccbytes = 5,
 	.eccpos = {6, 7, 8, 9, 10},
@@ -69,7 +69,7 @@
 };
 #endif
 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
 static struct nand_ecclayout nand_hw_eccoob = {
 	.eccbytes = 9,
 	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
@@ -1219,7 +1219,7 @@
 	if (is_16bit_nand())
 		this->options |= NAND_BUSWIDTH_16;
 
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
+#ifdef CFG_SYS_NAND_LARGEPAGE
 	host->pagesize_2k = 1;
 	this->ecc.layout = &nand_hw_eccoob2k;
 #else
diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c
index 0fea307..309e75d 100644
--- a/drivers/mtd/nand/raw/mxc_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxc_nand_spl.c
@@ -332,14 +332,14 @@
 	__attribute__((noreturn)) void (*uboot)(void);
 
 	/*
-	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
+	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must
 	 * be aligned to full pages
 	 */
 	if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			CONFIG_SYS_NAND_U_BOOT_SIZE,
-			(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+			CFG_SYS_NAND_U_BOOT_SIZE,
+			(uchar *)CFG_SYS_NAND_U_BOOT_DST)) {
 		/* Copy from NAND successful, start U-Boot */
-		uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+		uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 		uboot();
 	} else {
 		/* Unrecoverable error when copying from NAND */
diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c
index 14bca12..eacd99c 100644
--- a/drivers/mtd/nand/raw/nand.c
+++ b/drivers/mtd/nand/raw/nand.c
@@ -11,8 +11,8 @@
 #include <linux/mtd/concat.h>
 #include <linux/mtd/rawnand.h>
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 
 int nand_curr_device = -1;
@@ -21,7 +21,7 @@
 
 #if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
 #endif
 
 static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c
index ecd373e..7ac9bf4 100644
--- a/drivers/mtd/nand/raw/nand_spl_load.c
+++ b/drivers/mtd/nand/raw/nand_spl_load.c
@@ -20,8 +20,8 @@
 	 * Load U-Boot image from NAND into RAM
 	 */
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			CONFIG_SYS_NAND_U_BOOT_SIZE,
-			(void *)CONFIG_SYS_NAND_U_BOOT_DST);
+			CFG_SYS_NAND_U_BOOT_SIZE,
+			(void *)CFG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -36,6 +36,6 @@
 	/*
 	 * Jump to U-Boot image
 	 */
-	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 	(*uboot)();
 }
diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c
index 727861c..2f3af9e 100644
--- a/drivers/mtd/nand/raw/nand_spl_simple.c
+++ b/drivers/mtd/nand/raw/nand_spl_simple.c
@@ -10,13 +10,13 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/rawnand.h>
 
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
 static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
-					CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+					CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL	(ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
 
 
 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
@@ -139,8 +139,8 @@
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 	int i;
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	uint8_t *p = dst;
 
@@ -170,8 +170,8 @@
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 	int i;
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	uint8_t *p = dst;
 
@@ -212,7 +212,7 @@
 	 */
 	mtd = nand_to_mtd(&nand_chip);
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
-		(void  __iomem *)CONFIG_SYS_NAND_BASE;
+		(void  __iomem *)CFG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 #ifdef CONFIG_SPL_NAND_SOFTECC
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 8b9ff4d..b7d261d 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -407,7 +407,7 @@
 		cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
 
 		for (i = 0; i < cnt / 4; i++) {
-			*buf++ = readl(CONFIG_SYS_NAND_BASE);
+			*buf++ = readl(CFG_SYS_NAND_BASE);
 			len -= 4;
 		}
 	} while (len);
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index 13fd631..d4b40e8 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -812,7 +812,7 @@
 		return;
 	}
 
-	nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE;
 	err = vf610_nfc_nand_init(nfc, 0);
 	if (err)
 		printf("VF610 NAND init failed (err %d)\n", err);
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index a39fe5f..fc21af5 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -93,8 +93,8 @@
 #endif
 
 #ifdef CONFIG_CMD_NAND
-#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
-#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define CFG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #	define NAND_ALLOW_ERASE_ALL	1
 #endif
 
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index f073471..f7c09a2 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -94,8 +94,8 @@
 #	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #endif
 
-#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
-#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define CFG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #	define NAND_ALLOW_ERASE_ALL	1
 
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
index b080933..a5518d3 100644
--- a/include/configs/MCR3000.h
+++ b/include/configs/MCR3000.h
@@ -82,6 +82,6 @@
 /* Ethernet configuration part */
 
 /* NAND configuration part */
-#define CONFIG_SYS_NAND_BASE		0x0C000000
+#define CFG_SYS_NAND_BASE		0x0C000000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index bb93c28..c4cde1c 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -141,7 +141,7 @@
 /*
  * NAND Flash on the Local Bus
  */
-#define CONFIG_SYS_NAND_BASE	0xE0600000
+#define CFG_SYS_NAND_BASE	0xE0600000
 
 
 /* Vitesse 7385 */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 3448766..3288969 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -36,18 +36,18 @@
 
 #ifdef CONFIG_MTD_RAW_NAND
 #ifdef CONFIG_NXP_ESBC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CFG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CFG_SYS_NAND_U_BOOT_START	0x00200000
 #else
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START	(0x11000000)
 #elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xD0000000
-#define CONFIG_SYS_NAND_U_BOOT_START	0xD0000000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0xD0000000
+#define CFG_SYS_NAND_U_BOOT_START	0xD0000000
 #endif
 #endif
 #endif
@@ -167,23 +167,23 @@
 /* CFI for NOR Flash */
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
 
 #define CONFIG_MTD_PARTITION
 
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_2	/* RAL = 2 Bytes */ \
@@ -192,7 +192,7 @@
 				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
 
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
@@ -201,49 +201,49 @@
 				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 #endif
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 /* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
+#define CFG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
 					FTIM0_NAND_TWP(0x0C)   | \
 					FTIM0_NAND_TWCHT(0x04) | \
 					FTIM0_NAND_TWH(0x05)
-#define CONFIG_SYS_NAND_FTIM1		FTIM1_NAND_TADLE(0x1d) | \
+#define CFG_SYS_NAND_FTIM1		FTIM1_NAND_TADLE(0x1d) | \
 					FTIM1_NAND_TWBE(0x1d)  | \
 					FTIM1_NAND_TRR(0x07)   | \
 					FTIM1_NAND_TRP(0x0c)
-#define CONFIG_SYS_NAND_FTIM2		FTIM2_NAND_TRAD(0x0c) | \
+#define CFG_SYS_NAND_FTIM2		FTIM2_NAND_TRAD(0x0c) | \
 					FTIM2_NAND_TREH(0x05) | \
 					FTIM2_NAND_TWHRE(0x0f)
-#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+#define CFG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
+#define CFG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
+#define CFG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a)  | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3	0x0
+#define CFG_SYS_NAND_FTIM3	0x0
 #endif
 
 /* Set up IFC registers for boot location NOR/NAND */
 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
@@ -259,13 +259,13 @@
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 /* CPLD on IFC */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 08c1bcc..b9311fc 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -111,22 +111,22 @@
 
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CFG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#define CFG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
 
-#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CFG_SYS_NAND_BASE_LIST     {CFG_SYS_NAND_BASE}
 
 /* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+#define CFG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
 			       | OR_FCM_PGS	       /* Large Page*/ \
 			       | OR_FCM_CSCT \
 			       | OR_FCM_CST \
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 4b2327d..6eaa414 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -22,9 +22,9 @@
 #define BOOT_PAGE_OFFSET		0x27000
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0x30000000
+#define CFG_SYS_NAND_U_BOOT_START	0x30000000
 #endif
 
 #ifdef CONFIG_SPIFLASH
@@ -189,21 +189,21 @@
 #endif
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
 #if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -211,7 +211,7 @@
 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
@@ -221,30 +221,30 @@
 #endif
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
@@ -262,14 +262,14 @@
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index e7d82bf..a9e6cfa 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -25,13 +25,13 @@
  * HDR would be appended at end of image and copied to DDR along
  * with U-Boot image.
  */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
+#define CFG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
 					 CONFIG_U_BOOT_HDR_SIZE)
 #else
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #endif
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
+#define CFG_SYS_NAND_U_BOOT_DST	0x30000000
+#define CFG_SYS_NAND_U_BOOT_START	0x30000000
 #endif
 
 #ifdef CONFIG_SPIFLASH
@@ -178,17 +178,17 @@
 #define CONFIG_SYS_CS2_FTIM3		0x0
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -197,30 +197,30 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
@@ -238,14 +238,14 @@
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 0819550..47f4990 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -29,9 +29,9 @@
 #define BOOT_PAGE_OFFSET		0x27000
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CFG_SYS_NAND_U_BOOT_START	0x00200000
 #endif
 
 #ifdef CONFIG_SPIFLASH
@@ -166,17 +166,17 @@
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
@@ -185,30 +185,30 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)    | \
 					FTIM0_NAND_TWCHT(0x07)  | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)   | \
 					FTIM1_NAND_TRR(0x0e)    | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
 					FTIM2_NAND_TREH(0x0a)   | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
@@ -242,14 +242,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 75d9200..111f2e6 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -24,9 +24,9 @@
 #define BOOT_PAGE_OFFSET		0x27000
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CFG_SYS_NAND_U_BOOT_START	0x00200000
 #endif
 
 #ifdef CONFIG_SPIFLASH
@@ -142,17 +142,17 @@
 #define CONFIG_SYS_CS2_FTIM3		0x0
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
@@ -161,30 +161,30 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)    | \
 					FTIM0_NAND_TWCHT(0x07)  | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)   | \
 					FTIM1_NAND_TRR(0x0e)    | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
 					FTIM2_NAND_TREH(0x0a)   | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
@@ -202,14 +202,14 @@
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 #define CONFIG_HWCONFIG
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index cfd9cb3..b823298 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -197,17 +197,17 @@
 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
@@ -216,30 +216,30 @@
 				| CSOR_NAND_PB(128))	/*Page Per Block = 128*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
@@ -257,14 +257,14 @@
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 8eefaf2..13b1ff3 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -171,7 +171,7 @@
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -179,8 +179,8 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 #endif /* !CONFIG_MTD_RAW_NAND */
 
 /* USB Device Firmware Update support */
diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h
index 7fa1847..cb649b5 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -91,7 +91,7 @@
 #define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS  {   2,   3,   4,   5,   6,   7,   8,   9, \
+#define CFG_SYS_NAND_ECCPOS  {   2,   3,   4,   5,   6,   7,   8,   9, \
 			 10,  11,  12,  13,  14,  15,  16,  17,  18,  19, \
 			 20,  21,  22,  23,  24,  25,  26,  27,  28,  29, \
 			 30,  31,  32,  33,  34,  35,  36,  37,  38,  39, \
@@ -113,8 +113,8 @@
 			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
 			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
 			}
-#define CONFIG_SYS_NAND_ECCSIZE         512
-#define CONFIG_SYS_NAND_ECCBYTES        26
+#define CFG_SYS_NAND_ECCSIZE         512
+#define CFG_SYS_NAND_ECCBYTES        26
 #define MTDIDS_DEFAULT                  "nand0=nand.0"
 
 #endif /* CONFIG_MTD_RAW_NAND */
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 3952783..b7b1cb0 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -95,7 +95,7 @@
 /* NAND support */
 
 /* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -103,7 +103,7 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif	/* ! __CONFIG_IGEP003X_H */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 2eb7a51..a9a4c8d 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -16,16 +16,16 @@
 
 /* Board NAND Info. */
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, 10, \
+#define CFG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, 10, \
 					 11, 12, 13, 14, 16, 17, 18, 19, 20, \
 					 21, 22, 23, 24, 25, 26, 27, 28, 30, \
 					 31, 32, 33, 34, 35, 36, 37, 38, 39, \
 					 40, 41, 42, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56 }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	13
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	13
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 /* NAND block size is 128 KiB.  Synchronize these values with
  * corresponding Device Tree entries in Linux:
  *  MLO(SPL)             4 * NAND_BLOCK_SIZE = 512 KiB  @ 0x000000
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index fc82a8c..a0951fb 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -120,7 +120,7 @@
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
 				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
 				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
 				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -142,8 +142,8 @@
 			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
 			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
 			}
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	26
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	26
 #define NANDARGS \
 	"nandargs=setenv bootargs console=${console} " \
 		"${optargs} " \
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 60b4737..574bfe3 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -43,11 +43,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 #endif
 
 /* USB */
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index d80a686..2c785ad 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -24,13 +24,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CFG_SYS_NAND_BASE			0x40000000
 /* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC15
+#define CFG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PC15
 
 #endif
 
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 89a8e43..bba8574 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -150,13 +150,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PA22
 #endif
 
 /* USB */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 55edd70..3ce264a 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -20,23 +20,23 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PC8
 
 #endif
 
 #ifdef CONFIG_SD_BOOT
 #elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 #endif
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 00f5774..5e3ded2 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -21,11 +21,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
-#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
+#define CFG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
+#define CFG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 0a512c2..b79c8ba 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -25,13 +25,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PB6
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD17
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PB6
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PD17
 
 #endif
 
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index b8a14d5..40ea4ed 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -27,13 +27,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 #endif
 
 /* SPL */
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index f4161d7..31f107a 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -195,7 +195,7 @@
 #ifndef CONFIG_NOR_BOOT
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -203,9 +203,9 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 #endif
 #endif
 
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index fdbcbf5..bfa076b 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -108,7 +108,7 @@
 
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -116,7 +116,7 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif	/* ! __CONFIG_CHILIBOARD_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 874c0eb..2cb09fa 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -128,7 +128,7 @@
 #include <config_distro_bootcmd.h>
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 /* APBH DMA is required for NAND support */
 
 /* Ethernet */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index f0fbbe2..9061eba 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -22,9 +22,9 @@
 #endif
 
 /* NAND support */
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index d7e181b..afe8bad 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -122,8 +122,8 @@
 
 #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
 /* NAND stuff */
-/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
-#define CONFIG_SYS_NAND_BASE		-1
+/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */
+#define CFG_SYS_NAND_BASE		-1
 #endif
 
 /* USB Configs */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 5c7a9f2..f9bf849 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -166,7 +166,7 @@
 
 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 #endif
 
 /* USB Configs */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 3e7c0c0..9d44e67 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -37,13 +37,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PC8
 #endif
 
 /* DFU class support */
@@ -53,13 +53,13 @@
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 5a5c65d..f8ba4e8 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -107,21 +107,21 @@
  * Flash & Environment
  */
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_CS		3
-#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE		0x10
-#define CONFIG_SYS_NAND_MASK_ALE		0x8
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x40000
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_ECCPOS		{				\
+#define CFG_SYS_NAND_CS		3
+#define CFG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE		0x10
+#define CFG_SYS_NAND_MASK_ALE		0x8
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x40000
+#define CFG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS		{				\
 				24, 25, 26, 27, 28, \
 				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 				59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	10
 #endif
 
 #ifdef CONFIG_MTD_NOR_FLASH
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 4236612..5244b9c 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -35,8 +35,8 @@
 /*
  * NAND controller
  */
-#define CONFIG_SYS_NAND_BASE		SLC_NAND_BASE
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE		SLC_NAND_BASE
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 /*
  * NAND chip timings
@@ -79,10 +79,10 @@
  */
 
 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x60000
 
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index d45115b..4641059 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -100,12 +100,12 @@
 /* Defines for SPL */
 
 /* NAND boot config */
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
 						10, 11, 12, 13}
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	3
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x200000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 6cf716e..93201be 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -75,15 +75,15 @@
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
 					 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 #endif /* !CONFIG_MTD_RAW_NAND */
 
 /* Parallel NOR Support */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index 75322a3..6cae663 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -14,10 +14,10 @@
 
 #include "siemens-am33x-common.h"
 /* NAND specific changes for etamin due to different page size */
-#undef CONFIG_SYS_NAND_ECCPOS
+#undef CFG_SYS_NAND_ECCPOS
 
 #define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
-#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
 				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
 				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
 				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -40,14 +40,14 @@
 			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
 			}
 
-#undef CONFIG_SYS_NAND_ECCSIZE
-#undef CONFIG_SYS_NAND_ECCBYTES
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#undef CFG_SYS_NAND_ECCSIZE
+#undef CFG_SYS_NAND_ECCBYTES
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
 
-#define CONFIG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
-#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
-					CONFIG_SYS_NAND_BASE2}
+#define CFG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
+#define CFG_SYS_NAND_BASE_LIST       {CFG_SYS_NAND_BASE, \
+					CFG_SYS_NAND_BASE2}
 
 #define DDR_PLL_FREQ	303
 
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index a18920d..f19e12d 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -37,12 +37,12 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
 #endif
 
 /* JFFS2 */
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 3d62efb..ba09831 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -22,13 +22,13 @@
 #define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
 
 /* NAND flash */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
+#define CFG_SYS_NAND_MASK_ALE	BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE	BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 
 /* SPL */
 
@@ -37,8 +37,8 @@
 #define CONFIG_SYS_MCKR			0x1301
 #define CONFIG_SYS_MCKR_CSS		0x1302
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0xa0000
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	0xa0000
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
 #endif
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 232f786..974dff8 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -96,7 +96,7 @@
  * NAND
  */
 #define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
-#define CONFIG_SYS_NAND_BASE		0xd8000000
+#define CFG_SYS_NAND_BASE		0xd8000000
 #define CONFIG_MXC_NAND_HWECC
 
 /*
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index f52367c..e430efa 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h
@@ -126,8 +126,8 @@
 
 /* NAND */
 #ifdef CONFIG_NAND_MXS
-# define CONFIG_SYS_NAND_BASE		0x40000000
-# define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+# define CFG_SYS_NAND_BASE		0x40000000
+# define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 /* MTD device */
 #endif
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 008fc07..7760c8c 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -116,8 +116,8 @@
 /* Environment organization */
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x40000000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_BASE           0x40000000
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h
index 46a96f1..d42eb75 100644
--- a/include/configs/imx6ulz_smm_m2.h
+++ b/include/configs/imx6ulz_smm_m2.h
@@ -72,6 +72,6 @@
 
 /* NAND */
 
-#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CFG_SYS_NAND_BASE		0x20000000
 
 #endif
diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h
index a2323bd..a768ff3 100644
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h
@@ -44,6 +44,6 @@
 
 /* NAND */
 
-#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CFG_SYS_NAND_BASE		0x20000000
 
 #endif /* __IMX8MN_BSH_SMM_S2_H */
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index 5be4609..8f2b474 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -166,7 +166,7 @@
 #ifdef CONFIG_NAND_MXS
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CFG_SYS_NAND_BASE           0x20000000
 #endif /* CONFIG_NAND_MXS */
 
 #endif /* __IMX8MP_RSB3720_H */
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 181ed1b..a658cbc 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -59,7 +59,7 @@
 
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
+#define CFG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
 #endif
 
 /*
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index 0613b77..d883b18 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -77,17 +77,17 @@
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 
 /* NAND Flash Definitions */
-#define CONFIG_SYS_NAND_BASE		0x68000000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x68000000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
 				CSPR_PORT_SIZE_8 | \
 				CSPR_TE | \
 				CSPR_MSEL_NAND | \
 				CSPR_V)
-#define CONFIG_SYS_NAND_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR		(CSOR_NAND_ECC_ENC_EN \
+#define CFG_SYS_NAND_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR		(CSOR_NAND_ECC_ENC_EN \
 					| CSOR_NAND_ECC_DEC_EN \
 					| CSOR_NAND_ECC_MODE_4 \
 					| CSOR_NAND_RAL_3 \
@@ -97,29 +97,29 @@
 					| CSOR_NAND_TRHZ_40 \
 					| CSOR_NAND_BCTLD)
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x3) | \
 					FTIM0_NAND_TWP(0x8) | \
 					FTIM0_NAND_TWCHT(0x3) | \
 					FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1e) | \
 					FTIM1_NAND_TWBE(0x1e) | \
 					FTIM1_NAND_TRR(0x6) | \
 					FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x9) | \
 					FTIM2_NAND_TREH(0x5) | \
 					FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3		(FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3		(FTIM3_NAND_TWW(0x1e))
 
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 /* QRIO FPGA Definitions */
 #define CONFIG_SYS_QRIO_BASE		0x70000000
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 2e1459e..51ee686 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -231,18 +231,18 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 
 /* NAND Flash on IFC CS1*/
-#define CONFIG_SYS_NAND_BASE		0xfa000000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xfa000000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0f)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0f)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
 				CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
 				0x00000010 |	   /* drive TE high */\
 				CSPR_MSEL_NAND |   /* MSEL = NAND */\
 				CSPR_V)		   /* valid */
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024) /* 64kB */
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024) /* 64kB */
 
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
 				CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
 				CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
 				CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
@@ -253,30 +253,30 @@
 				CSOR_NAND_BCTLD)       /**/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x3) | \
 				FTIM0_NAND_TWP(0x8) | \
 				FTIM0_NAND_TWCHT(0x3) | \
 				FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x1e) | \
 				FTIM1_NAND_TWBE(0x1e) | \
 				FTIM1_NAND_TRR(0x6) | \
 				FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x9) | \
 				FTIM2_NAND_TREH(0x5) | \
 				FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x1e))
 
-#define CONFIG_SYS_CSPR1_EXT	CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1	CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1	CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1	CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0	CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1	CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2	CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3	CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT	CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1	CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1	CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1	CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0	CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1	CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2	CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3	CFG_SYS_NAND_FTIM3
 
 /* More NAND Flash Params */
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 /* QRIO on IFC CS2 */
 #define CONFIG_SYS_QRIO_BASE		0xfb000000
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index d6b60d8..b954029 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -12,7 +12,7 @@
 #define CONFIG_NAND_ECC_BCH
 #define CONFIG_NAND_KMETER1
 #define NAND_MAX_CHIPS				1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 
 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
 #define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 926c858..7d89b53 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -11,9 +11,9 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 #endif
 
@@ -70,17 +70,17 @@
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
 
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -88,20 +88,20 @@
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3           0x0
+#define CFG_SYS_NAND_FTIM3           0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #endif
 
 /*
@@ -156,14 +156,14 @@
 #endif
 
 #if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
@@ -205,14 +205,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 8c19468..4736784 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -59,8 +59,8 @@
 
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 #ifdef CONFIG_NXP_ESBC
 #define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index d207e47..2126370 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -79,17 +79,17 @@
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
 
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -97,25 +97,25 @@
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3           0x0
+#define CFG_SYS_NAND_FTIM3           0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #endif
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
 #endif
 
 #if defined(CONFIG_TFABOOT) || \
@@ -188,14 +188,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
@@ -206,14 +206,14 @@
 #define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
 #else
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
@@ -255,14 +255,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 206de7e..51667f2 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -51,16 +51,16 @@
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -68,24 +68,24 @@
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
 #endif
 
 /*
@@ -126,24 +126,24 @@
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #else
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
@@ -163,14 +163,14 @@
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
 
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 #endif
 
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 7e1a724..07ec2c9 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -59,8 +59,8 @@
 
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 #endif
 
 /* GPIO */
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 48408f2..8402eac 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -14,16 +14,16 @@
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -31,31 +31,31 @@
 				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 /* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
 /* EEPROM */
 #define I2C_RETIMER_ADDR			0x18
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 037d462..d51209c 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -95,17 +95,17 @@
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
 
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -113,25 +113,25 @@
 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3           0x0
+#define CFG_SYS_NAND_FTIM3           0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #endif
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #endif
 
 #if defined(CONFIG_TFABOOT) || \
@@ -204,14 +204,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
@@ -222,14 +222,14 @@
 #define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
 #else
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
@@ -271,14 +271,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 7693493..0df6891 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -19,16 +19,16 @@
 #define CONFIG_SYS_UBOOT_BASE		0x40100000
 #endif
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -36,20 +36,20 @@
 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 /*
@@ -78,14 +78,14 @@
 #define CONFIG_SYS_CPLD_FTIM3		0x0
 
 /* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 73e4ac3..dec661d 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -88,8 +88,8 @@
 #define QIXIS_BASE_PHYS_EARLY			0xC000000
 
 
-#define CONFIG_SYS_NAND_BASE			0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
+#define CFG_SYS_NAND_BASE			0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS		0x30000000
 
 
 /* MC firmware */
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 3a2fba6..ae45207 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -69,14 +69,14 @@
 #endif
 #endif
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -85,20 +85,20 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
@@ -174,14 +174,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
@@ -193,14 +193,14 @@
 #define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
 #else
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
@@ -230,14 +230,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index e2ae302..2ca1384 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -53,14 +53,14 @@
 #endif
 #endif
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -69,20 +69,20 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
@@ -132,14 +132,14 @@
 
 #if defined(CONFIG_TFABOOT) || \
 	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 53a3af1..d899720 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -81,8 +81,8 @@
 #define QIXIS_SDID_MASK				0x07
 #define QIXIS_ESDHC_NO_ADAPTER			0x7
 
-#define CONFIG_SYS_NAND_BASE			0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
+#define CFG_SYS_NAND_BASE			0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS		0x30000000
 
 /* MC firmware */
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
@@ -129,8 +129,8 @@
 	" 0x580e00000 \0"
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_U_BOOT_DST	0x80400000
+#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
 #endif
 
 #include <asm/arch/soc.h>
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index e601987..d9e11cc 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -70,14 +70,14 @@
 					 CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -86,20 +86,20 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define QIXIS_LBMAP_SWITCH		0x06
@@ -163,16 +163,16 @@
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
 #endif
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
@@ -194,14 +194,14 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 382d516..086c469 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -67,14 +67,14 @@
 					 CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -83,20 +83,20 @@
 				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
 					FTIM0_NAND_TWP(0x30)   | \
 					FTIM0_NAND_TWCHT(0x0e) | \
 					FTIM0_NAND_TWH(0x14))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
 					FTIM1_NAND_TWBE(0xab)  | \
 					FTIM1_NAND_TRR(0x1c)   | \
 					FTIM1_NAND_TRP(0x30))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
 					FTIM2_NAND_TREH(0x14) | \
 					FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define QIXIS_LBMAP_SWITCH		0x06
@@ -146,16 +146,16 @@
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
@@ -166,14 +166,14 @@
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 #endif
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 3652241..1734f32 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -44,10 +44,10 @@
  * NAND
  */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CFG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_LARGEPAGE
 #define CONFIG_MXC_NAND_HWECC
 #endif
 
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 30267e2..cd3910e 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -52,11 +52,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3 /* 0x40000000 */
-# define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
-# define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
-# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+# define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3 /* 0x40000000 */
+# define CFG_SYS_NAND_MASK_ALE		(1 << 21)
+# define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+# define CFG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CFG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* hw-controller addresses */
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index 61570b7..8176566 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h
@@ -36,7 +36,7 @@
 #define CFG_SYS_FSL_USDHC_NUM	2
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CFG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 0d9764e..a41e428 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -86,7 +86,7 @@
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC3_BASE_ADDR
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CFG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 2a97d2f..af17658 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -93,7 +93,7 @@
  */
 #ifdef CONFIG_NAND_MXS
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 #endif
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index e861038..9d6b3d4 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -83,7 +83,7 @@
 
 /* NAND */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CFG_SYS_NAND_BASE		0x60000000
 #endif
 
 /* OCOTP */
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index a777305..e18d16c 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -30,7 +30,7 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index ccc203f..2a52885 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h
@@ -31,7 +31,7 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index d46ca33..0890f51 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -21,10 +21,10 @@
 /* NAND */
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
                                          10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE         512
-#define CONFIG_SYS_NAND_ECCBYTES        3
+#define CFG_SYS_NAND_ECCSIZE         512
+#define CFG_SYS_NAND_ECCBYTES        3
 /* NAND: SPL falcon mode configs */
 #endif /* CONFIG_MTD_RAW_NAND */
 
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 77629d7..6eec955 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -26,10 +26,10 @@
 /* NAND */
 #if defined(CONFIG_MTD_RAW_NAND)
 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
                                          10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE         512
-#define CONFIG_SYS_NAND_ECCBYTES        3
+#define CFG_SYS_NAND_ECCSIZE         512
+#define CFG_SYS_NAND_ECCBYTES        3
 #endif /* CONFIG_MTD_RAW_NAND */
 
 #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 97f47ea..10f6ba6 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -70,14 +70,14 @@
 #define CONFIG_SYS_ONENAND_BLOCK_SIZE	(128*1024)
 
 /* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
 					 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 7c0bdcb..6001037 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -17,15 +17,15 @@
 /* Board NAND Info. */
 #ifdef CONFIG_MTD_RAW_NAND
 						  /* NAND devices */
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+#define CFG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
 					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
 					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
 					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
 					 52, 53, 54, 55, 56}
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	13
 #endif
 
 /* Environment information */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index d9f70c7..81ca68d 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -105,21 +105,21 @@
  * Flash & Environment
  */
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_CS		3
-#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE	0x10
-#define CONFIG_SYS_NAND_MASK_ALE	0x8
+#define CFG_SYS_NAND_CS		3
+#define CFG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE	0x10
+#define CFG_SYS_NAND_MASK_ALE	0x8
 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_ECCPOS		{				\
+#define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define CFG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS		{				\
 				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
 				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
 				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
 				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	10
 #endif
 
 /*
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 778bf51..38f360b5 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -98,13 +98,13 @@
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START	(0x11000000)
 #elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_START	0xf8f80000
 #endif /* not CONFIG_TPL_BUILD */
 #endif
 
@@ -207,22 +207,22 @@
 
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 	| BR_PS_8	/* Port Size = 8 bit */ \
 	| BR_MS_FCM	/* MSEL = FCM */ \
 	| BR_V)	/* valid */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
+#define CFG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
 	| OR_FCM_PGS	/* Large Page*/ \
 	| OR_FCM_CSCT \
 	| OR_FCM_CST \
@@ -231,7 +231,7 @@
 	| OR_FCM_TRLX \
 	| OR_FCM_EHTR)
 #else
-#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
+#define CFG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
 	| OR_FCM_CSCT \
 	| OR_FCM_CST \
 	| OR_FCM_CHT \
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index dea8712..bc04c50 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -42,7 +42,7 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index 2bdae8a..817fabf 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -44,7 +44,7 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
index f69d8ad..c5817b0 100644
--- a/include/configs/phycore_am335x_r2.h
+++ b/include/configs/phycore_am335x_r2.h
@@ -84,7 +84,7 @@
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -92,8 +92,8 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif /* !CONFIG_MTD_RAW_NAND */
 
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 6a89fb1..adb2f43 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -129,13 +129,13 @@
 #define PHYS_SDRAM_SIZE				0x04000000	/* 64 megs */
 
 /* NAND flash */
-#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CFG_SYS_NAND_BASE			0x40000000
 /* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
+#define CFG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
 
 /* NOR flash */
 #define PHYS_FLASH_1				0x10000000
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index c56db4d..4352a24 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -146,13 +146,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
 
 #endif
 
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 7d3a326..a7deaa3 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -25,13 +25,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		BIT(21)
+#define CFG_SYS_NAND_MASK_ALE		BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD3
+#define CFG_SYS_NAND_MASK_CLE		BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PD3
 #endif
 
 #ifdef CONFIG_NAND_BOOT
@@ -44,11 +44,11 @@
 
 #ifdef CONFIG_SD_BOOT
 #elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 #endif
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index ebf5467..f9decb2 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h
@@ -58,8 +58,8 @@
 
 /* nand driver parameters */
 #ifdef CONFIG_TARGET_PRESIDIO_ASIC
-	#define CONFIG_SYS_NAND_BASE            CONFIG_SYS_FLASH_BASE
-	#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
+	#define CFG_SYS_NAND_BASE            CONFIG_SYS_FLASH_BASE
+	#define CFG_SYS_NAND_BASE_LIST       { CFG_SYS_NAND_BASE }
 #endif
 
 #endif /* __PRESIDIO_ASIC_H */
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index 70c6ec5..7c5bfdb 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -28,11 +28,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
-#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#define CFG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_MASK_ALE	BIT(21)
+#define CFG_SYS_NAND_MASK_CLE	BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 #endif
 
 #endif
diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h
index 9281c7c..09cc4dd 100644
--- a/include/configs/sama5d2_ptc_ek.h
+++ b/include/configs/sama5d2_ptc_ek.h
@@ -21,11 +21,11 @@
 
 /* NAND Flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
+#define CFG_SYS_NAND_MASK_ALE	BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
+#define CFG_SYS_NAND_MASK_CLE	BIT(22)
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index eed688d..1c9af9b 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -29,11 +29,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CFG_SYS_NAND_BASE		0x60000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index b05fa59..afb9b9a 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -38,11 +38,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CFG_SYS_NAND_BASE		0x60000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index c4552c2..0daadec 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -17,11 +17,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x80000000
+#define CFG_SYS_NAND_BASE		0x80000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index d719992..d59899f 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -17,11 +17,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x80000000
+#define CFG_SYS_NAND_BASE		0x80000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index dd247d2..d071f59 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -48,7 +48,7 @@
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -56,10 +56,10 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 /*
  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
@@ -361,7 +361,7 @@
 
  */
 
-#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */
+#define CFG_SYS_NAND_BASE		(0x08000000)	/* physical address */
 							/* to access nand at */
 							/* CS0 */
 #endif
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 5460c12..7c8f167 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -54,11 +54,11 @@
  */
 
 /* NAND flash settings */
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 
 /* serial console */
 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
@@ -92,13 +92,13 @@
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index 29462c5..7c35c91 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -29,11 +29,11 @@
 /* Mem test settings */
 
 /* NAND Flash */
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC8
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC8
 
 /* UARTs/Serial console */
 
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 704a714..70a24ed 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -71,8 +71,8 @@
  * NAND Support
  */
 #ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
-#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
+#define CFG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
+#define CFG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
 #endif
 
 /*
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 3c978f5..388a4e4 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -99,7 +99,7 @@
 #define CONFIG_SYS_FPGA_BASE		0xc0000000
 #define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
 
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
+#define CFG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
 
 /* LIME GDC */
 #define CONFIG_SYS_LIME_BASE		0xc8000000
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index f130c63..dd1fe0a 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -54,11 +54,11 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 #endif
 
 #if defined(CONFIG_BOARD_TAURUS)
@@ -126,13 +126,13 @@
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 82add65..efd3a0d 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -42,13 +42,13 @@
  * GPMC NAND block.  We support 1 device and the physical address to
  * access CS0 at is 0x8000000.
  */
-#define CONFIG_SYS_NAND_BASE		0x8000000
+#define CFG_SYS_NAND_BASE		0x8000000
 
 /* NAND: SPL related configs */
 
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -56,8 +56,8 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 /* SPL */
 /* Defines for SPL */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 05536c3..b289b9e 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -123,7 +123,7 @@
 /* General parts of the framework, required. */
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 #endif
 #endif /* !CONFIG_NOR_BOOT */
 
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index b8b4b28..a4a45fa 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -62,12 +62,12 @@
 /* EEPROM definitions */
 
 /* NAND Configuration */
-#define CONFIG_SYS_NAND_MASK_CLE		0x4000
-#define CONFIG_SYS_NAND_MASK_ALE		0x2000
-#define CONFIG_SYS_NAND_CS			2
+#define CFG_SYS_NAND_MASK_CLE		0x4000
+#define CFG_SYS_NAND_MASK_ALE		0x2000
+#define CFG_SYS_NAND_CS			2
 
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
+#define CFG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_BASE_LIST		{ 0x30000000, }
 
 #define DFU_ALT_INFO_MMC \
 	"dfu_alt_info_mmc=" \
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index 44706c7..d34042a 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -16,8 +16,8 @@
  * access CS0 at is 0x8000000.
  */
 #ifdef CONFIG_MTD_RAW_NAND
-#ifndef CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE		0x8000000
+#ifndef CFG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x8000000
 #endif
 #endif
 
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 47f3c81..6cc443c 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -55,7 +55,7 @@
 /* SPL */
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_BASE		0x30000000
+#define CFG_SYS_NAND_BASE		0x30000000
 #endif
 
 /* Now bring in the rest of the common code. */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 32b47db..a57ecff 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -40,8 +40,8 @@
 #define CONFIG_SYS_TIMER_RATE			1000000
 #endif
 
-#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
-#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
+#define CFG_SYS_NAND_REGS_BASE			0x68100000
+#define CFG_SYS_NAND_DATA_BASE			0x68000000
 
 /*
  * Network Configuration
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 44eaeda..2cdc3fb 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -33,13 +33,13 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 7e3d347..215149a 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -14,7 +14,7 @@
 /* NAND support */
 
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+#define CFG_SYS_NAND_BASE		NFC_BASE_ADDR
 
 /* Dynamic MTD partition support */
 #endif
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index a7c805c..054eb89 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -43,7 +43,7 @@
 
 /* driver configuration */
 #define CONFIG_SYS_MAX_NAND_CHIPS 1
-#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
+#define CFG_SYS_NAND_BASE MLC_NAND_BASE
 
 /*
  * GPIO
@@ -63,8 +63,8 @@
 /* SPL will use serial */
 /* SPL will load U-Boot from NAND offset 0x40000 */
 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST   CONFIG_TEXT_BASE
 
 /*
  * Include SoC specific configuration