commit b3d07d7193ce2444ab9cbfc160fd6211f5087188
author Tang Yuantian <Yuantian.Tang@freescale.com> Thu Oct 09 16:11:37 2014 +0800
committer York Sun <yorksun@freescale.com> Wed Nov 19 12:56:14 2014 -0800
tree 1405d33e76a354f66c51848a3b6da10454ab30a2
parent f3cc6b7b9b30bfed604e21d099f2bc86d9945734

arm: ls102xa: Fixed a register definition error

There are 8 SCFG_SPARECR registers in SCFG memory block, not one.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b5db720 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,7 +182,7 @@
 	u32 etsecmcr;
 	u32 sdhciovserlcr;
 	u32 resv14[61];
-	u32 sparecr;
+	u32 sparecr[8];
 };
 
 /* Clocking */