tree 1ddee2e418e9629888437c4a90146aa0bff34557
parent 3a29fe9f1b86cf015ce262e34873aebdc029b40c
author Valentin Longchamp <valentin.longchamp@keymile.com> 1447754011 +0100
committer Tom Rini <trini@konsulko.com> 1447878535 -0500

powerpc/km8321: define CONFIG_SYS_DDRCDR

On the km8321 boards is CONFIG_SYS_DDRCDR not defined, which leads to
the DDRCDR not being configured at startup and still containing the
reset value.

The required settings for our km8321 hardware designs are different than
the reset value and must be set with CONFIG_SYS_DDRCDR, that is used
by mpc83xx's cpu_init_f function at early CPU initialization.

The important settings are the DDR2 internal voltage level and the
half-strength "drivers".

In our case where the DRAM chips are soldered on board and the routing
for these signals under control, half-strength is sufficient as a few
measurements done in the lasts have shown. Since all the hardware
qualification tests have been performed with half strength, the nominal
strength settings are removed in favor of the default reset half
strength settings.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>