| commit | b20b19eabcb719fada497d20fbec78b9ed1ebec4 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Wed Jul 18 13:27:24 2018 +0200 |
| committer | Michal Simek <michal.simek@xilinx.com> | Tue Oct 16 14:58:45 2018 +0200 |
| tree | 5c79372be4b2ccad94cee1721ca8de0325a2c9fa | |
| parent | f707b5a7fef98a48ca9dee2fbd324c5c44f9b963 [diff] |
arm: zynq: Enable FIT fpga loading in SPL for zc706 Enable loading FPGA from FIT image in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>