diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index d58ed43..3c82e99 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -58,6 +58,7 @@
 #define USDHC1_AIPS2_SLOT		(56)
 #define RGPIO2P0_AIPS0_SLOT		(15)
 #define RGPIO2P1_AIPS2_SLOT		(15)
+#define SNVS_AIPS2_SLOT			(35)
 #define IOMUXC0_AIPS0_SLOT		(61)
 #define OCOTP_CTRL_AIPS1_SLOT		(38)
 #define OCOTP_CTRL_PCC1_SLOT		(38)
@@ -177,6 +178,9 @@
 #define USDHC0_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
 #define USDHC1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
 
+#define SNVS_BASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
+#define SNVS_LP_LPCR	(SNVS_BASE + 0x38)
+
 #define RGPIO2P0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))
 #define RGPIO2P1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
 
@@ -939,6 +943,9 @@
 #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
 
+#define SNVS_LPCR_DPEN				(0x20)
+#define SNVS_LPCR_SRTC_ENV			(0x1)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 
 #include <asm/types.h>