commit b1954254997f8616624b1f0b7bcd90c84ae0fabd
author York Sun <yorksun@freescale.com> Mon Sep 16 12:49:31 2013 -0700
committer York Sun <yorksun@freescale.com> Wed Oct 16 16:15:17 2013 -0700
tree 8310923265a2fd56d900bc4b973cfbb2f95dfc75
parent f0af438d082a65934c3b105d0d2f6c1988b5ff87

powerpc/mpc85xx: Add workaround for erratum A006379

Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Erratum A006379 applies to
	T4240 rev 1.0
	B4860 rev 1.0, 2.0

Signed-off-by: York Sun <yorksun@freescale.com>

arch/powerpc/include/asm/config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index b51d383..946ea97 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -599,6 +599,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -624,6 +625,7 @@
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000