diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 1a77eba..af7d05f 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -1764,15 +1764,9 @@
 	.get_rate = stm32mp1_clk_get_rate,
 };
 
-static const struct udevice_id stm32mp1_clk_ids[] = {
-	{ .compatible = "st,stm32mp1-rcc-clk" },
-	{ }
-};
-
 U_BOOT_DRIVER(stm32mp1_clock) = {
 	.name = "stm32mp1_clk",
 	.id = UCLASS_CLK,
-	.of_match = stm32mp1_clk_ids,
 	.ops = &stm32mp1_clk_ops,
 	.priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
 	.probe = stm32mp1_clk_probe,
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 17b3a80..c031dfd 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -169,7 +169,7 @@
 
 config STM32_RCC
 	bool "Enable RCC driver for the STM32 SoC's family"
-	depends on STM32 && MISC
+	depends on (STM32 || ARCH_STM32MP) && MISC
 	help
 	  Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
 	  block) is responsible of the management of the clock and reset
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index 980b3a5..13d7069 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -30,6 +30,11 @@
 	.drv_name = "stm32h7_rcc_clock",
 };
 
+struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
+	.drv_name = "stm32mp1_clk",
+	.soc = STM32MP1,
+};
+
 static int stm32_rcc_bind(struct udevice *dev)
 {
 	struct udevice *child;
@@ -39,7 +44,6 @@
 	int ret;
 
 	debug("%s(dev=%p)\n", __func__, dev);
-
 	drv = lists_driver_lookup_name(rcc_clk->drv_name);
 	if (!drv) {
 		debug("Cannot find driver '%s'\n", rcc_clk->drv_name);
@@ -53,9 +57,15 @@
 	if (ret)
 		return ret;
 
+	drv = lists_driver_lookup_name("stm32_rcc_reset");
+	if (!drv) {
+		dev_err(dev, "Cannot find driver stm32_rcc_reset'\n");
+		return -ENOENT;
+	}
+
-	return device_bind_driver_to_node(dev, "stm32_rcc_reset",
-					  "stm32_rcc_reset",
-					  dev_ofnode(dev), &child);
+	return device_bind_with_driver_data(dev, drv, "stm32_rcc_reset",
+					    rcc_clk->soc,
+					    dev_ofnode(dev), &child);
 }
 
 static const struct misc_ops stm32_rcc_ops = {
@@ -66,6 +76,7 @@
 	{.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 },
 	{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
 	{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
+	{.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
 	{ }
 };
 
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index c21ede2..16d3dba 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -8,16 +8,12 @@
 #include <dm.h>
 #include <errno.h>
 #include <reset-uclass.h>
+#include <stm32_rcc.h>
 #include <asm/io.h>
 
 /* reset clear offset for STM32MP RCC */
 #define RCC_CL 0x4
 
-enum rcc_type {
-	RCC_STM32 = 0,
-	RCC_STM32MP,
-};
-
 struct stm32_reset_priv {
 	fdt_addr_t base;
 };
@@ -40,7 +36,7 @@
 	debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
 	      reset_ctl->id, bank, offset);
 
-	if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
 		/* reset assert is done in rcc set register */
 		writel(BIT(offset), priv->base + bank);
 	else
@@ -57,7 +53,7 @@
 	debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
 	      reset_ctl->id, bank, offset);
 
-	if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
 		/* reset deassert is done in rcc clr register */
 		writel(BIT(offset), priv->base + bank + RCC_CL);
 	else
@@ -88,15 +84,9 @@
 	return 0;
 }
 
-static const struct udevice_id stm32_reset_ids[] = {
-	{ .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
-	{ }
-};
-
 U_BOOT_DRIVER(stm32_rcc_reset) = {
 	.name			= "stm32_rcc_reset",
 	.id			= UCLASS_RESET,
-	.of_match		= stm32_reset_ids,
 	.probe			= stm32_reset_probe,
 	.priv_auto_alloc_size	= sizeof(struct stm32_reset_priv),
 	.ops			= &stm32_reset_ops,