x86: Add common functions for TDP and perf control
These functions are the same on modern Intel CPUs, so use common code to
set them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels();
fix 'muiltiplier' and 'desgn' typos]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index 586a2e8..55a7439 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -41,12 +41,9 @@
void set_max_freq(void)
{
- msr_t msr, perf_ctl, platform_info;
-
- /* Check for configurable TDP option */
- platform_info = msr_read(MSR_PLATFORM_INFO);
+ msr_t msr, perf_ctl;
- if ((platform_info.hi >> 1) & 3) {
+ if (cpu_config_tdp_levels()) {
/* Set to nominal TDP ratio */
msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
perf_ctl.lo = (msr.lo & 0xff) << 8;
diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c
index 58cc2f3..169b5b0 100644
--- a/arch/x86/cpu/broadwell/cpu_full.c
+++ b/arch/x86/cpu/broadwell/cpu_full.c
@@ -329,15 +329,6 @@
return 0;
}
-static int cpu_config_tdp_levels(void)
-{
- msr_t platform_info;
-
- /* Bits 34:33 indicate how many levels supported */
- platform_info = msr_read(MSR_PLATFORM_INFO);
- return (platform_info.hi >> 1) & 3;
-}
-
static void set_max_ratio(void)
{
msr_t msr, perf_ctl;
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 7d0ed73..1898903 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -145,3 +145,23 @@
return 0;
}
+
+void cpu_set_perf_control(uint clk_ratio)
+{
+ msr_t perf_ctl;
+
+ perf_ctl.lo = (clk_ratio & 0xff) << 8;
+ perf_ctl.hi = 0;
+ msr_write(MSR_IA32_PERF_CTL, perf_ctl);
+ debug("CPU: frequency set to %d MHz\n", clk_ratio * INTEL_BCLK_MHZ);
+}
+
+bool cpu_config_tdp_levels(void)
+{
+ msr_t platform_info;
+
+ /* Bits 34:33 indicate how many levels supported */
+ platform_info = msr_read(MSR_PLATFORM_INFO);
+
+ return ((platform_info.hi >> 1) & 3) != 0;
+}
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 3177ba3..56ab6bf 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -140,19 +140,16 @@
[0x11] = 128,
};
-int cpu_config_tdp_levels(void)
+bool cpu_ivybridge_config_tdp_levels(void)
{
struct cpuid_result result;
- msr_t platform_info;
/* Minimum CPU revision */
result = cpuid(1);
if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
- return 0;
+ return false;
- /* Bits 34:33 indicate how many levels supported */
- platform_info = msr_read(MSR_PLATFORM_INFO);
- return (platform_info.hi >> 1) & 3;
+ return cpu_config_tdp_levels();
}
/*
@@ -213,7 +210,7 @@
msr_write(MSR_PKG_POWER_LIMIT, limit);
/* Use nominal TDP values for CPUs with configurable TDP */
- if (cpu_config_tdp_levels()) {
+ if (cpu_ivybridge_config_tdp_levels()) {
msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
limit.hi = 0;
limit.lo = msr.lo & 0xff;
@@ -329,24 +326,20 @@
static void set_max_ratio(void)
{
- msr_t msr, perf_ctl;
-
- perf_ctl.hi = 0;
+ msr_t msr;
+ uint ratio;
/* Check for configurable TDP option */
- if (cpu_config_tdp_levels()) {
+ if (cpu_ivybridge_config_tdp_levels()) {
/* Set to nominal TDP ratio */
msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
- perf_ctl.lo = (msr.lo & 0xff) << 8;
+ ratio = msr.lo & 0xff;
} else {
/* Platform Info bits 15:8 give max ratio */
msr = msr_read(MSR_PLATFORM_INFO);
- perf_ctl.lo = msr.lo & 0xff00;
+ ratio = (msr.lo & 0xff00) >> 8;
}
- msr_write(MSR_IA32_PERF_CTL, perf_ctl);
-
- debug("model_x06ax: frequency set to %d\n",
- ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
+ cpu_set_perf_control(ratio);
}
static void set_energy_perf_bias(u8 policy)
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index a809b82..0f427af 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -141,7 +141,7 @@
* CPUs with configurable TDP also need power limits set
* in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
*/
- if (cpu_config_tdp_levels()) {
+ if (cpu_ivybridge_config_tdp_levels()) {
msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
writel(msr.lo, MCHBAR_REG(0x59A0));