nds32: ftmac100: support cache enable.
Add cache inval and flush when rx and tx.
Signed-off-by: rick <rick@andestech.com>
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index f231e6b..4e45f00 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -79,7 +79,6 @@
struct ftmac100_rxdes *rxdes = priv->rxdes;
unsigned int maccr;
int i;
-
debug ("%s()\n", __func__);
ftmac100_reset(priv);
@@ -156,7 +155,6 @@
unsigned short rxlen;
curr_des = &priv->rxdes[priv->rx_index];
-
if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN)
return 0;
@@ -169,7 +167,7 @@
}
rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0);
-
+ invalidate_dcache_range(curr_des->rxdes2,curr_des->rxdes2+rxlen);
debug ("%s(): RX buffer %d, %x received\n",
__func__, priv->rx_index, rxlen);
@@ -196,6 +194,7 @@
/* initiate a transmit sequence */
+ flush_dcache_range((u32)packet,(u32)packet+length);
curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */
curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;