Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-mmc
diff --git a/MAINTAINERS b/MAINTAINERS
index d0a4a28..921ce05 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1640,9 +1640,18 @@
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
T: git https://source.denx.de/u-boot/custodians/u-boot-tpm.git
S: Maintained
+F: cmd/optee*
+F: doc/README.tee
+F: doc/device-tree-bindings/firmware/linaro,optee-tz.txt
+F: drivers/firmware/scmi/optee_agent.c
F: drivers/tee/
+F: include/sandboxtee.h
F: include/tee.h
F: include/tee/
+F: include/test/optee.h
+F: test/dm/tee.c
+F: test/optee/
+F: test/py/tests/test_optee_rpmb.py
TEE-lib
M: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dad8697..0c6f022 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -167,8 +167,8 @@
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
- rk3588s-coolpi-4b.dts \
- rk3588-coolpi-cm5-evb.dts \
+ rk3588s-coolpi-4b.dtb \
+ rk3588-coolpi-cm5-evb.dtb \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
@@ -180,6 +180,7 @@
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+ rk3588-toybrick-x0.dtb \
rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi b/arch/arm/dts/rk3308-evb-u-boot.dtsi
index d15ba94..007a69f 100644
--- a/arch/arm/dts/rk3308-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -4,14 +4,11 @@
*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &emmc;
- };
-};
-
&uart4 {
bootph-all;
clock-frequency = <24000000>;
- status = "okay";
+};
+
+&uart4_xfer {
+ bootph-all;
};
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
index 124a240..184b84f 100644
--- a/arch/arm/dts/rk3308-evb.dts
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -23,7 +23,7 @@
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
- func-key {
+ button-func {
linux,code = <KEY_FN>;
label = "function";
press-threshold-microvolt = <18000>;
@@ -37,31 +37,31 @@
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
- esc-key {
+ button-esc {
linux,code = <KEY_MICMUTE>;
label = "micmute";
press-threshold-microvolt = <1130000>;
};
- home-key {
+ button-home {
linux,code = <KEY_MODE>;
label = "mode";
press-threshold-microvolt = <901000>;
};
- menu-key {
+ button-menu {
linux,code = <KEY_PLAY>;
label = "play";
press-threshold-microvolt = <624000>;
};
- vol-down-key {
+ button-down {
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
press-threshold-microvolt = <300000>;
};
- vol-up-key {
+ button-up {
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <18000>;
@@ -75,115 +75,115 @@
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
- power {
+ key-power {
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
- wakeup-source;
debounce-interval = <100>;
+ wakeup-source;
};
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
-
- vdd_core: vdd-core {
- compatible = "pwm-regulator";
- pwms = <&pwm0 0 5000 1>;
- regulator-name = "vdd_core";
- regulator-min-microvolt = <827000>;
- regulator-max-microvolt = <1340000>;
regulator-always-on;
regulator-boot-on;
- regulator-settling-time-up-us = <250>;
- pwm-supply = <&vcc5v0_sys>;
- };
-
- vdd_log: vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vdd_1v0: vdd-1v0 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_1v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- vin-supply = <&vcc5v0_sys>;
+ vin-supply = <&vcc12v_dcin>;
};
vccio_sdio: vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
vin-supply = <&vcc_io>;
};
vcc_ddr: vcc-ddr {
compatible = "regulator-fixed";
regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vccio_flash: vccio-flash {
compatible = "regulator-fixed";
regulator-name = "vccio_flash";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
vin-supply = <&vcc_io>;
};
vcc5v0_host: vcc5v0-host {
compatible = "regulator-fixed";
- enable-active-high;
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&usb_drv>;
regulator-name = "vbus_host";
vin-supply = <&vcc5v0_sys>;
};
+
+ vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 1>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = <1340000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-settling-time-up-us = <250>;
+ pwm-supply = <&vcc5v0_sys>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vdd_1v0: vdd-1v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&cpu0 {
diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
index 97d922c..3e01e7a 100644
--- a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
@@ -5,13 +5,37 @@
#include "rk3308-u-boot.dtsi"
/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &emmc;
+ aliases {
+ ethernet0 = &gmac;
};
};
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&mac_clkin>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmiim1_pins &macm1_refclk>;
+ status = "okay";
+};
+
+&gpio4 {
+ bootph-pre-ram;
+};
+
&uart2 {
bootph-all;
clock-frequency = <24000000>;
- status = "okay";
+};
+
+&uart2m0_xfer {
+ bootph-all;
+};
+
+&vcc_sd {
+ bootph-pre-ram;
+};
+
+&vdd_core {
+ regulator-init-microvolt = <1015000>;
};
diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
index b4a54a8..9232357 100644
--- a/arch/arm/dts/rk3308-roc-cc.dts
+++ b/arch/arm/dts/rk3308-roc-cc.dts
@@ -9,11 +9,17 @@
/ {
model = "Firefly ROC-RK3308-CC board";
compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
+
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &emmc;
+ };
+
chosen {
stdout-path = "serial2:1500000n8";
};
- ir_rx {
+ ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -27,14 +33,15 @@
leds {
compatible = "gpio-leds";
- power {
+
+ power_led: led-0 {
label = "firefly:red:power";
linux,default-trigger = "ir-power-click";
default-state = "on";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
};
- user {
+ user_led: led-1 {
label = "firefly:blue:user";
linux,default-trigger = "ir-user-click";
default-state = "off";
@@ -45,10 +52,10 @@
typec_vcc5v: typec-vcc5v {
compatible = "regulator-fixed";
regulator-name = "typec_vcc5v";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
};
vcc5v0_sys: vcc5v0-sys {
@@ -61,29 +68,6 @@
vin-supply = <&typec_vcc5v>;
};
- vdd_core: vdd-core {
- compatible = "pwm-regulator";
- pwms = <&pwm0 0 5000 1>;
- regulator-name = "vdd_core";
- regulator-min-microvolt = <827000>;
- regulator-max-microvolt = <1340000>;
- regulator-init-microvolt = <1015000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-settling-time-up-us = <250>;
- pwm-supply = <&vcc5v0_sys>;
- };
-
- vdd_log: vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
@@ -100,8 +84,8 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0
- 3300000 0x1>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
vin-supply = <&vcc5v0_sys>;
};
@@ -113,9 +97,30 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
+ vin-supply = <&vcc_io>;
+ };
+
+ vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 1>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = <1340000>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
- vim-supply = <&vcc_io>;
+ pwm-supply = <&vcc5v0_sys>;
};
+ vdd_log: vdd-log {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&cpu0 {
@@ -123,12 +128,9 @@
};
&emmc {
- bus-width = <8>;
cap-mmc-highspeed;
- supports-emmc;
- disable-wp;
+ mmc-hs200-1_8v;
non-removable;
- num-slots = <1>;
status = "okay";
};
@@ -143,15 +145,6 @@
};
};
-&mac {
- assigned-clocks = <&cru SCLK_MAC>;
- assigned-clock-parents = <&mac_clkin>;
- clock_in_out = "input";
- pinctrl-names = "default";
- pinctrl-0 = <&rmiim1_pins &macm1_refclk>;
- status = "okay";
-};
-
&pwm5 {
status = "okay";
pinctrl-names = "active";
@@ -181,10 +174,8 @@
};
&sdmmc {
- bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- supports-sd;
card-detect-delay = <300>;
sd-uhs-sdr25;
sd-uhs-sdr50;
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index d88dee8..a6fb8b1 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -4,39 +4,42 @@
*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;
- };
+&emmc {
+ cap-sd-highspeed;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
};
-&uart0 {
- bootph-all;
-};
-
-&pinctrl {
+&emmc_bus4 {
+ bootph-pre-ram;
bootph-some-ram;
+};
- uart0 {
- bootph-some-ram;
- };
- rtc {
- bootph-some-ram;
- };
+&u2phy_otg {
+ /delete-property/ phy-supply;
};
-&uart0_xfer {
- bootph-some-ram;
+&uart0 {
+ bootph-all;
+ clock-frequency = <24000000>;
};
&uart0_cts {
- bootph-some-ram;
+ bootph-all;
};
&uart0_rts {
- bootph-some-ram;
+ bootph-all;
};
-&rtc_32k {
- bootph-some-ram;
+&uart0_xfer {
+ bootph-all;
+};
+
+&vcc5v0_otg {
+ /delete-property/ regulator-always-on;
+};
+
+&vdd_core {
+ regulator-init-microvolt = <1015000>;
};
diff --git a/arch/arm/dts/rk3308-rock-pi-s.dts b/arch/arm/dts/rk3308-rock-pi-s.dts
index b5a8691..b47fe02 100644
--- a/arch/arm/dts/rk3308-rock-pi-s.dts
+++ b/arch/arm/dts/rk3308-rock-pi-s.dts
@@ -1,12 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (C) 2023 Akash Gajjar <gajjar04akash@gmail.com>
- * Copyright (c) 2023 Jagan Teki <jagan@openedev.com>
+ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
*/
/dts-v1/;
-#include <dt-bindings/input/input.h>
#include "rk3308.dtsi"
/ {
@@ -14,7 +12,7 @@
compatible = "radxa,rockpis", "rockchip,rk3308";
aliases {
- ethernet0 = &mac;
+ ethernet0 = &gmac;
mmc0 = &emmc;
mmc1 = &sdmmc;
};
@@ -107,7 +105,6 @@
regulator-name = "vdd_core";
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
- regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>;
regulator-always-on;
regulator-boot-on;
@@ -137,7 +134,7 @@
status = "okay";
};
-&mac {
+&gmac {
clock_in_out = "output";
phy-supply = <&vcc_io>;
snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
@@ -146,6 +143,68 @@
status = "okay";
};
+&gpio0 {
+ gpio-line-names =
+ /* GPIO0_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_B0 - B7 */
+ "", "", "", "header1-pin3 [GPIO0_B3]",
+ "header1-pin5 [GPIO0_B4]", "", "",
+ "header1-pin11 [GPIO0_B7]",
+ /* GPIO0_C0 - C7 */
+ "header1-pin13 [GPIO0_C0]",
+ "header1-pin15 [GPIO0_C1]", "", "", "",
+ "", "", "",
+ /* GPIO0_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /* GPIO1_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_C0 - C7 */
+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
+ "header1-pin19 [GPIO1_C7]",
+ /* GPIO1_D0 - D7 */
+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]",
+ "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ /* GPIO2_A0 - A7 */
+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]",
+ "", "",
+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
+ /* GPIO2_B0 - B7 */
+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
+ /* GPIO2_C0 - C7 */
+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
+ /* GPIO2_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ /* GPIO3_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO3_B0 - B7 */
+ "", "", "header2-pin42 [GPIO3_B2]",
+ "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]",
+ "header2-pin39 [GPIO3_B5]", "", "",
+ /* GPIO3_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO3_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
&i2c1 {
status = "okay";
};
@@ -207,6 +266,20 @@
&sdmmc {
cap-sd-highspeed;
status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+ };
};
&uart0 {
@@ -223,6 +296,19 @@
};
};
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci {
+ status = "okay";
+};
+
+&usb20_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index db2c20a..684fa7a 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -10,32 +10,134 @@
mmc0 = &emmc;
mmc1 = &sdmmc;
};
-};
-&cru {
- bootph-all;
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
+ };
+
+ dmc: dmc@ff010000 {
+ compatible = "rockchip,rk3308-dmc";
+ reg = <0x0 0xff010000 0x0 0x10000>;
+ bootph-all;
+ };
+
+ otp: nvmem@ff210000 {
+ compatible = "rockchip,rk3308-otp";
+ reg = <0x0 0xff210000 0x0 0x4000>;
+ clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
+ <&cru PCLK_OTP_PHY>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = <&cru SRST_OTP_PHY>;
+ reset-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ };
+
+ rng: rng@ff2f0000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff2f0000 0x0 0x4000>;
+ };
};
-&dmc {
+&cru {
bootph-all;
};
&emmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&grf {
bootph-all;
};
-&sdmmc {
+&pcfg_pull_none {
bootph-all;
- u-boot,spl-fifo-mode;
};
-&grf {
+&pcfg_pull_none_4ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_none_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up {
bootph-all;
};
-&saradc {
+&pcfg_pull_up_4ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_up_8ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&rtc_32k {
+ bootph-all;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&xin24m {
bootph-all;
- status = "okay";
};
diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi
index 9a152a8..cfc0a87 100644
--- a/arch/arm/dts/rk3308.dtsi
+++ b/arch/arm/dts/rk3308.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
*
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -19,6 +20,11 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -39,7 +45,7 @@
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
@@ -52,7 +58,7 @@
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -62,7 +68,7 @@
cpu2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -72,7 +78,7 @@
cpu3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x3>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
@@ -95,10 +101,12 @@
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
- cpu0_opp_table: cpu0-opp-table {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -126,7 +134,7 @@
};
arm-pmu {
- compatible = "arm,cortex-a53-pmu";
+ compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
@@ -163,12 +171,53 @@
grf: grf@ff000000 {
compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff000000 0x0 0x10000>;
+ reg = <0x0 0xff000000 0x0 0x08000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x500>;
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-fastboot = <BOOT_FASTBOOT>;
+ };
};
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
- dmc: dmc@0xff010000 {
- compatible = "rockchip,rk3308-dmc";
- reg = <0x0 0xff010000 0x0 0x10000>;
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
};
detect_grf: syscon@ff00b000 {
@@ -183,7 +232,6 @@
reg = <0x0 0xff00c000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
-
};
i2c0: i2c@ff040000 {
@@ -239,7 +287,7 @@
};
wdt: watchdog@ff080000 {
- compatible = "snps,dw-wdt";
+ compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
reg = <0x0 0xff080000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -321,9 +369,8 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 0>, <&dmac0 1>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "high_speed";
+ pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
- pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>;
status = "disabled";
};
@@ -337,9 +384,8 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 2>, <&dmac0 3>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "high_speed";
+ pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
- pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>;
status = "disabled";
};
@@ -353,141 +399,140 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac1 16>, <&dmac1 17>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "high_speed";
+ pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
- pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>;
status = "disabled";
};
pwm8: pwm@ff160000 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm8_pin>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm8_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm9: pwm@ff160010 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm9_pin>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm9_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm10: pwm@ff160020 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm10_pin>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm10_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm11: pwm@ff160030 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm11_pin>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm11_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm4: pwm@ff170000 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm4_pin>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm@ff170010 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm5_pin>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm5_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm6: pwm@ff170020 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm6_pin>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm6_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm7: pwm@ff170030 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm7_pin>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm7_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm0: pwm@ff180000 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@ff180010 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1_pin>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@ff180020 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pin>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@ff180030 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pin>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -503,41 +548,34 @@
compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff1e0000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ #io-channel-cells = <1>;
resets = <&cru SRST_SARADC_P>;
reset-names = "saradc-apb";
status = "disabled";
};
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- dmac0: dma-controller@ff2c0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff2c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC0>;
- clock-names = "apb_pclk";
- peripherals-req-type-burst;
- };
+ dmac0: dma-controller@ff2c0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
- dmac1: dma-controller@ff2d0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff2d0000 0x0 0x4000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC1>;
- clock-names = "apb_pclk";
- peripherals-req-type-burst;
- };
+ dmac1: dma-controller@ff2d0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff2d0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
};
i2s_2ch_0: i2s@ff350000 {
@@ -572,7 +610,7 @@
};
spdif_tx: spdif-tx@ff3a0000 {
- compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
+ compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff3a0000 0x0 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
@@ -584,16 +622,52 @@
status = "disabled";
};
+ usb20_otg: usb@ff400000 {
+ compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@ff440000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@ff450000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
status = "disabled";
@@ -602,35 +676,49 @@
emmc: mmc@ff490000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff490000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
status = "disabled";
};
sdio: mmc@ff4a0000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff4a0000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
status = "disabled";
};
+ nfc: nand-controller@ff4b0000 {
+ compatible = "rockchip,rk3308-nfc",
+ "rockchip,rv1108-nfc";
+ reg = <0x0 0xff4b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&cru SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
+ &flash_rdn &flash_rdy &flash_wrn>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
- mac: ethernet@ff4e0000 {
- compatible = "rockchip,rk3308-mac";
+ gmac: ethernet@ff4e0000 {
+ compatible = "rockchip,rk3308-gmac";
reg = <0x0 0xff4e0000 0x0 0x10000>;
- rockchip,grf = <&grf>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
@@ -646,40 +734,57 @@
pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
resets = <&cru SRST_MAC_A>;
reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ sfc: spi@ff4c0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff4c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
status = "disabled";
};
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+ assigned-clocks = <&cru SCLK_RTC32K>;
+ assigned-clock-rates = <32768>;
};
gic: interrupt-controller@ff580000 {
compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
-
reg = <0x0 0xff581000 0x0 0x1000>,
<0x0 0xff582000 0x0 0x2000>,
<0x0 0xff584000 0x0 0x2000>,
<0x0 0xff586000 0x0 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #address-cells = <0>;
};
sram: sram@fff80000 {
compatible = "mmio-sram";
reg = <0x0 0xfff80000 0x0 0x40000>;
+ ranges = <0 0x0 0xfff80000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x0 0xfff80000 0x40000>;
+
/* reserved for ddr dvfs and system suspend/resume */
ddr-sram@0 {
reg = <0x0 0x8000>;
};
+
/* reserved for vad audio buffer */
vad_sram: vad-sram@8000 {
reg = <0x8000 0x38000>;
@@ -692,62 +797,58 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- gpio0: gpio0@ff220000 {
+
+ gpio0: gpio@ff220000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff220000 0x0 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio1: gpio1@ff230000 {
+ gpio1: gpio@ff230000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff230000 0x0 0x100>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio2: gpio2@ff240000 {
+ gpio2: gpio@ff240000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff240000 0x0 0x100>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio3: gpio3@ff250000 {
+ gpio3: gpio@ff250000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff250000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio4: gpio4@ff260000 {
+ gpio4: gpio@ff260000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -831,122 +932,307 @@
input-enable;
};
- i2c0 {
- i2c0_xfer: i2c0-xfer {
+ emmc {
+ emmc_clk: emmc-clk {
rockchip,pins =
- <1 RK_PD0 2 &pcfg_pull_none_smt>,
- <1 RK_PD1 2 &pcfg_pull_none_smt>;
+ <3 RK_PB1 2 &pcfg_pull_none_8ma>;
};
- };
- i2c1 {
- i2c1_xfer: i2c1-xfer {
+ emmc_cmd: emmc-cmd {
rockchip,pins =
- <0 RK_PB3 1 &pcfg_pull_none_smt>,
- <0 RK_PB4 1 &pcfg_pull_none_smt>;
+ <3 RK_PB0 2 &pcfg_pull_up_8ma>;
};
- };
- i2c2 {
- i2c2_xfer: i2c2-xfer {
+ emmc_pwren: emmc-pwren {
rockchip,pins =
- <2 RK_PA2 3 &pcfg_pull_none_smt>,
- <2 RK_PA3 3 &pcfg_pull_none_smt>;
+ <3 RK_PB3 2 &pcfg_pull_none>;
};
- };
- i2c3-m0 {
- i2c3m0_xfer: i2c3m0-xfer {
+ emmc_rstn: emmc-rstn {
rockchip,pins =
- <0 RK_PB7 2 &pcfg_pull_none_smt>,
- <0 RK_PC0 2 &pcfg_pull_none_smt>;
+ <3 RK_PB2 2 &pcfg_pull_none>;
};
- };
- i2c3-m1 {
- i2c3m1_xfer: i2c3m1-xfer {
+ emmc_bus1: emmc-bus1 {
rockchip,pins =
- <3 RK_PB4 2 &pcfg_pull_none_smt>,
- <3 RK_PB5 2 &pcfg_pull_none_smt>;
+ <3 RK_PA0 2 &pcfg_pull_up_8ma>;
};
- };
- i2c3-m2 {
- i2c3m2_xfer: i2c3m2-xfer {
+ emmc_bus4: emmc-bus4 {
rockchip,pins =
- <2 RK_PA1 3 &pcfg_pull_none_smt>,
- <2 RK_PA0 3 &pcfg_pull_none_smt>;
+ <3 RK_PA0 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA1 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA2 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA3 2 &pcfg_pull_up_8ma>;
};
- };
- i2s_2ch_0 {
- i2s_2ch_0_mclk: i2s-2ch-0-mclk {
+ emmc_bus8: emmc-bus8 {
rockchip,pins =
- <4 RK_PB4 1 &pcfg_pull_none>;
+ <3 RK_PA0 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA1 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA2 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA3 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA4 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA5 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA6 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA7 2 &pcfg_pull_up_8ma>;
};
+ };
- i2s_2ch_0_sclk: i2s-2ch-0-sclk {
+ flash {
+ flash_csn0: flash-csn0 {
rockchip,pins =
- <4 RK_PB5 1 &pcfg_pull_none>;
+ <3 RK_PB5 1 &pcfg_pull_none>;
};
- i2s_2ch_0_lrck: i2s-2ch-0-lrck {
+ flash_rdy: flash-rdy {
rockchip,pins =
- <4 RK_PB6 1 &pcfg_pull_none>;
+ <3 RK_PB4 1 &pcfg_pull_none>;
};
- i2s_2ch_0_sdo: i2s-2ch-0-sdo {
+ flash_ale: flash-ale {
rockchip,pins =
- <4 RK_PB7 1 &pcfg_pull_none>;
+ <3 RK_PB3 1 &pcfg_pull_none>;
};
- i2s_2ch_0_sdi: i2s-2ch-0-sdi {
+ flash_cle: flash-cle {
rockchip,pins =
- <4 RK_PC0 1 &pcfg_pull_none>;
+ <3 RK_PB1 1 &pcfg_pull_none>;
};
- };
- i2s_8ch_0 {
- i2s_8ch_0_mclk: i2s-8ch-0-mclk {
+ flash_wrn: flash-wrn {
rockchip,pins =
- <2 RK_PA4 1 &pcfg_pull_none>;
+ <3 RK_PB0 1 &pcfg_pull_none>;
};
- i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
+ flash_rdn: flash-rdn {
rockchip,pins =
- <2 RK_PA5 1 &pcfg_pull_none>;
+ <3 RK_PB2 1 &pcfg_pull_none>;
};
- i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
+ flash_bus8: flash-bus8 {
rockchip,pins =
- <2 RK_PA6 1 &pcfg_pull_none>;
+ <3 RK_PA0 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA1 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA2 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA3 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA4 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA5 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA6 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA7 1 &pcfg_pull_up_12ma>;
};
+ };
- i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
+ sfc {
+ sfc_bus4: sfc-bus4 {
rockchip,pins =
- <2 RK_PA7 1 &pcfg_pull_none>;
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ <3 RK_PA1 3 &pcfg_pull_none>,
+ <3 RK_PA2 3 &pcfg_pull_none>,
+ <3 RK_PA3 3 &pcfg_pull_none>;
};
- i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
+ sfc_bus2: sfc-bus2 {
rockchip,pins =
- <2 RK_PB0 1 &pcfg_pull_none>;
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ <3 RK_PA1 3 &pcfg_pull_none>;
};
- i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
+ sfc_cs0: sfc-cs0 {
rockchip,pins =
- <2 RK_PB1 1 &pcfg_pull_none>;
+ <3 RK_PA4 3 &pcfg_pull_none>;
};
- i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
+ sfc_clk: sfc-clk {
rockchip,pins =
- <2 RK_PB2 1 &pcfg_pull_none>;
+ <3 RK_PA5 3 &pcfg_pull_none>;
};
+ };
- i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
+ gmac {
+ rmii_pins: rmii-pins {
rockchip,pins =
- <2 RK_PB3 1 &pcfg_pull_none>;
- };
-
+ /* mac_txen */
+ <1 RK_PC1 3 &pcfg_pull_none_12ma>,
+ /* mac_txd1 */
+ <1 RK_PC3 3 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <1 RK_PC2 3 &pcfg_pull_none_12ma>,
+ /* mac_rxd0 */
+ <1 RK_PC4 3 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <1 RK_PC5 3 &pcfg_pull_none>,
+ /* mac_rxer */
+ <1 RK_PB7 3 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <1 RK_PC0 3 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PB6 3 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ mac_refclk_12ma: mac-refclk-12ma {
+ rockchip,pins =
+ <1 RK_PB4 3 &pcfg_pull_none_12ma>;
+ };
+
+ mac_refclk: mac-refclk {
+ rockchip,pins =
+ <1 RK_PB4 3 &pcfg_pull_none>;
+ };
+ };
+
+ gmac-m1 {
+ rmiim1_pins: rmiim1-pins {
+ rockchip,pins =
+ /* mac_txen */
+ <4 RK_PB7 2 &pcfg_pull_none_12ma>,
+ /* mac_txd1 */
+ <4 RK_PA5 2 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <4 RK_PA4 2 &pcfg_pull_none_12ma>,
+ /* mac_rxd0 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* mac_rxer */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <4 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ macm1_refclk_12ma: macm1-refclk-12ma {
+ rockchip,pins =
+ <4 RK_PB4 2 &pcfg_pull_none_12ma>;
+ };
+
+ macm1_refclk: macm1-refclk {
+ rockchip,pins =
+ <4 RK_PB4 2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ <1 RK_PD0 2 &pcfg_pull_none_smt>,
+ <1 RK_PD1 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ <0 RK_PB3 1 &pcfg_pull_none_smt>,
+ <0 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins =
+ <2 RK_PA2 3 &pcfg_pull_none_smt>,
+ <2 RK_PA3 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3-m0 {
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ <0 RK_PB7 2 &pcfg_pull_none_smt>,
+ <0 RK_PC0 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3-m1 {
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ <3 RK_PB4 2 &pcfg_pull_none_smt>,
+ <3 RK_PB5 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3-m2 {
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ <2 RK_PA1 3 &pcfg_pull_none_smt>,
+ <2 RK_PA0 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s_2ch_0 {
+ i2s_2ch_0_mclk: i2s-2ch-0-mclk {
+ rockchip,pins =
+ <4 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ i2s_2ch_0_sclk: i2s-2ch-0-sclk {
+ rockchip,pins =
+ <4 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ i2s_2ch_0_lrck: i2s-2ch-0-lrck {
+ rockchip,pins =
+ <4 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ i2s_2ch_0_sdo: i2s-2ch-0-sdo {
+ rockchip,pins =
+ <4 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ i2s_2ch_0_sdi: i2s-2ch-0-sdi {
+ rockchip,pins =
+ <4 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s_8ch_0 {
+ i2s_8ch_0_mclk: i2s-8ch-0-mclk {
+ rockchip,pins =
+ <2 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
+ rockchip,pins =
+ <2 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
+ rockchip,pins =
+ <2 RK_PA6 1 &pcfg_pull_none>;
+ };
+
+ i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
+ rockchip,pins =
+ <2 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
+ rockchip,pins =
+ <2 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
+ rockchip,pins =
+ <2 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
+ rockchip,pins =
+ <2 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
+ rockchip,pins =
+ <2 RK_PB3 1 &pcfg_pull_none>;
+ };
+
i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
rockchip,pins =
<2 RK_PB4 1 &pcfg_pull_none>;
@@ -1163,281 +1449,154 @@
};
};
- spdif_in {
- spdif_in: spdif-in {
+ pwm0 {
+ pwm0_pin: pwm0-pin {
rockchip,pins =
- <0 RK_PC2 1 &pcfg_pull_none>;
+ <0 RK_PB5 1 &pcfg_pull_none>;
};
- };
- spdif_out {
- spdif_out: spdif-out {
+ pwm0_pin_pull_down: pwm0-pin-pull-down {
rockchip,pins =
- <0 RK_PC1 1 &pcfg_pull_none>;
+ <0 RK_PB5 1 &pcfg_pull_down>;
};
};
- tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
+ pwm1 {
+ pwm1_pin: pwm1-pin {
rockchip,pins =
- <0 RK_PB2 0 &pcfg_pull_none>;
+ <0 RK_PB6 1 &pcfg_pull_none>;
};
- tsadc_otp_out: tsadc-otp-out {
+ pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins =
- <0 RK_PB2 1 &pcfg_pull_none>;
+ <0 RK_PB6 1 &pcfg_pull_down>;
};
};
- uart0 {
- uart0_xfer: uart0-xfer {
+ pwm2 {
+ pwm2_pin: pwm2-pin {
rockchip,pins =
- <2 RK_PA1 1 &pcfg_pull_up>,
- <2 RK_PA0 1 &pcfg_pull_up>;
+ <0 RK_PB7 1 &pcfg_pull_none>;
};
- uart0_cts: uart0-cts {
+ pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins =
- <2 RK_PA2 1 &pcfg_pull_none>;
+ <0 RK_PB7 1 &pcfg_pull_down>;
};
+ };
- uart0_rts: uart0-rts {
+ pwm3 {
+ pwm3_pin: pwm3-pin {
rockchip,pins =
- <2 RK_PA3 1 &pcfg_pull_none>;
+ <0 RK_PC0 1 &pcfg_pull_none>;
};
- uart0_rts_gpio: uart0-rts-gpio {
+ pwm3_pin_pull_down: pwm3-pin-pull-down {
rockchip,pins =
- <2 RK_PA3 0 &pcfg_pull_none>;
+ <0 RK_PC0 1 &pcfg_pull_down>;
};
};
- uart1 {
- uart1_xfer: uart1-xfer {
+ pwm4 {
+ pwm4_pin: pwm4-pin {
rockchip,pins =
- <1 RK_PD1 1 &pcfg_pull_up>,
- <1 RK_PD0 1 &pcfg_pull_up>;
+ <0 RK_PA1 2 &pcfg_pull_none>;
};
- uart1_cts: uart1-cts {
+ pwm4_pin_pull_down: pwm4-pin-pull-down {
rockchip,pins =
- <1 RK_PC6 1 &pcfg_pull_none>;
+ <0 RK_PA1 2 &pcfg_pull_down>;
};
+ };
- uart1_rts: uart1-rts {
+ pwm5 {
+ pwm5_pin: pwm5-pin {
rockchip,pins =
- <1 RK_PC7 1 &pcfg_pull_none>;
+ <0 RK_PC1 2 &pcfg_pull_none>;
};
- };
- uart2-m0 {
- uart2m0_xfer: uart2m0-xfer {
+ pwm5_pin_pull_down: pwm5-pin-pull-down {
rockchip,pins =
- <1 RK_PC7 2 &pcfg_pull_up>,
- <1 RK_PC6 2 &pcfg_pull_up>;
+ <0 RK_PC1 2 &pcfg_pull_down>;
};
};
- uart2-m1 {
- uart2m1_xfer: uart2m1-xfer {
+ pwm6 {
+ pwm6_pin: pwm6-pin {
rockchip,pins =
- <4 RK_PD3 2 &pcfg_pull_up>,
- <4 RK_PD2 2 &pcfg_pull_up>;
+ <0 RK_PC2 2 &pcfg_pull_none>;
};
- };
- uart3 {
- uart3_xfer: uart3-xfer {
- rockchip,pins =
- <3 RK_PB5 4 &pcfg_pull_up>,
- <3 RK_PB4 4 &pcfg_pull_up>;
- };
- };
-
- uart3-m1 {
- uart3m1_xfer: uart3m1-xfer {
+ pwm6_pin_pull_down: pwm6-pin-pull-down {
rockchip,pins =
- <0 RK_PC2 3 &pcfg_pull_up>,
- <0 RK_PC1 3 &pcfg_pull_up>;
+ <0 RK_PC2 2 &pcfg_pull_down>;
};
};
- uart4 {
-
- uart4_xfer: uart4-xfer {
- rockchip,pins =
- <4 RK_PB1 1 &pcfg_pull_up>,
- <4 RK_PB0 1 &pcfg_pull_up>;
- };
-
- uart4_cts: uart4-cts {
- rockchip,pins =
- <4 RK_PA6 1 &pcfg_pull_none>;
-
- };
-
- uart4_rts: uart4-rts {
+ pwm7 {
+ pwm7_pin: pwm7-pin {
rockchip,pins =
- <4 RK_PA7 1 &pcfg_pull_none>;
+ <2 RK_PB0 2 &pcfg_pull_none>;
};
- uart4_rts_gpio: uart4-rts-gpio {
+ pwm7_pin_pull_down: pwm7-pin-pull-down {
rockchip,pins =
- <4 RK_PA7 0 &pcfg_pull_none>;
+ <2 RK_PB0 2 &pcfg_pull_down>;
};
};
- spi0 {
- spi0_clk: spi0-clk {
- rockchip,pins =
- <2 RK_PA2 2 &pcfg_pull_up_4ma>;
- };
-
- spi0_csn0: spi0-csn0 {
- rockchip,pins =
- <2 RK_PA3 2 &pcfg_pull_up_4ma>;
- };
-
- spi0_miso: spi0-miso {
- rockchip,pins =
- <2 RK_PA0 2 &pcfg_pull_up_4ma>;
- };
-
- spi0_mosi: spi0-mosi {
- rockchip,pins =
- <2 RK_PA1 2 &pcfg_pull_up_4ma>;
- };
-
- spi0_clk_hs: spi0-clk-hs {
- rockchip,pins =
- <2 RK_PA2 2 &pcfg_pull_up_8ma>;
- };
-
- spi0_miso_hs: spi0-miso-hs {
+ pwm8 {
+ pwm8_pin: pwm8-pin {
rockchip,pins =
- <2 RK_PA0 2 &pcfg_pull_up_8ma>;
+ <2 RK_PB2 2 &pcfg_pull_none>;
};
- spi0_mosi_hs: spi0-mosi-hs {
+ pwm8_pin_pull_down: pwm8-pin-pull-down {
rockchip,pins =
- <2 RK_PA1 2 &pcfg_pull_up_8ma>;
+ <2 RK_PB2 2 &pcfg_pull_down>;
};
-
};
- spi1 {
- spi1_clk: spi1-clk {
- rockchip,pins =
- <3 RK_PB3 3 &pcfg_pull_up_4ma>;
- };
-
- spi1_csn0: spi1-csn0 {
- rockchip,pins =
- <3 RK_PB5 3 &pcfg_pull_up_4ma>;
- };
-
- spi1_miso: spi1-miso {
- rockchip,pins =
- <3 RK_PB2 3 &pcfg_pull_up_4ma>;
- };
-
- spi1_mosi: spi1-mosi {
- rockchip,pins =
- <3 RK_PB4 3 &pcfg_pull_up_4ma>;
- };
-
- spi1_clk_hs: spi1-clk-hs {
- rockchip,pins =
- <3 RK_PB3 3 &pcfg_pull_up_8ma>;
- };
-
- spi1_miso_hs: spi1-miso-hs {
+ pwm9 {
+ pwm9_pin: pwm9-pin {
rockchip,pins =
- <3 RK_PB2 3 &pcfg_pull_up_8ma>;
+ <2 RK_PB3 2 &pcfg_pull_none>;
};
- spi1_mosi_hs: spi1-mosi-hs {
+ pwm9_pin_pull_down: pwm9-pin-pull-down {
rockchip,pins =
- <3 RK_PB4 3 &pcfg_pull_up_8ma>;
+ <2 RK_PB3 2 &pcfg_pull_down>;
};
};
- spi1-m1 {
- spi1m1_miso: spi1m1-miso {
- rockchip,pins =
- <2 RK_PA4 2 &pcfg_pull_up_4ma>;
- };
-
- spi1m1_mosi: spi1m1-mosi {
- rockchip,pins =
- <2 RK_PA5 2 &pcfg_pull_up_4ma>;
- };
-
- spi1m1_clk: spi1m1-clk {
- rockchip,pins =
- <2 RK_PA7 2 &pcfg_pull_up_4ma>;
- };
-
- spi1m1_csn0: spi1m1-csn0 {
- rockchip,pins =
- <2 RK_PB1 2 &pcfg_pull_up_4ma>;
- };
-
- spi1m1_miso_hs: spi1m1-miso-hs {
- rockchip,pins =
- <2 RK_PA4 2 &pcfg_pull_up_8ma>;
- };
-
- spi1m1_mosi_hs: spi1m1-mosi-hs {
- rockchip,pins =
- <2 RK_PA5 2 &pcfg_pull_up_8ma>;
- };
-
- spi1m1_clk_hs: spi1m1-clk-hs {
+ pwm10 {
+ pwm10_pin: pwm10-pin {
rockchip,pins =
- <2 RK_PA7 2 &pcfg_pull_up_8ma>;
+ <2 RK_PB4 2 &pcfg_pull_none>;
};
- spi1m1_csn0_hs: spi1m1-csn0-hs {
+ pwm10_pin_pull_down: pwm10-pin-pull-down {
rockchip,pins =
- <2 RK_PB1 2 &pcfg_pull_up_8ma>;
+ <2 RK_PB4 2 &pcfg_pull_down>;
};
};
- spi2 {
- spi2_clk: spi2-clk {
- rockchip,pins =
- <1 RK_PD0 3 &pcfg_pull_up_4ma>;
- };
-
- spi2_csn0: spi2-csn0 {
- rockchip,pins =
- <1 RK_PD1 3 &pcfg_pull_up_4ma>;
- };
-
- spi2_miso: spi2-miso {
- rockchip,pins =
- <1 RK_PC6 3 &pcfg_pull_up_4ma>;
- };
-
- spi2_mosi: spi2-mosi {
- rockchip,pins =
- <1 RK_PC7 3 &pcfg_pull_up_4ma>;
- };
-
- spi2_clk_hs: spi2-clk-hs {
+ pwm11 {
+ pwm11_pin: pwm11-pin {
rockchip,pins =
- <1 RK_PD0 3 &pcfg_pull_up_8ma>;
+ <2 RK_PC0 4 &pcfg_pull_none>;
};
- spi2_miso_hs: spi2-miso-hs {
+ pwm11_pin_pull_down: pwm11-pin-pull-down {
rockchip,pins =
- <1 RK_PC6 3 &pcfg_pull_up_8ma>;
+ <2 RK_PC0 4 &pcfg_pull_down>;
};
+ };
- spi2_mosi_hs: spi2-mosi-hs {
+ rtc {
+ rtc_32k: rtc-32k {
rockchip,pins =
- <1 RK_PC7 3 &pcfg_pull_up_8ma>;
+ <0 RK_PC3 1 &pcfg_pull_none>;
};
};
@@ -1474,17 +1633,6 @@
<4 RK_PD2 1 &pcfg_pull_up_4ma>,
<4 RK_PD3 1 &pcfg_pull_up_4ma>;
};
-
- sdmmc_gpio: sdmmc-gpio {
- rockchip,pins =
- <4 RK_PD0 0 &pcfg_pull_up_4ma>,
- <4 RK_PD1 0 &pcfg_pull_up_4ma>,
- <4 RK_PD2 0 &pcfg_pull_up_4ma>,
- <4 RK_PD3 0 &pcfg_pull_up_4ma>,
- <4 RK_PD4 0 &pcfg_pull_up_4ma>,
- <4 RK_PD5 0 &pcfg_pull_up_4ma>,
- <4 RK_PD6 0 &pcfg_pull_up_4ma>;
- };
};
sdio {
@@ -1525,327 +1673,216 @@
<4 RK_PA2 1 &pcfg_pull_up_8ma>,
<4 RK_PA3 1 &pcfg_pull_up_8ma>;
};
-
- sdio_gpio: sdio-gpio {
- rockchip,pins =
- <4 RK_PA0 0 &pcfg_pull_up_4ma>,
- <4 RK_PA1 0 &pcfg_pull_up_4ma>,
- <4 RK_PA2 0 &pcfg_pull_up_4ma>,
- <4 RK_PA3 0 &pcfg_pull_up_4ma>,
- <4 RK_PA4 0 &pcfg_pull_up_4ma>,
- <4 RK_PA5 0 &pcfg_pull_up_4ma>;
- };
};
- emmc {
- emmc_clk: emmc-clk {
- rockchip,pins =
- <3 RK_PB1 2 &pcfg_pull_none_8ma>;
- };
-
- emmc_cmd: emmc-cmd {
+ spdif_in {
+ spdif_in: spdif-in {
rockchip,pins =
- <3 RK_PB0 2 &pcfg_pull_up_8ma>;
+ <0 RK_PC2 1 &pcfg_pull_none>;
};
+ };
- emmc_pwren: emmc-pwren {
+ spdif_out {
+ spdif_out: spdif-out {
rockchip,pins =
- <3 RK_PB3 2 &pcfg_pull_none>;
+ <0 RK_PC1 1 &pcfg_pull_none>;
};
+ };
- emmc_rstn: emmc-rstn {
+ spi0 {
+ spi0_clk: spi0-clk {
rockchip,pins =
- <3 RK_PB2 2 &pcfg_pull_none>;
+ <2 RK_PA2 2 &pcfg_pull_up_4ma>;
};
- emmc_bus1: emmc-bus1 {
+ spi0_csn0: spi0-csn0 {
rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>;
+ <2 RK_PA3 2 &pcfg_pull_up_4ma>;
};
- emmc_bus4: emmc-bus4 {
+ spi0_miso: spi0-miso {
rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
- <3 RK_PA3 2 &pcfg_pull_up_8ma>;
+ <2 RK_PA0 2 &pcfg_pull_up_4ma>;
};
- emmc_bus8: emmc-bus8 {
+ spi0_mosi: spi0-mosi {
rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
- <3 RK_PA3 2 &pcfg_pull_up_8ma>,
- <3 RK_PA4 2 &pcfg_pull_up_8ma>,
- <3 RK_PA5 2 &pcfg_pull_up_8ma>,
- <3 RK_PA6 2 &pcfg_pull_up_8ma>,
- <3 RK_PA7 2 &pcfg_pull_up_8ma>;
+ <2 RK_PA1 2 &pcfg_pull_up_4ma>;
};
};
- flash {
- flash_csn0: flash-csn0 {
- rockchip,pins =
- <3 RK_PB5 1 &pcfg_pull_none>;
- };
-
- flash_rdy: flash-rdy {
- rockchip,pins =
- <3 RK_PB4 1 &pcfg_pull_none>;
- };
-
- flash_ale: flash-ale {
- rockchip,pins =
- <3 RK_PB3 1 &pcfg_pull_none>;
- };
-
- flash_cle: flash-cle {
+ spi1 {
+ spi1_clk: spi1-clk {
rockchip,pins =
- <3 RK_PB1 1 &pcfg_pull_none>;
+ <3 RK_PB3 3 &pcfg_pull_up_4ma>;
};
- flash_wrn: flash-wrn {
+ spi1_csn0: spi1-csn0 {
rockchip,pins =
- <3 RK_PB0 1 &pcfg_pull_none>;
+ <3 RK_PB5 3 &pcfg_pull_up_4ma>;
};
- flash_rdn: flash-rdn {
+ spi1_miso: spi1-miso {
rockchip,pins =
- <3 RK_PB2 1 &pcfg_pull_none>;
+ <3 RK_PB2 3 &pcfg_pull_up_4ma>;
};
- flash_bus8: flash-bus8 {
+ spi1_mosi: spi1-mosi {
rockchip,pins =
- <3 RK_PA0 1 &pcfg_pull_up_12ma>,
- <3 RK_PA1 1 &pcfg_pull_up_12ma>,
- <3 RK_PA2 1 &pcfg_pull_up_12ma>,
- <3 RK_PA3 1 &pcfg_pull_up_12ma>,
- <3 RK_PA4 1 &pcfg_pull_up_12ma>,
- <3 RK_PA5 1 &pcfg_pull_up_12ma>,
- <3 RK_PA6 1 &pcfg_pull_up_12ma>,
- <3 RK_PA7 1 &pcfg_pull_up_12ma>;
+ <3 RK_PB4 3 &pcfg_pull_up_4ma>;
};
};
- pwm0 {
- pwm0_pin: pwm0-pin {
+ spi1-m1 {
+ spi1m1_miso: spi1m1-miso {
rockchip,pins =
- <0 RK_PB5 1 &pcfg_pull_none>;
+ <2 RK_PA4 2 &pcfg_pull_up_4ma>;
};
- pwm0_pin_pull_down: pwm0-pin-pull-down {
+ spi1m1_mosi: spi1m1-mosi {
rockchip,pins =
- <0 RK_PB5 1 &pcfg_pull_down>;
+ <2 RK_PA5 2 &pcfg_pull_up_4ma>;
};
- };
- pwm1 {
- pwm1_pin: pwm1-pin {
+ spi1m1_clk: spi1m1-clk {
rockchip,pins =
- <0 RK_PB6 1 &pcfg_pull_none>;
+ <2 RK_PA7 2 &pcfg_pull_up_4ma>;
};
- pwm1_pin_pull_down: pwm1-pin-pull-down {
+ spi1m1_csn0: spi1m1-csn0 {
rockchip,pins =
- <0 RK_PB6 1 &pcfg_pull_down>;
+ <2 RK_PB1 2 &pcfg_pull_up_4ma>;
};
};
- pwm2 {
- pwm2_pin: pwm2-pin {
+ spi2 {
+ spi2_clk: spi2-clk {
rockchip,pins =
- <0 RK_PB7 1 &pcfg_pull_none>;
+ <1 RK_PD0 3 &pcfg_pull_up_4ma>;
};
- pwm2_pin_pull_down: pwm2-pin-pull-down {
+ spi2_csn0: spi2-csn0 {
rockchip,pins =
- <0 RK_PB7 1 &pcfg_pull_down>;
+ <1 RK_PD1 3 &pcfg_pull_up_4ma>;
};
- };
- pwm3 {
- pwm3_pin: pwm3-pin {
+ spi2_miso: spi2-miso {
rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_none>;
+ <1 RK_PC6 3 &pcfg_pull_up_4ma>;
};
- pwm3_pin_pull_down: pwm3-pin-pull-down {
+ spi2_mosi: spi2-mosi {
rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_down>;
+ <1 RK_PC7 3 &pcfg_pull_up_4ma>;
};
};
- pwm4 {
- pwm4_pin: pwm4-pin {
+ tsadc {
+ tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
- <0 RK_PA1 2 &pcfg_pull_none>;
+ <0 RK_PB2 0 &pcfg_pull_none>;
};
- pwm4_pin_pull_down: pwm4-pin-pull-down {
+ tsadc_otp_out: tsadc-otp-out {
rockchip,pins =
- <0 RK_PA1 2 &pcfg_pull_down>;
+ <0 RK_PB2 1 &pcfg_pull_none>;
};
};
- pwm5 {
- pwm5_pin: pwm5-pin {
+ uart0 {
+ uart0_xfer: uart0-xfer {
rockchip,pins =
- <0 RK_PC1 2 &pcfg_pull_none>;
+ <2 RK_PA1 1 &pcfg_pull_up>,
+ <2 RK_PA0 1 &pcfg_pull_up>;
};
- pwm5_pin_pull_down: pwm5-pin-pull-down {
+ uart0_cts: uart0-cts {
rockchip,pins =
- <0 RK_PC1 2 &pcfg_pull_down>;
+ <2 RK_PA2 1 &pcfg_pull_none>;
};
- };
- pwm6 {
- pwm6_pin: pwm6-pin {
+ uart0_rts: uart0-rts {
rockchip,pins =
- <0 RK_PC2 2 &pcfg_pull_none>;
+ <2 RK_PA3 1 &pcfg_pull_none>;
};
- pwm6_pin_pull_down: pwm6-pin-pull-down {
+ uart0_rts_pin: uart0-rts-pin {
rockchip,pins =
- <0 RK_PC2 2 &pcfg_pull_down>;
+ <2 RK_PA3 0 &pcfg_pull_none>;
};
};
- pwm7 {
- pwm7_pin: pwm7-pin {
- rockchip,pins =
- <2 RK_PB0 2 &pcfg_pull_none>;
- };
-
- pwm7_pin_pull_down: pwm7-pin-pull-down {
+ uart1 {
+ uart1_xfer: uart1-xfer {
rockchip,pins =
- <2 RK_PB0 2 &pcfg_pull_down>;
+ <1 RK_PD1 1 &pcfg_pull_up>,
+ <1 RK_PD0 1 &pcfg_pull_up>;
};
- };
- pwm8 {
- pwm8_pin: pwm8-pin {
+ uart1_cts: uart1-cts {
rockchip,pins =
- <2 RK_PB2 2 &pcfg_pull_none>;
+ <1 RK_PC6 1 &pcfg_pull_none>;
};
- pwm8_pin_pull_down: pwm8-pin-pull-down {
+ uart1_rts: uart1-rts {
rockchip,pins =
- <2 RK_PB2 2 &pcfg_pull_down>;
+ <1 RK_PC7 1 &pcfg_pull_none>;
};
};
- pwm9 {
- pwm9_pin: pwm9-pin {
- rockchip,pins =
- <2 RK_PB3 2 &pcfg_pull_none>;
- };
-
- pwm9_pin_pull_down: pwm9-pin-pull-down {
+ uart2-m0 {
+ uart2m0_xfer: uart2m0-xfer {
rockchip,pins =
- <2 RK_PB3 2 &pcfg_pull_down>;
+ <1 RK_PC7 2 &pcfg_pull_up>,
+ <1 RK_PC6 2 &pcfg_pull_up>;
};
};
- pwm10 {
- pwm10_pin: pwm10-pin {
- rockchip,pins =
- <2 RK_PB4 2 &pcfg_pull_none>;
- };
-
- pwm10_pin_pull_down: pwm10-pin-pull-down {
+ uart2-m1 {
+ uart2m1_xfer: uart2m1-xfer {
rockchip,pins =
- <2 RK_PB4 2 &pcfg_pull_down>;
+ <4 RK_PD3 2 &pcfg_pull_up>,
+ <4 RK_PD2 2 &pcfg_pull_up>;
};
};
- pwm11 {
- pwm11_pin: pwm11-pin {
- rockchip,pins =
- <2 RK_PC0 4 &pcfg_pull_none>;
- };
-
- pwm11_pin_pull_down: pwm11-pin-pull-down {
+ uart3 {
+ uart3_xfer: uart3-xfer {
rockchip,pins =
- <2 RK_PC0 4 &pcfg_pull_down>;
+ <3 RK_PB5 4 &pcfg_pull_up>,
+ <3 RK_PB4 4 &pcfg_pull_up>;
};
};
- gmac {
- rmii_pins: rmii-pins {
- rockchip,pins =
- /* mac_txen */
- <1 RK_PC1 3 &pcfg_pull_none_12ma>,
- /* mac_txd1 */
- <1 RK_PC3 3 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <1 RK_PC2 3 &pcfg_pull_none_12ma>,
- /* mac_rxd0 */
- <1 RK_PC4 3 &pcfg_pull_none>,
- /* mac_rxd1 */
- <1 RK_PC5 3 &pcfg_pull_none>,
- /* mac_rxer */
- <1 RK_PB7 3 &pcfg_pull_none>,
- /* mac_rxdv */
- <1 RK_PC0 3 &pcfg_pull_none>,
- /* mac_mdio */
- <1 RK_PB6 3 &pcfg_pull_none>,
- /* mac_mdc */
- <1 RK_PB5 3 &pcfg_pull_none>;
- };
-
- mac_refclk_12ma: mac-refclk-12ma {
- rockchip,pins =
- <1 RK_PB4 3 &pcfg_pull_none_12ma>;
- };
-
- mac_refclk: mac-refclk {
+ uart3-m1 {
+ uart3m1_xfer: uart3m1-xfer {
rockchip,pins =
- <1 RK_PB4 3 &pcfg_pull_none>;
+ <0 RK_PC2 3 &pcfg_pull_up>,
+ <0 RK_PC1 3 &pcfg_pull_up>;
};
};
- gmac-m1 {
- rmiim1_pins: rmiim1-pins {
+ uart4 {
+ uart4_xfer: uart4-xfer {
rockchip,pins =
- /* mac_txen */
- <4 RK_PB7 2 &pcfg_pull_none_12ma>,
- /* mac_txd1 */
- <4 RK_PA5 2 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <4 RK_PA4 2 &pcfg_pull_none_12ma>,
- /* mac_rxd0 */
- <4 RK_PA2 2 &pcfg_pull_none>,
- /* mac_rxd1 */
- <4 RK_PA3 2 &pcfg_pull_none>,
- /* mac_rxer */
- <4 RK_PA0 2 &pcfg_pull_none>,
- /* mac_rxdv */
- <4 RK_PA1 2 &pcfg_pull_none>,
- /* mac_mdio */
- <4 RK_PB6 2 &pcfg_pull_none>,
- /* mac_mdc */
- <4 RK_PB5 2 &pcfg_pull_none>;
+ <4 RK_PB1 1 &pcfg_pull_up>,
+ <4 RK_PB0 1 &pcfg_pull_up>;
};
- macm1_refclk_12ma: macm1-refclk-12ma {
+ uart4_cts: uart4-cts {
rockchip,pins =
- <4 RK_PB4 2 &pcfg_pull_none_12ma>;
+ <4 RK_PA6 1 &pcfg_pull_none>;
};
- macm1_refclk: macm1-refclk {
+ uart4_rts: uart4-rts {
rockchip,pins =
- <4 RK_PB4 2 &pcfg_pull_none>;
+ <4 RK_PA7 1 &pcfg_pull_none>;
};
- };
- rtc {
- rtc_32k: rtc-32k {
+ uart4_rts_pin: uart4-rts-pin {
rockchip,pins =
- <0 RK_PC3 1 &pcfg_pull_none>;
+ <4 RK_PA7 0 &pcfg_pull_none>;
};
};
-
};
};
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 7c5067c..d3608bd 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -131,7 +131,7 @@
};
&vop {
- bootph-all;
+ bootph-some-ram;
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
diff --git a/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
index 85ee577..3838562 100644
--- a/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
@@ -4,3 +4,10 @@
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"
+
+&spi1 {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts
index 931334a..d5df893 100644
--- a/arch/arm/dts/rk3399-rock-pi-4a.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4a.dts
@@ -12,3 +12,13 @@
model = "Radxa ROCK Pi 4A";
compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399";
};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index 791f16b..793ed4a 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -6,12 +6,6 @@
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0;
};
-
- rng: rng@fe388000 {
- compatible = "rockchip,cryptov2-rng";
- reg = <0x0 0xfe388000 0x0 0x2000>;
- status = "okay";
- };
};
&dsi_dphy0 {
diff --git a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
index 4aa6ab1..eb18008 100644
--- a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
@@ -3,20 +3,31 @@
#include "rk356x-u-boot.dtsi"
&fspi_dual_io_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&gpio0 {
- bootph-all;
+ bootph-pre-ram;
};
&i2c0 {
bootph-pre-ram;
};
-&rk817 {
+&i2c0_xfer {
+ bootph-pre-ram;
+};
+
+&i2s1m0_mclk {
+ bootph-pre-ram;
+};
+
+&pmic_int_l {
bootph-pre-ram;
+};
+&rk817 {
regulators {
bootph-pre-ram;
};
@@ -27,15 +38,13 @@
};
&sdmmc_pwren_l {
- bootph-all;
+ bootph-pre-ram;
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
index 930d660..0e25b7e 100644
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -3,7 +3,7 @@
#include "rk356x-u-boot.dtsi"
&gpio0 {
- bootph-all;
+ bootph-pre-ram;
};
&sdhci {
@@ -13,11 +13,9 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
@@ -34,5 +32,5 @@
};
&vcc_sd_h {
- bootph-all;
+ bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
index c235b43..f2c9d8e 100644
--- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
@@ -9,11 +9,9 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3568-generic-u-boot.dtsi b/arch/arm/dts/rk3568-generic-u-boot.dtsi
index 6e8307e..fd7f536 100644
--- a/arch/arm/dts/rk3568-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-generic-u-boot.dtsi
@@ -1,3 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
+
+&sfc {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/dts/rk3568-generic.dts b/arch/arm/dts/rk3568-generic.dts
index 88eb1bf..085a092 100644
--- a/arch/arm/dts/rk3568-generic.dts
+++ b/arch/arm/dts/rk3568-generic.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Minimal generic DT for RK3566/RK3568 with eMMC and SD-card enabled
+ * Minimal generic DT for RK3566/RK3568 with eMMC, SD-card, SPI flash and USB OTG enabled
*/
/dts-v1/;
@@ -12,7 +12,7 @@
aliases {
mmc0 = &sdhci;
- mmc1 = &sdmmc;
+ mmc1 = &sdmmc0;
};
chosen {
@@ -28,7 +28,7 @@
no-sdio;
non-removable;
pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
status = "okay";
};
@@ -39,10 +39,39 @@
no-mmc;
no-sdio;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
status = "okay";
};
+&sfc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ };
+};
+
&uart2 {
status = "okay";
};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ extcon = <&usb2phy0>;
+ maximum-speed = "high-speed";
+ phys = <&usb2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
index 1fc71fa..d8a6dd8 100644
--- a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
@@ -3,7 +3,8 @@
#include "rk356x-u-boot.dtsi"
&fspi_dual_io_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdhci {
@@ -15,10 +16,8 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 5b823fc..9d18f5d 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -26,16 +26,15 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
- bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index d347080..0a0943b4 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -21,6 +21,11 @@
bootph-all;
};
+ rng: rng@fe388000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xfe388000 0x0 0x2000>;
+ };
+
otp: nvmem@fe38c000 {
compatible = "rockchip,rk3568-otp";
reg = <0x0 0xfe38c000 0x0 0x4000>;
@@ -33,119 +38,134 @@
};
};
-&xin24m {
- bootph-all;
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x8000>;
+ };
+ };
};
+#endif
&cru {
bootph-all;
};
-&pmucru {
- bootph-all;
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&grf {
- bootph-all;
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&pmugrf {
- bootph-all;
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&pinctrl {
- bootph-all;
+&emmc_datastrobe {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&pcfg_pull_none_smt {
- bootph-all;
+&emmc_rstnout {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&pcfg_pull_none {
- bootph-all;
+&fspi_pins {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&pcfg_pull_up_drv_level_2 {
+&grf {
bootph-all;
};
-&pcfg_pull_up {
+&pcfg_pull_none {
bootph-all;
};
-&emmc_bus8 {
- bootph-all;
+&pcfg_pull_none_smt {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&emmc_clk {
+&pcfg_pull_up {
bootph-all;
};
-&emmc_cmd {
- bootph-all;
+&pcfg_pull_up_drv_level_2 {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&emmc_datastrobe {
+&pinctrl {
bootph-all;
};
-&emmc_rstnout {
+&pmucru {
bootph-all;
};
-&fspi_pins {
+&pmugrf {
bootph-all;
};
-&i2c0_xfer {
- bootph-all;
+&sdhci {
+ bootph-pre-ram;
+ bootph-some-ram;
+ max-frequency = <200000000>;
};
+&sdmmc0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&sdmmc0_bus4 {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_clk {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_cmd {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_det {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_pwren {
- bootph-all;
-};
-
-&uart2m0_xfer {
- bootph-all;
-};
-
-&sdhci {
bootph-pre-ram;
- max-frequency = <200000000>;
+ bootph-some-ram;
};
-&sdmmc0 {
- bootph-pre-ram;
+&sfc {
+ u-boot,spl-sfc-no-dma;
};
&uart2 {
- bootph-pre-ram;
+ bootph-all;
clock-frequency = <24000000>;
};
-#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
-&binman {
- simple-bin-spi {
- mkimage {
- args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
- offset = <0x8000>;
- };
- };
+&uart2m0_xfer {
+ bootph-all;
};
-#endif
+
+&xin24m {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
index ed15b14..f0ef016 100644
--- a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -3,7 +3,8 @@
#include "rk3588-u-boot.dtsi"
&fspim2_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdhci {
@@ -12,16 +13,15 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <&fspim2_pins>;
status = "okay";
flash@0 {
- bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi
index 853ed58..225dfa0 100644
--- a/arch/arm/dts/rk3588-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
@@ -1,3 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588s-u-boot.dtsi"
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
index e4721d9..95d7576 100644
--- a/arch/arm/dts/rk3588-generic.dts
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled
+ * Minimal generic DT for RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled
*/
/dts-v1/;
@@ -40,5 +40,6 @@
};
&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
index 60494bb..9683856 100644
--- a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi
@@ -7,12 +7,11 @@
#include "rk3588-u-boot.dtsi"
&fspim1_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <&fspim1_pins>;
#address-cells = <1>;
@@ -20,9 +19,10 @@
status = "okay";
flash@0 {
- bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
index 5d5fa6f..1ab31a4 100644
--- a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
@@ -3,7 +3,8 @@
#include "rk3588-u-boot.dtsi"
&fspim1_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdhci {
@@ -12,10 +13,8 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 9ee9dd0..d6020ca 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -18,7 +18,8 @@
};
&fspim2_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl {
@@ -35,16 +36,15 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <&fspim2_pins>;
status = "okay";
flash@0 {
- bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
index ca2a684..a50bcc4 100644
--- a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
@@ -12,6 +12,10 @@
};
&uart9 {
- bootph-pre-ram;
+ bootph-all;
clock-frequency = <24000000>;
};
+
+&uart9m0_xfer {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
index 6e4b970..f51d7f3 100644
--- a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -3,7 +3,8 @@
#include "rk3588s-u-boot.dtsi"
&fspim2_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdhci {
@@ -12,16 +13,15 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <&fspim2_pins>;
status = "okay";
flash@0 {
- bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
index 888d1b9..12a92c0 100644
--- a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
@@ -9,14 +9,13 @@
};
&fspim0_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index ac67c77..d3c2579 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -41,6 +41,17 @@
status = "disabled";
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&cru PCLK_VO0GRF>;
+ };
+
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
usbdpphy0_grf: syscon@fd5c8000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5c8000 0x0 0x4000>;
@@ -72,26 +83,9 @@
};
};
- vo0_grf: syscon@fd5a6000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a6000 0x0 0x2000>;
- clocks = <&cru PCLK_VO0GRF>;
- };
-
- usb_grf: syscon@fd5ac000 {
- compatible = "rockchip,rk3588-usb-grf", "syscon";
- reg = <0x0 0xfd5ac000 0x0 0x4000>;
- };
-
- usbdpphy0_grf: syscon@fd5c8000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5c8000 0x0 0x4000>;
- };
-
rng: rng@fe378000 {
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
- status = "disabled";
};
usbdp_phy0: phy@fed80000 {
@@ -126,35 +120,55 @@
};
};
-&emmc_bus8 {
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x8000>;
+ };
+ };
+};
+#endif
+
+&cru {
bootph-all;
};
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&emmc_clk {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_cmd {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_data_strobe {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_rstnout {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&pinctrl {
+&ioc {
bootph-all;
};
-&pcfg_pull_none {
+&pcfg_pull_down {
bootph-all;
};
-&pcfg_pull_up_drv_level_2 {
+&pcfg_pull_none {
bootph-all;
};
@@ -162,16 +176,17 @@
bootph-all;
};
-&xin24m {
- bootph-all;
+&pcfg_pull_up_drv_level_2 {
+ bootph-pre-ram;
+ bootph-some-ram;
};
-&cru {
- bootph-pre-ram;
+&php_grf {
+ bootph-all;
};
-&sys_grf {
- bootph-pre-ram;
+&pinctrl {
+ bootph-all;
};
&pmu1grf {
@@ -180,42 +195,56 @@
&scmi {
bootph-pre-ram;
+ bootph-some-ram;
};
&scmi_clk {
bootph-pre-ram;
+ bootph-some-ram;
};
-&sdmmc {
+&sdhci {
bootph-pre-ram;
bootph-some-ram;
u-boot,spl-fifo-mode;
};
-&sdhci {
+&sdmmc {
bootph-pre-ram;
bootph-some-ram;
u-boot,spl-fifo-mode;
};
&sdmmc_bus4 {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc_clk {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc_cmd {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sfc {
+ u-boot,spl-sfc-no-dma;
+};
+
+&sys_grf {
bootph-all;
};
&uart2 {
- bootph-pre-ram;
+ bootph-all;
clock-frequency = <24000000>;
};
@@ -223,17 +252,6 @@
bootph-all;
};
-&ioc {
- bootph-pre-ram;
-};
-
-#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
-&binman {
- simple-bin-spi {
- mkimage {
- args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
- offset = <0x8000>;
- };
- };
+&xin24m {
+ bootph-all;
};
-#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 4276a0f..ecf3b4e 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -43,11 +43,14 @@
* Boot-device identifiers as used by the BROM
*/
enum {
+ BROM_BOOTSOURCE_UNKNOWN = 0,
BROM_BOOTSOURCE_NAND = 1,
BROM_BOOTSOURCE_EMMC = 2,
BROM_BOOTSOURCE_SPINOR = 3,
BROM_BOOTSOURCE_SPINAND = 4,
BROM_BOOTSOURCE_SD = 5,
+ BROM_BOOTSOURCE_I2C = 8,
+ BROM_BOOTSOURCE_SPI = 9,
BROM_BOOTSOURCE_USB = 10,
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
};
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rockchip/cru_rk3308.h
similarity index 95%
rename from arch/arm/include/asm/arch-rk3308/cru_rk3308.h
rename to arch/arm/include/asm/arch-rockchip/cru_rk3308.h
index 84b63e4..091ae82 100644
--- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3308.h
@@ -147,6 +147,20 @@
CORE_DIV_CON_SHIFT = 0,
CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
+ /* CRU_CLK_SEL2_CON */
+ CLK_RTC32K_SEL_SHIFT = 8,
+ CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT,
+ CLK_RTC32K_IO = 0,
+ CLK_RTC32K_PVTM,
+ CLK_RTC32K_FRAC_DIV,
+ CLK_RTC32K_DIV,
+
+ /* CRU_CLK_SEL3_CON */
+ CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16,
+ CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff,
+
/* CRU_CLK_SEL5_CON */
BUS_PLL_SEL_SHIFT = 6,
BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT,
diff --git a/arch/arm/include/asm/arch-rk3308/grf_rk3308.h b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h
similarity index 100%
rename from arch/arm/include/asm/arch-rk3308/grf_rk3308.h
rename to arch/arm/include/asm/arch-rockchip/grf_rk3308.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4f22d9b..67d3b28 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -160,14 +160,25 @@
select SPL_ATF
select SPL_ATF_NO_PLATFORM_PARAM
select SPL_LOAD_FIT
+ imply ARMV8_CRYPTO
+ imply ARMV8_SET_SMPEN
+ imply DM_RNG
+ imply LEGACY_IMAGE_FORMAT
+ imply MISC
+ imply MISC_INIT_R
+ imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
- imply SPL_ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_OTP
imply SPL_CLK
- imply SPL_REGMAP
- imply SPL_SYSCON
+ imply SPL_DM_SEQ_ALIAS
+ imply SPL_FIT_SIGNATURE
+ imply SPL_PINCTRL
imply SPL_RAM
- imply SPL_SERIAL
+ imply SPL_REGMAP
+ imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SEPARATE_BSS
+ imply SPL_SERIAL
+ imply SPL_SYSCON
help
The Rockchip RK3308 is a ARM-based Soc which embedded with quad
Cortex-A35 and highly integrated audio interfaces.
@@ -180,19 +191,19 @@
select SUPPORT_TPL
select TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
+ imply ARMV8_CRYPTO
+ imply ARMV8_SET_SMPEN
+ imply MISC
+ imply MISC_INIT_R
+ imply OF_LIVE
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_EFUSE
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD
+ imply SPL_SEPARATE_BSS
imply SPL_SERIAL
imply TPL_SERIAL
- imply SPL_SEPARATE_BSS
- select ENABLE_ARM_SOC_BOOT0_HOOK
- select DEBUG_UART_BOARD_INIT
- select SYS_NS16550
- imply MISC
- imply ROCKCHIP_EFUSE
- imply MISC_INIT_R
help
The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
@@ -295,12 +306,16 @@
select BOARD_LATE_INIT
select DM_REGULATOR_FIXED
select DM_RESET
- imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
- imply ROCKCHIP_COMMON_BOARD
- imply OF_LIBFDT_OVERLAY
- imply ROCKCHIP_OTP
+ imply BOOTSTD_FULL
+ imply DM_RNG
imply MISC_INIT_R
imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+ imply OF_LIBFDT_OVERLAY
+ imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+ imply RNG_ROCKCHIP
+ imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_OTP
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
help
The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
@@ -322,16 +337,19 @@
select BOARD_LATE_INIT
select DM_REGULATOR_FIXED
select DM_RESET
- imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
- imply ROCKCHIP_COMMON_BOARD
- imply OF_LIBFDT_OVERLAY
- imply ROCKCHIP_OTP
+ imply BOOTSTD_FULL
+ imply CLK_SCMI
+ imply DM_RNG
imply MISC_INIT_R
imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
- imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
- imply CLK_SCMI
+ imply OF_LIBFDT_OVERLAY
+ imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+ imply RNG_ROCKCHIP
+ imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_OTP
imply SCMI_FIRMWARE
- imply BOOTSTD_FULL
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+ imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
help
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
@@ -574,6 +592,9 @@
imply TPL_SYS_MALLOC_F if TPL
imply TPL_SYS_MALLOC_SIMPLE if TPL
+config NR_DRAM_BANKS
+ default 10 if ROCKCHIP_EXTERNAL_TPL
+
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3066/Kconfig"
diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c
index 637a5e1..db368a7 100644
--- a/arch/arm/mach-rockchip/px30-board-tpl.c
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -36,7 +36,7 @@
{
int ret;
-#ifdef CONFIG_DEBUG_UART
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
debug_uart_init();
/*
* Debug UART can be used from here if required:
@@ -46,8 +46,10 @@
* printhex8(0x1234);
* printascii("string");
*/
+#if CONFIG_TPL_BANNER_PRINT
printascii("U-Boot TPL board init\n");
#endif
+#endif
secure_timer_init();
ret = sdram_init();
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index b4f655f..2ec3289 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -19,6 +19,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff3a0000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ff370000",
};
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index c77c56c..70cf500 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -28,6 +28,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff130000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
};
diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig
index 749e999..fac9662 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -23,9 +23,6 @@
config TEXT_BASE
default 0x00600000
-config SPL_SERIAL
- default y
-
source "board/rockchip/evb_rk3308/Kconfig"
source "board/firefly/firefly-rk3308/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
index ccda533..201bf66 100644
--- a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
@@ -7,7 +7,7 @@
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3308.h>
+#include <asm/arch-rockchip/cru_rk3308.h>
#include <linux/err.h>
int rockchip_get_clk(struct udevice **devp)
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c
index 27a7483..a0915c7 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -5,8 +5,8 @@
#include <common.h>
#include <init.h>
#include <malloc.h>
-#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/grf_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/gpio.h>
#include <debug_uart.h>
@@ -141,6 +141,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff4c0000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ff480000",
};
diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
index daf74a0..d2f267e 100644
--- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
@@ -17,4 +17,7 @@
.name = "rockchip_rk3328_grf",
.id = UCLASS_SYSCON,
.of_match = rk3328_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
};
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index 651ba10..8f5ca1d 100644
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -55,6 +55,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff120000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
};
diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c
index 8589c46..40eb9eb 100644
--- a/arch/arm/mach-rockchip/rv1126/rv1126.c
+++ b/arch/arm/mach-rockchip/rv1126/rv1126.c
@@ -15,6 +15,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ffc50000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ffc90000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ffc60000",
};
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0ae..f2a3d6b 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -8,6 +8,7 @@
#include <init.h>
#include <log.h>
#include <ram.h>
+#include <asm/armv8/mmu.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-rockchip/sdram.h>
@@ -35,12 +36,271 @@
s64 reserve[8];
};
+#ifdef CONFIG_ARM64
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE (CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
+
+/* ATAGS memory structures */
+
+enum tag_magic {
+ ATAG_NONE,
+ ATAG_CORE = 0x54410001,
+ ATAG_SERIAL = 0x54410050,
+ ATAG_DDR_MEM = 0x54410052,
+ ATAG_MAX = 0x544100ff,
+};
+
+/*
+ * An ATAG contains the following data:
+ * - header
+ * u32 size // sizeof(header + tag data) / sizeof(u32)
+ * u32 magic
+ * - tag data
+ */
+
+struct tag_header {
+ u32 size;
+ u32 magic;
+} __packed;
+
+/*
+ * DDR_MEM tag bank is storing data this way:
+ * - address0
+ * - address1
+ * - [...]
+ * - addressX
+ * - size0
+ * - size1
+ * - [...]
+ * - sizeX
+ *
+ * with X being tag_ddr_mem.count - 1.
+ */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+static u32 js_hash(const void *buf, u32 len)
+{
+ u32 i, hash = 0x47C6A7E6;
+
+ if (!buf || !len)
+ return hash;
+
+ for (i = 0; i < len; i++)
+ hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
+
+ return hash;
+}
+
+static int rockchip_dram_init_banksize(void)
+{
+ const struct tag_header *tag_h = NULL;
+ u32 *addr = (void *)ATAGS_PHYS_BASE;
+ struct tag_ddr_mem *ddr_info;
+ u32 calc_hash;
+ u8 i, j;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ return -ENOTSUPP;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return -ENOTSUPP;
+
+ /* Find DDR_MEM tag */
+ while (addr < (u32 *)ATAGS_PHYS_END) {
+ tag_h = (const struct tag_header *)addr;
+
+ if (!tag_h->size) {
+ debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ if (tag_h->magic == ATAG_DDR_MEM)
+ break;
+
+ switch (tag_h->magic) {
+ case ATAG_NONE:
+ case ATAG_CORE:
+ case ATAG_SERIAL ... ATAG_MAX:
+ addr += tag_h->size;
+ continue;
+ default:
+ debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
+ tag_h->magic, addr);
+ return -EINVAL;
+ }
+ }
+
+ if (addr >= (u32 *)ATAGS_PHYS_END ||
+ (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
+ debug("End of ATAGS, no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ /* Data is right after the magic member of the tag_header struct */
+ ddr_info = (struct tag_ddr_mem *)(&tag_h->magic + 1);
+ if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
+ debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
+ ddr_info->count, CONFIG_NR_DRAM_BANKS);
+ return -ENOMEM;
+ }
+
+ if (!ddr_info->hash) {
+ debug("No hash for tag (0x%08x)\n", tag_h->magic);
+ } else {
+ calc_hash = js_hash(addr, sizeof(u32) * (tag_h->size - 1));
+
+ if (calc_hash != ddr_info->hash) {
+ debug("Incorrect hash for tag (0x%08x), got (0x%08x) expected (0x%08x)\n",
+ tag_h->magic, ddr_info->hash, calc_hash);
+ return -EINVAL;
+ }
+ }
+
+ /*
+ * Rockchip guaranteed DDR_MEM is ordered so no need to worry about
+ * bi_dram order.
+ */
+ for (i = 0, j = 0; i < ddr_info->count; i++, j++) {
+ phys_size_t size = ddr_info->bank[(i + ddr_info->count)];
+ phys_addr_t start_addr = ddr_info->bank[i];
+ struct mm_region *tmp_mem_map = mem_map;
+ phys_addr_t end_addr;
+
+ /*
+ * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
+ * have it, so force this space as reserved.
+ */
+ if (start_addr < SZ_2M) {
+ size -= SZ_2M - start_addr;
+ start_addr = SZ_2M;
+ }
+
+ /*
+ * Put holes for reserved memory areas from mem_map.
+ *
+ * Only check for at most one overlap with one reserved memory
+ * area.
+ */
+ while (tmp_mem_map->size) {
+ const phys_addr_t rsrv_start = tmp_mem_map->phys;
+ const phys_size_t rsrv_size = tmp_mem_map->size;
+ const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
+
+ /*
+ * DRAM memories are expected by Arm to be marked as
+ * Normal Write-back cacheable, Inner shareable[1], so
+ * let's filter on that to put holes in non-DRAM areas.
+ *
+ * [1] https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
+ */
+ const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ /*
+ * (AttrIndx | SH) in Lower Attributes of Block
+ * Descriptor[2].
+ * [2] https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
+ */
+ const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9, 8);
+
+ if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
+ tmp_mem_map++;
+ continue;
+ }
+
+ /*
+ * If the start of the DDR_MEM tag is in a reserved
+ * memory area, move start address and resize.
+ */
+ if (start_addr >= rsrv_start && start_addr < rsrv_end) {
+ if (rsrv_end - start_addr > size) {
+ debug("Would be negative memory size\n");
+ return -EINVAL;
+ }
+
+ size -= rsrv_end - start_addr;
+ start_addr = rsrv_end;
+ break;
+ }
+
+ if (start_addr < rsrv_start) {
+ end_addr = start_addr + size;
+
+ if (end_addr <= rsrv_start) {
+ tmp_mem_map++;
+ continue;
+ }
+
+ /*
+ * If the memory area overlaps a reserved memory
+ * area with start address outside of reserved
+ * memory area and...
+ *
+ * ... ends in the middle of reserved memory
+ * area, resize.
+ */
+ if (end_addr <= rsrv_end) {
+ size = rsrv_start - start_addr;
+ break;
+ }
+
+ /*
+ * ... ends after the reserved memory area,
+ * split the region in two, one for before the
+ * reserved memory area and one for after.
+ */
+ gd->bd->bi_dram[j].start = start_addr;
+ gd->bd->bi_dram[j].size = rsrv_start - start_addr;
+
+ j++;
+
+ size = end_addr - rsrv_end;
+ start_addr = rsrv_end;
+
+ break;
+ }
+
+ tmp_mem_map++;
+ }
+
+ if (j > CONFIG_NR_DRAM_BANKS) {
+ debug("Too many banks, max allowed (%d)\n",
+ CONFIG_NR_DRAM_BANKS);
+ return -ENOMEM;
+ }
+
+ gd->bd->bi_dram[j].start = start_addr;
+ gd->bd->bi_dram[j].size = size;
+ }
+
+ return 0;
+}
+#endif
+
int dram_init_banksize(void)
{
size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64
+ int ret = rockchip_dram_init_banksize();
+
+ if (!ret)
+ return ret;
+
+ debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
+ ret);
+
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 79c856d..3543267 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -29,7 +29,7 @@
* -ENOSYS, if the device matching the node can not be mapped onto a
* SPL boot device (e.g. the third MMC device)
* -1, for unspecified failures
- * a positive integer (from the BOOT_DEVICE_... family) on succes.
+ * a positive integer (from the BOOT_DEVICE_... family) on success.
*/
static int spl_node_to_boot_device(int node)
@@ -148,8 +148,8 @@
/* Try to map this back onto SPL boot devices */
boot_device = spl_node_to_boot_device(node);
if (boot_device < 0) {
- debug("%s: could not map node @%x to a boot-device\n",
- __func__, node);
+ debug("%s: could not map node %s to a boot-device\n",
+ __func__, conf);
continue;
}
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 1586a09..3ce7e79 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -32,18 +32,26 @@
const char *board_spl_was_booted_from(void)
{
- u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+ static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN;
+ u32 bootdevice_brom_id;
const char *bootdevice_ofpath = NULL;
+ if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN)
+ bootdevice_brom_id = brom_bootsource_id_cache;
+ else
+ bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+
if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
bootdevice_ofpath = boot_devices[bootdevice_brom_id];
- if (bootdevice_ofpath)
+ if (bootdevice_ofpath) {
+ brom_bootsource_id_cache = bootdevice_brom_id;
debug("%s: brom_bootdevice_id %x maps to '%s'\n",
__func__, bootdevice_brom_id, bootdevice_ofpath);
- else
+ } else {
debug("%s: failed to resolve brom_bootdevice_id %x\n",
__func__, bootdevice_brom_id);
+ }
return bootdevice_ofpath;
}
diff --git a/board/firefly/firefly-rk3308/MAINTAINERS b/board/firefly/firefly-rk3308/MAINTAINERS
index e584038..b70ff52 100644
--- a/board/firefly/firefly-rk3308/MAINTAINERS
+++ b/board/firefly/firefly-rk3308/MAINTAINERS
@@ -4,3 +4,4 @@
F: board/firefly/firefly-rk3308/
F: configs/roc-cc-rk3308_defconfig
F: include/configs/firefly_rk3308.h
+F: arch/arm/dts/rk3308-roc-cc*
diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
index 99a52a7..af00250 100644
--- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c
+++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <adc.h>
-#include <asm/arch/grf_rk3308.h>
+#include <asm/arch-rockchip/grf_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
#include <linux/bitops.h>
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile
deleted file mode 100644
index c1c49b1..0000000
--- a/board/friendlyelec/nanopc-t6-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
deleted file mode 100644
index 99bbef9..0000000
--- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc000000,
- .end = 0x3fc4fffff,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff00000,
- .end = 0x3ffffffff,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
- * Inject the reserved-memory nodes into the DTS
- */
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
- NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return nanopc_t6_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile
deleted file mode 100644
index 47819d9..0000000
--- a/board/pine64/quartzpro64-rk3588/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
deleted file mode 100644
index bda804a..0000000
--- a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2023 Google, Inc
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc000000,
- .end = 0x3fc4fffff,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff00000,
- .end = 0x3ffffffff,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
- * Inject the reserved-memory nodes into the DTS
- */
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
- NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return quartzpro64_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/radxa/rock2/MAINTAINERS b/board/radxa/rock2/MAINTAINERS
index 5328fd7..af974c9 100644
--- a/board/radxa/rock2/MAINTAINERS
+++ b/board/radxa/rock2/MAINTAINERS
@@ -1,9 +1,7 @@
FIREFLY
M: Simon Glass <sjg@chromium.org>
S: Maintained
-F: arch/arm/dts/rk3288-rock2-som.dtsi
-F: arch/arm/dts/rk3288-rock2-square.dts
-F: arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
+F: arch/arm/dts/rk3288-rock2*
F: board/radxa/rock2
F: include/configs/rock2.h
F: configs/rock2_defconfig
diff --git a/board/radxa/rock5a-rk3588s/Makefile b/board/radxa/rock5a-rk3588s/Makefile
deleted file mode 100644
index 48dd512..0000000
--- a/board/radxa/rock5a-rk3588s/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Collabora Ltd.
-#
-
-obj-y += rock5a-rk3588s.o
diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
deleted file mode 100644
index 2d7a8c0..0000000
--- a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5a_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc000000,
- .end = 0x3fc4fffff,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff00000,
- .end = 0x3ffffffff,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
- * Inject the reserved-memory nodes into the DTS
- */
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
- NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5a_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/radxa/rock5b-rk3588/Makefile b/board/radxa/rock5b-rk3588/Makefile
deleted file mode 100644
index 95d8135..0000000
--- a/board/radxa/rock5b-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2022 Collabora Ltd.
-#
-
-obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
deleted file mode 100644
index 5c3b52b9..0000000
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc000000,
- .end = 0x3fc4fffff,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff00000,
- .end = 0x3ffffffff,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
- * Inject the reserved-memory nodes into the DTS
- */
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
- NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5b_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/rockchip/evb_rk3308/MAINTAINERS b/board/rockchip/evb_rk3308/MAINTAINERS
index fe2c5f0..abffbb1 100644
--- a/board/rockchip/evb_rk3308/MAINTAINERS
+++ b/board/rockchip/evb_rk3308/MAINTAINERS
@@ -4,10 +4,11 @@
F: board/rockchip/evb_rk3308
F: include/configs/evb_rk3308.h
F: configs/evb-rk3308_defconfig
+F: arch/arm/dts/rk3308-evb*
ROCK-PI-S
M: Akash Gajjar <gajjar04akash@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/rock-pi-s-rk3308_defconfig
-F: arch/arm/dts/rk3308-rock-pi-s.dts
-F: arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+F: arch/arm/dts/rk3308-rock-pi-s*
diff --git a/board/rockchip/evb_rk3588/Makefile b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec..0000000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8..0000000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc000000,
- .end = 0x3fc4fffff,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff00000,
- .end = 0x3ffffffff,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
- * Inject the reserved-memory nodes into the DTS
- */
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
- NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/rockchip/toybrick_rk3588/Makefile b/board/rockchip/toybrick_rk3588/Makefile
deleted file mode 100644
index 75d4d94..0000000
--- a/board/rockchip/toybrick_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += toybrick-rk3588.o
diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
deleted file mode 100644
index e3217f7..0000000
--- a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc000000,
- .end = 0x3fc4fffff,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff00000,
- .end = 0x3ffffffff,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- int ret;
-
- /*
- * Inject the reserved-memory nodes into the DTS
- */
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
- NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index bfebfe5..c48de73 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -58,9 +58,9 @@
mdelay(1);
- ret = gpio_direction_output(STM32_RST, 1);
+ ret = gpio_direction_input(STM32_RST);
if (ret) {
- debug("Failed to configure STM32_RST as output high\n");
+ debug("Failed to configure STM32_RST as input\n");
return;
}
}
diff --git a/board/turing/turing-rk1-rk3588/Makefile b/board/turing/turing-rk1-rk3588/Makefile
deleted file mode 100644
index a979d80..0000000
--- a/board/turing/turing-rk1-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += turing-rk1-rk3588.o
diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
deleted file mode 100644
index e2338a2..0000000
--- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include <fdtdec.h>
-#include <fdt_support.h>
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc000000,
- .end = 0x3fc4fffff,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff00000,
- .end = 0x3ffffffff,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
- * Inject the reserved-memory nodes into the DTS
- */
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
- NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return turing_rk1_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index c8c9238..fcade91 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -3,12 +3,9 @@
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
-CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_ANBERNIC_RGXX3_RK3566=y
CONFIG_DEBUG_UART_BASE=0xFE660000
@@ -70,8 +67,6 @@
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
-CONFIG_DM_RNG=y
-CONFIG_RNG_ROCKCHIP=y
# CONFIG_RNG_SMCCC_TRNG is not set
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig
index 5cc9524..a0caa36 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
@@ -15,7 +14,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTSTD_FULL=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig
index a0fe370..2608bb6 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
@@ -23,7 +22,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig
index fc17660..c5bb7a4 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
@@ -23,7 +22,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index d57b2f6..04a94e1 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -3,43 +3,35 @@
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
-CONFIG_DEBUG_UART_BASE=0xFF0C0000
+CONFIG_DEBUG_UART_BASE=0xFF0E0000
CONFIG_DEBUG_UART_CLOCK=24000000
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=0
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_SLEEP is not set
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -50,9 +42,11 @@
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PHY=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -61,15 +55,15 @@
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 75a0e0f..53ad677 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -57,6 +57,7 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+# CONFIG_ROCKCHIP_IODOMAIN is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_MOTORCOMM=y
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 6e8061f..e71d670 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
@@ -32,7 +31,7 @@
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
@@ -49,6 +48,7 @@
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index c8db04c..a8c32c4 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -33,7 +31,8 @@
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -52,7 +51,7 @@
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index e7d5e55..033702f 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -2,18 +2,22 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
@@ -21,19 +25,27 @@
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
+# CONFIG_ADC is not set
CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_MISC=y
# CONFIG_ROCKCHIP_IODOMAIN is not set
@@ -43,10 +55,27 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index b50f4f8..87a1717 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -15,8 +14,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -27,15 +26,21 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
+# CONFIG_ADC is not set
CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
@@ -44,10 +49,19 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index 3233b75..f29505e 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -3,7 +3,6 @@
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_ENV_SIZE=0x1f000
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
index 1c50a0c..ea67b6a 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig
index 5c7bc0b..738dda0 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
@@ -23,7 +22,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
index 0f1a946..00743b7 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig
index 4ebf0cc..91e3a19 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
index 307a540..5619855 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -13,11 +12,13 @@
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
@@ -28,6 +29,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -40,10 +42,11 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig
index 9ef2bb2..40baec3 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -13,11 +12,13 @@
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
@@ -28,6 +29,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -40,10 +42,11 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig
index b5ed9e4..e749f9a 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1"
diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig
index d6e23c1..ba80053 100644
--- a/configs/orangepi-5-plus-rk3588_defconfig
+++ b/configs/orangepi-5-plus-rk3588_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus"
@@ -24,7 +23,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig
index e6b3da1..d61f85a 100644
--- a/configs/orangepi-5-rk3588s_defconfig
+++ b/configs/orangepi-5-rk3588s_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5"
@@ -23,7 +22,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig
index edeb1d8..ad237ed 100644
--- a/configs/pinetab2-rk3566_defconfig
+++ b/configs/pinetab2-rk3566_defconfig
@@ -3,7 +3,7 @@
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-pinetab2-v2.0"
CONFIG_ROCKCHIP_RK3568=y
diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig
index fef8043..535e34f 100644
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -3,7 +3,6 @@
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a"
diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
index bb541ed..e197def 100644
--- a/configs/quartz64-b-rk3566_defconfig
+++ b/configs/quartz64-b-rk3566_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b"
diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig
index b2a66d3..33cbda8 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -19,7 +18,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -64,7 +62,6 @@
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
-CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index bf61db4..d23ab57 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
index 43aa8ec..dbb77b8 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 5e8f51e..ef58bd6 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -2,10 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_ROC_RK3308_CC=y
CONFIG_DEBUG_UART_BASE=0xFF0C0000
CONFIG_DEBUG_UART_CLOCK=24000000
@@ -14,32 +15,23 @@
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=0
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_SLEEP is not set
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -50,26 +42,30 @@
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PHY=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index c161bc9..b06b57f 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index bca44be..315b8b8 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -3,25 +3,30 @@
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -40,14 +45,20 @@
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
@@ -61,6 +72,7 @@
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -81,7 +93,6 @@
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig
index 1e9cd2c..37a124e 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -6,7 +6,6 @@
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_DEBUG_UART_BASE=0xFF0A0000
CONFIG_DEBUG_UART_CLOCK=24000000
@@ -17,30 +16,22 @@
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_SLEEP is not set
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -51,9 +42,11 @@
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PHY=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -62,15 +55,15 @@
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index ebe2d4a..01df911 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index ac4f1eb..9e14b14 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
@@ -24,7 +23,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -75,7 +73,6 @@
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
-CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig
index b9ac6b9..9d565c1 100644
--- a/configs/soquartz-blade-rk3566_defconfig
+++ b/configs/soquartz-blade-rk3566_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig
index e87a639..fe2c771 100644
--- a/configs/soquartz-cm4-rk3566_defconfig
+++ b/configs/soquartz-cm4-rk3566_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig
index b2c1684..db9eee2 100644
--- a/configs/soquartz-model-a-rk3566_defconfig
+++ b/configs/soquartz-model-a-rk3566_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig
index 6ee92e9..76bfa50 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -2,7 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -33,8 +31,9 @@
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -53,7 +52,7 @@
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig
index e18ced7..038b147 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
@@ -24,7 +23,6 @@
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -81,7 +79,6 @@
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
-CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
@@ -91,7 +88,6 @@
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 5dd5ea7..9a726e9 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -131,6 +131,8 @@
- Turing Machines RK1 (turing-rk1-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
+ - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s)
+ - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588)
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index 7755b01..8616483 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -12,8 +12,8 @@
#include <malloc.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/arch/cru_rk3308.h>
#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
@@ -65,6 +65,57 @@
RK3308_MODE_CON, 6, 10, 0, NULL),
};
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+
static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
{
struct rk3308_cru *cru = priv->cru;
@@ -832,6 +883,44 @@
return rk3308_crypto_get_clk(priv, clk_id);
}
+static ulong rk3308_rtc32k_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
+{
+ struct rk3308_cru *cru = priv->cru;
+ unsigned long m, n;
+ u32 con, fracdiv;
+
+ con = readl(&cru->clksel_con[2]);
+ if ((con & CLK_RTC32K_SEL_MASK) >> CLK_RTC32K_SEL_SHIFT !=
+ CLK_RTC32K_FRAC_DIV)
+ return -EINVAL;
+
+ fracdiv = readl(&cru->clksel_con[3]);
+ m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK;
+ m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT;
+ n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK;
+ n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT;
+
+ return OSC_HZ * m / n;
+}
+
+static ulong rk3308_rtc32k_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
+ ulong hz)
+{
+ struct rk3308_cru *cru = priv->cru;
+ unsigned long m, n, val;
+
+ rational_best_approximation(hz, OSC_HZ,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &m, &n);
+ val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, &cru->clksel_con[3]);
+ rk_clrsetreg(&cru->clksel_con[2], CLK_RTC32K_SEL_MASK,
+ CLK_RTC32K_FRAC_DIV << CLK_RTC32K_SEL_SHIFT);
+
+ return rk3308_rtc32k_get_clk(priv, clk_id);
+}
+
static ulong rk3308_clk_get_rate(struct clk *clk)
{
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
@@ -912,6 +1001,9 @@
case SCLK_CRYPTO_APK:
rate = rk3308_crypto_get_clk(priv, clk->id);
break;
+ case SCLK_RTC32K:
+ rate = rk3308_rtc32k_get_clk(priv, clk->id);
+ break;
default:
return -ENOENT;
}
@@ -990,6 +1082,11 @@
case SCLK_CRYPTO_APK:
ret = rk3308_crypto_set_clk(priv, clk->id, rate);
break;
+ case SCLK_RTC32K:
+ ret = rk3308_rtc32k_set_clk(priv, clk->id, rate);
+ break;
+ case USB480M:
+ return 0;
default:
return -ENOENT;
}
@@ -1022,6 +1119,8 @@
switch (clk->id) {
case SCLK_MAC:
return rk3308_mac_set_parent(clk, parent);
+ case USB480M:
+ return 0;
default:
break;
}
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 57ef27d..24eeca8 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1527,28 +1527,20 @@
struct rk3568_cru *cru = priv->cru;
int src_clk;
- switch (rate) {
- case OSC_HZ:
- src_clk = SCLK_SFC_SEL_24M;
- break;
- case 50 * MHz:
- src_clk = SCLK_SFC_SEL_50M;
- break;
- case 75 * MHz:
- src_clk = SCLK_SFC_SEL_75M;
- break;
- case 100 * MHz:
- src_clk = SCLK_SFC_SEL_100M;
- break;
- case 125 * MHz:
- src_clk = SCLK_SFC_SEL_125M;
- break;
- case 150 * MHz:
+ if (rate >= 150 * MHz)
src_clk = SCLK_SFC_SEL_150M;
- break;
- default:
+ else if (rate >= 125 * MHz)
+ src_clk = SCLK_SFC_SEL_125M;
+ else if (rate >= 100 * MHz)
+ src_clk = SCLK_SFC_SEL_100M;
+ else if (rate >= 75 * MHz)
+ src_clk = SCLK_SFC_SEL_75M;
+ else if (rate >= 50 * MHz)
+ src_clk = SCLK_SFC_SEL_50M;
+ else if (rate >= OSC_HZ)
+ src_clk = SCLK_SFC_SEL_24M;
+ else
return -ENOENT;
- }
rk_clrsetreg(&cru->clksel_con[28],
SCLK_SFC_SEL_MASK,
@@ -2417,6 +2409,8 @@
case BCLK_EMMC:
rate = rk3568_emmc_get_bclk(priv);
break;
+ case CLK_USB3OTG0_REF:
+ case CLK_USB3OTG1_REF:
case TCLK_EMMC:
rate = OSC_HZ;
break;
@@ -2596,6 +2590,8 @@
case BCLK_EMMC:
ret = rk3568_emmc_set_bclk(priv, rate);
break;
+ case CLK_USB3OTG0_REF:
+ case CLK_USB3OTG1_REF:
case TCLK_EMMC:
ret = OSC_HZ;
break;
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 8f33843..4c611a3 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1569,6 +1569,9 @@
case DCLK_DECOM:
rate = rk3588_mmc_get_clk(priv, clk->id);
break;
+ case REF_CLK_USB3OTG0:
+ case REF_CLK_USB3OTG1:
+ case REF_CLK_USB3OTG2:
case TMCLK_EMMC:
case TCLK_WDT0:
rate = OSC_HZ;
@@ -1734,6 +1737,9 @@
case DCLK_DECOM:
ret = rk3588_mmc_set_clk(priv, clk->id, rate);
break;
+ case REF_CLK_USB3OTG0:
+ case REF_CLK_USB3OTG1:
+ case REF_CLK_USB3OTG2:
case TMCLK_EMMC:
case TCLK_WDT0:
ret = OSC_HZ;
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6b06888..6009d55 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -104,7 +104,7 @@
config ROCKCHIP_IODOMAIN
bool "Rockchip IO-domain driver support"
depends on DM_REGULATOR && ARCH_ROCKCHIP
- default y if ROCKCHIP_RK3568
+ default y if ROCKCHIP_RK3328 || ROCKCHIP_RK3568
help
Enable support for IO-domains in Rockchip SoCs. It is necessary
for the IO-domain setting of the SoC to match the voltage supplied
diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c
index 0ffea32..04d4d07 100644
--- a/drivers/misc/rockchip-io-domain.c
+++ b/drivers/misc/rockchip-io-domain.c
@@ -27,6 +27,10 @@
#define MAX_VOLTAGE_1_8 1980000
#define MAX_VOLTAGE_3_3 3600000
+#define RK3328_SOC_CON4 0x410
+#define RK3328_SOC_CON4_VCCIO2 BIT(7)
+#define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
+
#define RK3399_PMUGRF_CON0 0x180
#define RK3399_PMUGRF_CON0_VSEL BIT(8)
#define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
@@ -95,6 +99,22 @@
return regmap_write(grf, offset, val);
}
+static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
+{
+ int ret = rockchip_iodomain_write(grf, offset, idx, uV);
+
+ if (!ret && idx == RK3328_SOC_VCCIO2_SUPPLY_NUM) {
+ /*
+ * set vccio2 iodomain to also use this framework
+ * instead of a special gpio.
+ */
+ u32 val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16);
+ ret = regmap_write(grf, RK3328_SOC_CON4, val);
+ }
+
+ return ret;
+}
+
static int rk3399_pmu_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
{
int ret = rockchip_iodomain_write(grf, offset, idx, uV);
@@ -111,6 +131,20 @@
return ret;
}
+static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
+ .grf_offset = 0x410,
+ .supply_names = {
+ "vccio1-supply",
+ "vccio2-supply",
+ "vccio3-supply",
+ "vccio4-supply",
+ "vccio5-supply",
+ "vccio6-supply",
+ "pmuio-supply",
+ },
+ .write = rk3328_iodomain_write,
+};
+
static const struct rockchip_iodomain_soc_data soc_data_rk3399 = {
.grf_offset = 0xe640,
.supply_names = {
@@ -157,6 +191,10 @@
static const struct udevice_id rockchip_iodomain_ids[] = {
{
+ .compatible = "rockchip,rk3328-io-voltage-domain",
+ .data = (ulong)&soc_data_rk3328,
+ },
+ {
.compatible = "rockchip,rk3399-io-voltage-domain",
.data = (ulong)&soc_data_rk3399,
},
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 706fb12..c889c7b 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -391,6 +391,8 @@
static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
+ struct rockchip_sdhc_plat *plat = dev_get_plat(mmc->dev);
+ struct mmc_config *cfg = &plat->cfg;
u32 reg;
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
@@ -437,6 +439,20 @@
sdhci_writew(host, reg, DWCMSHC_EMMC_EMMC_CTRL);
+ /*
+ * Reading more than 4 blocks with a single CMD18 command in PIO mode
+ * triggers Data End Bit Error using a slower mode than HS200. Limit to
+ * reading max 4 blocks in one command when using PIO mode.
+ */
+ if (!(host->flags & USE_DMA)) {
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == MMC_HS_400_ES)
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ else
+ cfg->b_max = 4;
+ }
+
return 0;
}
@@ -598,16 +614,6 @@
dev_read_bool(dev, "u-boot,spl-fifo-mode"))
host->flags &= ~USE_DMA;
- /*
- * Reading more than 4 blocks with a single CMD18 command in PIO mode
- * triggers Data End Bit Error on RK3568 and RK3588. Limit to reading
- * max 4 blocks in one command when using PIO mode.
- */
- if (!(host->flags & USE_DMA) &&
- (device_is_compatible(dev, "rockchip,rk3568-dwcmshc") ||
- device_is_compatible(dev, "rockchip,rk3588-dwcmshc")))
- cfg->b_max = 4;
-
return sdhci_probe(dev);
}
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index c1bae3f..51f835a 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -19,7 +19,7 @@
#include <asm/arch-rockchip/grf_px30.h>
#include <asm/arch-rockchip/grf_rk322x.h>
#include <asm/arch-rockchip/grf_rk3288.h>
-#include <asm/arch-rk3308/grf_rk3308.h>
+#include <asm/arch-rockchip/grf_rk3308.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/arch-rockchip/grf_rk3368.h>
#include <asm/arch-rockchip/grf_rk3399.h>
@@ -739,7 +739,7 @@
.data = (ulong)&rk3228_gmac_ops },
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)&rk3288_gmac_ops },
- { .compatible = "rockchip,rk3308-mac",
+ { .compatible = "rockchip,rk3308-gmac",
.data = (ulong)&rk3308_gmac_ops },
{ .compatible = "rockchip,rk3328-gmac",
.data = (ulong)&rk3328_gmac_ops },
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index d392aed..43f6e02 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -329,6 +329,22 @@
return ret;
}
+static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
+ {
+ .reg = 0x100,
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0100, 1, 0, 2, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x0104, 1, 0, 2, 1 },
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
{
.reg = 0x100,
@@ -443,6 +459,10 @@
static const struct udevice_id rockchip_usb2phy_ids[] = {
{
+ .compatible = "rockchip,rk3308-usb2phy",
+ .data = (ulong)&rk3308_phy_cfgs,
+ },
+ {
.compatible = "rockchip,rk3328-usb2phy",
.data = (ulong)&rk3328_usb2phy_cfgs,
},
diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c
index 10828e8..2643662 100644
--- a/drivers/ram/rockchip/sdram_rk3308.c
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -7,8 +7,8 @@
#include <dm.h>
#include <ram.h>
#include <syscon.h>
-#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3308.h>
#include <asm/arch-rockchip/sdram.h>
struct dram_info {
diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c
index 8ad7c09..86b16a3 100644
--- a/drivers/tee/sandbox.c
+++ b/drivers/tee/sandbox.c
@@ -174,7 +174,7 @@
uint slot;
u64 val;
char *value;
- u32 value_sz;
+ u32 value_sz, tmp_sz;
switch (func) {
case TA_AVB_CMD_READ_ROLLBACK_INDEX:
@@ -267,8 +267,12 @@
if (!ep)
return TEE_ERROR_ITEM_NOT_FOUND;
- value_sz = strlen(ep->data) + 1;
- memcpy(value, ep->data, value_sz);
+ tmp_sz = strlen(ep->data) + 1;
+ if (value_sz < tmp_sz)
+ return TEE_ERROR_SHORT_BUFFER;
+
+ memcpy(value, ep->data, tmp_sz);
+ params[1].u.memref.size = tmp_sz;
return TEE_SUCCESS;
case TA_AVB_CMD_WRITE_PERSIST_VALUE: