tree 6c488a4a1c1c446416334e3786c6857c9e4a239c
parent 6af975cc8f02102d66b002b7c65eea3df6605a79
author Svyatoslav Ryhel <clamor95@gmail.com> 1700120126 +0200
committer Svyatoslav Ryhel <clamor95@gmail.com> 1703013851 +0200

ARM: tegra114: clock: implement PLLD2 support

PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>