| commit | 6af975cc8f02102d66b002b7c65eea3df6605a79 | [log] [tgz] |
|---|---|---|
| author | Svyatoslav Ryhel <clamor95@gmail.com> | Mon Jul 03 18:11:58 2023 +0300 |
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | Tue Dec 19 21:24:11 2023 +0200 |
| tree | 079f3d6242b77b5fd0de7f429e559a0a5c55de61 | |
| parent | c93b518c6366bef07e1311aef2f01b95f14ef8c8 [diff] |
ARM: tegra30: clock: implement PLLD2 support PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>