diff --git a/Kconfig b/Kconfig
index 9af31e3..75bab7f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -56,6 +56,25 @@
 
 	  This option is enabled by default for U-Boot.
 
+config SYS_MALLOC_F
+	bool "Enable malloc() pool before relocation"
+	default 0x400
+	help
+	  Before relocation memory is very limited on many platforms. Still,
+	  we can provide a small malloc() pool if needed. Driver model in
+	  particular needs this to operate, so that it can allocate the
+	  initial serial device and any others that are needed.
+
+config SYS_MALLOC_F_LEN
+	hex "Size of malloc() pool before relocation"
+	depends on SYS_MALLOC_F
+	default 0x400
+	help
+	  Before relocation memory is very limited on many platforms. Still,
+	  we can provide a small malloc() pool if needed. Driver model in
+	  particular needs this to operate, so that it can allocate the
+	  initial serial device and any others that are needed.
+
 menuconfig EXPERT
         bool "Configure standard U-Boot features (expert users)"
         help
@@ -118,6 +137,7 @@
 config FIT_SIGNATURE
 	bool "Enable signature verification of FIT uImages"
 	depends on FIT
+	depends on DM
 	select RSA
 	help
 	  This option enables signature verification of FIT uImages,
@@ -165,3 +185,5 @@
 source "fs/Kconfig"
 
 source "lib/Kconfig"
+
+source "test/Kconfig"
diff --git a/arch/Kconfig b/arch/Kconfig
index 132123b..3d419bc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -40,6 +40,7 @@
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select SUPPORT_OF_CONTROL
 
 config SANDBOX
 	bool "Sandbox"
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index a8dc4e2..24f5c02 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -8,30 +8,79 @@
 	default y
 
 config SYS_CPU
-	default "arcv1"
+	default "arcv1" if ISA_ARCOMPACT
+	default "arcv2" if ISA_ARCV2
 
 choice
+	prompt "ARC Instruction Set"
+	default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+	bool "ARCompact ISA"
+	help
+	  The original ARC ISA of ARC600/700 cores
+
+config ISA_ARCV2
+	bool "ARC ISA v2"
+	help
+	  ISA for the Next Generation ARC-HS cores
+
+endchoice
+
+choice
 	prompt "CPU selection"
-	default CPU_ARC770D
+	default CPU_ARC770D if ISA_ARCOMPACT
+	default CPU_ARCHS38 if ISA_ARCV2
 
 config CPU_ARC750D
 	bool "ARC 750D"
 	select ARC_MMU_V2
+	depends on ISA_ARCOMPACT
 	help
 	  Choose this option to build an U-Boot for ARC750D CPU.
 
 config CPU_ARC770D
 	bool "ARC 770D"
 	select ARC_MMU_V3
+	depends on ISA_ARCOMPACT
 	help
 	  Choose this option to build an U-Boot for ARC770D CPU.
 
+config CPU_ARCEM6
+	bool "ARC EM6"
+	select ARC_MMU_ABSENT
+	depends on ISA_ARCV2
+	help
+	  Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS36
+	bool "ARC HS36"
+	select ARC_MMU_ABSENT
+	depends on ISA_ARCV2
+	help
+	  Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS38
+	bool "ARC HS38"
+	select ARC_MMU_V4
+	depends on ISA_ARCV2
+	help
+	  Next Generation ARC Core based on ISA-v2 ISA with MMU.
+
 endchoice
 
 choice
 	prompt "MMU Version"
 	default ARC_MMU_V3 if CPU_ARC770D
 	default ARC_MMU_V2 if CPU_ARC750D
+	default ARC_MMU_ABSENT if CPU_ARCEM6
+	default ARC_MMU_ABSENT if CPU_ARCHS36
+	default ARC_MMU_V4 if CPU_ARCHS38
+
+config ARC_MMU_ABSENT
+	bool "No MMU"
+	help
+	  No MMU
 
 config ARC_MMU_V2
 	bool "MMU v2"
@@ -48,6 +97,12 @@
 	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 	  Shared Address Spaces (SASID)
 
+config ARC_MMU_V4
+	bool "MMU v4"
+	depends on CPU_ARCHS38
+	help
+	  Introduced as a part of ARC HS38 release.
+
 endchoice
 
 config CPU_BIG_ENDIAN
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index f1e81b6..4fcd407 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -38,6 +38,18 @@
 PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif
 
+ifdef CONFIG_CPU_ARCEM6
+PLATFORM_CPPFLAGS += -marcem
+endif
+
+ifdef CONFIG_CPU_ARCHS34
+PLATFORM_CPPFLAGS += -marchs
+endif
+
+ifdef CONFIG_CPU_ARCHS38
+PLATFORM_CPPFLAGS += -marchs
+endif
+
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
 
 # Needed for relocation
diff --git a/arch/arc/cpu/arcv2/Makefile b/arch/arc/cpu/arcv2/Makefile
new file mode 100644
index 0000000..cc69e5a
--- /dev/null
+++ b/arch/arc/cpu/arcv2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += start.o
diff --git a/arch/arc/cpu/arcv2/start.S b/arch/arc/cpu/arcv2/start.S
new file mode 100644
index 0000000..3ce6896
--- /dev/null
+++ b/arch/arc/cpu/arcv2/start.S
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+	st.a	\reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+	lr	%r9, [\aux]
+	PUSH	%r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+	PUSH	%r1
+	PUSH	%r2
+	PUSH	%r3
+	PUSH	%r4
+	PUSH	%r5
+	PUSH	%r6
+	PUSH	%r7
+	PUSH	%r8
+	PUSH	%r9
+	PUSH	%r10
+	PUSH	%r11
+	PUSH	%r12
+	PUSH	%r13
+	PUSH	%r14
+	PUSH	%r15
+	PUSH	%r16
+	PUSH	%r17
+	PUSH	%r18
+	PUSH	%r19
+	PUSH	%r20
+	PUSH	%r21
+	PUSH	%r22
+	PUSH	%r23
+	PUSH	%r24
+.endm
+
+.macro SAVE_ALL_SYS
+	/* saving %r0 to reg->r0 in advance since weread %ecr into it */
+	st	%r0, [%sp, -8]
+	lr	%r0, [%ecr]	/* all stack addressing is manual so far */
+	st	%r0, [%sp]
+	st	%sp, [%sp, -4]
+	/* now move %sp to reg->r0 position so we can do "push" automatically */
+	sub	%sp, %sp, 8
+
+	SAVE_R1_TO_R24
+	PUSH	%r25
+	PUSH	%gp
+	PUSH	%fp
+	PUSH	%blink
+	PUSHAX	%eret
+	PUSHAX	%erstatus
+	PUSH	%lp_count
+	PUSHAX	%lp_end
+	PUSHAX	%lp_start
+	PUSHAX	%erbta
+.endm
+
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+	/* If MMU exists exception faulting address is loaded in EFA reg */
+	lr	%r0, [%efa]
+#else
+	/* Otherwise in ERET (exception return) reg */
+	lr	%r0, [%eret]
+#endif
+.endm
+
+.section .ivt, "a",@progbits
+.align 4
+	/* Critical system events */
+.word	_start			/* 0 - 0x000 */
+.word	memory_error		/* 1 - 0x008 */
+.word	instruction_error	/* 2 - 0x010 */
+
+	/* Exceptions */
+.word	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
+.word	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
+.word	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
+.word	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
+							or Misaligned Access  */
+.word	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
+.word	EV_Trap			/* 0x128, Trap exception       (0x25) */
+.word	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */
+
+	/* Device interrupts */
+.rept	29
+	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
+.endr
+
+.text
+.globl _start
+_start:
+	/* Setup interrupt vector base that matches "__text_start" */
+	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+	/* Setup stack pointer */
+	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
+	mov	%fp, %sp
+
+	/* Clear bss */
+	mov	%r0, __bss_start
+	mov	%r1, __bss_end
+
+clear_bss:
+	st.ab	0, [%r0, 4]
+	brlt	%r0, %r1, clear_bss
+
+	/* Zero the one and only argument of "board_init_f" */
+	mov_s	%r0, 0
+	j	board_init_f
+
+memory_error:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_memory_error
+
+instruction_error:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_instruction_error
+
+interrupt_handler:
+	/* Todo - save and restore CPU context when interrupts will be in use */
+	bl	do_interrupt_handler
+	rtie
+
+EV_MachineCheck:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_machine_check_fault
+
+EV_TLBMissI:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_itlb_miss
+
+EV_TLBMissD:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_dtlb_miss
+
+EV_TLBProtV:
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_tlb_prot_violation
+
+EV_PrivilegeV:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_privilege_violation
+
+EV_Trap:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_trap
+
+EV_Extension:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_extension
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl	relocate_code
+relocate_code:
+	/*
+	 * r0-r12 might be clobbered by C functions
+	 * so we use r13-r16 for storage here
+	 */
+	mov	%r13, %r0		/* save addr_sp */
+	mov	%r14, %r1		/* save addr of gd */
+	mov	%r15, %r2		/* save addr of destination */
+
+	mov	%r16, %r2		/* %r9 - relocation offset */
+	sub	%r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+	mov	%sp, %r13
+	mov	%fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+	mov	%r0, __image_copy_start
+	cmp	%r0, %r15		/* skip relocation if code loaded */
+	bz	do_board_init_r		/* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+	mov	%r1, %r15
+	mov	%r2, __image_copy_end
+	sub	%r2, %r2, %r0		/* r3 <- amount of bytes to copy */
+	asr	%r2, %r2, 2		/* r3 <- amount of words to copy */
+	mov	%lp_count, %r2
+	lp	copy_end
+	ld.ab	%r2,[%r0,4]
+	st.ab	%r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+	bl	do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+	bl	invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	bl	flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+	lr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Read current position */
+	add	%r0, %r0, %r16			/* Update address */
+	sr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+	mov	%r2, board_init_r	/* old address of "board_init_r()" */
+	add	%r2, %r2, %r16		/* new address of "board_init_r()" */
+	mov	%r0, %r14		/* 1-st parameter: gd_t */
+	mov	%r1, %r15		/* 2-nd parameter: dest_addr */
+	j	[%r2]
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 2725961..8a77cd9 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -17,10 +17,14 @@
 #define ARCH_DMA_MINALIGN		128
 #endif
 
-#if defined(CONFIG_ARC_MMU_V2)
+#if defined(ARC_MMU_ABSENT)
+#define CONFIG_ARC_MMU_VER 0
+#elif defined(CONFIG_ARC_MMU_V2)
 #define CONFIG_ARC_MMU_VER 2
 #elif defined(CONFIG_ARC_MMU_V3)
 #define CONFIG_ARC_MMU_VER 3
+#elif defined(CONFIG_ARC_MMU_V4)
+#define CONFIG_ARC_MMU_VER 4
 #endif
 
 #endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f1ccad..41f3220 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -839,6 +839,8 @@
 
 source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
 
+source "arch/arm/cpu/arm1176/bcm2835/Kconfig"
+
 source "arch/arm/cpu/armv7/exynos/Kconfig"
 
 source "arch/arm/cpu/armv7/highbank/Kconfig"
diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig
new file mode 100644
index 0000000..94f57d7
--- /dev/null
+++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RPI
+
+config DM
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+endif
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 7fcb5d2..2064efa 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -65,6 +65,27 @@
 config SYS_SOC
 	default "exynos"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
+config DM_SPI
+	default y if !SPL_BUILD
+
+config DM_SPI_FLASH
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config SYS_MALLOC_F
+	default y if !SPL_BUILD
+
+config SYS_MALLOC_F_LEN
+	default 0x400 if !SPL_BUILD
+
 source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index a029379..4644098 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -93,6 +93,21 @@
 
 endchoice
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if DM && !SPL_BUILD
+
+config DM_SERIAL
+	default y if DM && !SPL_BUILD
+
+config SYS_MALLOC_F
+	default y if DM && !SPL_BUILD
+
+config SYS_MALLOC_F_LEN
+	default 0x400 if DM && !SPL_BUILD
+
 config SYS_SOC
 	default "omap3"
 
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6d94199..3586650 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -21,6 +21,9 @@
 config TARGET_ALT
 	bool "Alt board"
 
+config TARGET_SILK
+	bool "Silk board"
+
 endchoice
 
 config SYS_SOC
@@ -28,7 +31,7 @@
 
 config RMOBILE_EXTRAM_BOOT
 	bool "Enable boot from RAM"
-	depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+	depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
 	default n
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
@@ -37,5 +40,6 @@
 source "board/renesas/lager/Kconfig"
 source "board/kmc/kzm9g/Kconfig"
 source "board/renesas/alt/Kconfig"
+source "board/renesas/silk/Kconfig"
 
 endif
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index d47546a..a5dbbea 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -40,7 +40,7 @@
 	and	r1, r1, #0x7F00
 	lsrs	r1, r1, #8
 	cmp	r1, #0x4C		/* 0x4C is ID of r8a7794 */
-	beq	_exit_init_l2_a15
+	beq	_enable_actlr_smp
 
 	/* surpress wfe if ca15 */
 	tst r4, #4
@@ -64,6 +64,16 @@
 	orrne r0, r0, #0x20		/* L2CTLR[5] */
 #endif
 	mcrne p15, 1, r0, c9, c0, 2
+
+	b	_exit_init_l2_a15
+
+_enable_actlr_smp: /* R8A7794 only (CA7) */
+#ifndef CONFIG_DCACHE_OFF
+	mrc    p15, 0, r0, c1, c0, 1
+	orr    r0, r0, #0x40
+	mcr    p15, 0, r0, c1, c0, 1
+#endif
+
 _exit_init_l2_a15:
 	ldr	r3, =(CONFIG_SYS_INIT_SP_ADDR)
 	sub	sp, r3, #4
diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig
index 1446452..ee32469 100644
--- a/arch/arm/cpu/armv7/tegra-common/Kconfig
+++ b/arch/arm/cpu/armv7/tegra-common/Kconfig
@@ -17,9 +17,33 @@
 
 endchoice
 
+config SYS_MALLOC_F
+	default y
+
+config SYS_MALLOC_F_LEN
+	default 0x1800
+
 config USE_PRIVATE_LIBGCC
 	default y if SPL_BUILD
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
+config DM_SPI
+	default y if !SPL_BUILD
+
+config DM_SPI_FLASH
+	default y if !SPL_BUILD
+
+config DM_I2C
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
 source "arch/arm/cpu/armv7/tegra20/Kconfig"
 source "arch/arm/cpu/armv7/tegra30/Kconfig"
 source "arch/arm/cpu/armv7/tegra114/Kconfig"
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 5c5a84f..1a47ac9 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -48,6 +48,12 @@
 
 endchoice
 
+config SYS_MALLOC_F
+	default y
+
+config SYS_MALLOC_F_LEN
+	default 0x2000
+
 config CMD_PINMON
 	bool "Enable boot mode pins monitor command"
 	default y
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h
index 50464ff..3012278 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -114,14 +114,10 @@
 		at91_port_t	pioa;
 		at91_port_t	piob;
 		at91_port_t	pioc;
-	#if (ATMEL_PIO_PORTS > 3)
-		at91_port_t	piod;
-	#endif
-	#if (ATMEL_PIO_PORTS > 4)
-		at91_port_t	pioe;
-	#endif
-	} ;
-	at91_port_t port[ATMEL_PIO_PORTS];
+		at91_port_t	piod;	/* not present in all hardware */
+		at91_port_t	pioe;/* not present in all hardware */
+	};
+	at91_port_t port[5];
 } at91_pio_t;
 
 #ifdef CONFIG_AT91_GPIO
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 71bb9d7..7202c3f 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -424,6 +424,14 @@
 	int write_recovery;
 	phys_size_t dram_size = 0;
 
+	if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) {
+		/*
+		 * Reduce RAM size to avoid overwriting memory used by
+		 * current stack? Not sure what is happening.
+		 */
+		return sdram_memsize() / 2;
+	}
+
 	num_dimm_banks = sizeof(iic0_dimm_addr);
 
 	/*------------------------------------------------------------------
diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk
index f87c9dc..9cb41bb 100644
--- a/arch/powerpc/cpu/ppc4xx/config.mk
+++ b/arch/powerpc/cpu/ppc4xx/config.mk
@@ -7,10 +7,7 @@
 
 PLATFORM_CPPFLAGS += -mstring -msoft-float
 
-cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
-is440:=$(shell grep CONFIG_440 $(cfg))
-
-ifneq (,$(findstring CONFIG_440,$(is440)))
+ifneq (,$(CONFIG_440))
 PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
 else
 PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index e5a0e21..5f5c720 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -450,10 +450,12 @@
 	      PLB4Ax_ACR_RDP_4DEEP);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 
+#ifndef CONFIG_SYS_GENERIC_BOARD
 	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
 	/* Clear initial global data */
 	memset((void *)gd, 0, sizeof(gd_t));
+#endif
 }
 
 /*
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 09a02d7..7a0f0d2 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -760,6 +760,15 @@
 #endif
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
+#ifdef CONFIG_SYS_GENERIC_BOARD
+	mr	r3, r1
+	bl	board_init_f_mem
+	mr	r1, r3
+	li	r0,0
+	stwu	r0, -4(r1)
+	stwu	r0, -4(r1)
+#endif
+	li	r3, 0
 	bl	board_init_f
 	/* NOTREACHED - board_init_f() does not return */
 
@@ -1027,7 +1036,14 @@
 	GET_GOT			/* initialize GOT access			*/
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
-
+#ifdef CONFIG_SYS_GENERIC_BOARD
+	mr	r3, r1
+	bl	board_init_f_mem
+	mr	r1, r3
+	stwu	r0, -4(r1)
+	stwu	r0, -4(r1)
+#endif
+	li	r3, 0
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
 	/* NOTREACHED - board_init_f() does not return */
 
diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds
index 8773178..1980508 100644
--- a/arch/powerpc/cpu/ppc4xx/u-boot.lds
+++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds
@@ -76,9 +76,13 @@
   . = ALIGN(256);
   __init_begin = .;
   .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
+  .data.init : {
+	*(.data.init)
+	. = ALIGN(256);
+	LONG(0) LONG(0)		/* Extend u-boot.bin to here */
+  }
   __init_end = .;
+  _end = .;
 
 #ifndef CONFIG_SPL
 #ifdef CONFIG_440
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
new file mode 100644
index 0000000..ad104b9
--- /dev/null
+++ b/arch/powerpc/dts/Makefile
@@ -0,0 +1,11 @@
+dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/arch/powerpc/dts/arches.dts b/arch/powerpc/dts/arches.dts
new file mode 100644
index 0000000..bd5ebfd
--- /dev/null
+++ b/arch/powerpc/dts/arches.dts
@@ -0,0 +1,339 @@
+/*
+ * Device Tree Source for AMCC Arches (dual 460GT board)
+ *
+ * (C) Copyright 2008 Applied Micro Circuits Corporation
+ * Victor Gallardo <vgallardo@amcc.com>
+ * Adam Graham <agraham@amcc.com>
+ *
+ * Based on the glacier.dts file
+ *   Stefan Roese <sr@denx.de>
+ *   Copyright 2008 DENX Software Engineering
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "amcc,arches";
+	compatible = "amcc,arches";
+	dcr-parent = <&{/cpus/cpu@0}>;
+
+	aliases {
+		ethernet0 = &EMAC0;
+		ethernet1 = &EMAC1;
+		ethernet2 = &EMAC2;
+		serial0 = &UART0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			model = "PowerPC,460GT";
+			reg = <0x00000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+			timebase-frequency = <0>; /* Filled in by U-Boot */
+			i-cache-line-size = <32>;
+			d-cache-line-size = <32>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+			dcr-controller;
+			dcr-access-method = "native";
+			next-level-cache = <&L2C0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+	};
+
+	UIC0: interrupt-controller0 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <0>;
+		dcr-reg = <0x0c0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+
+	UIC1: interrupt-controller1 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <1>;
+		dcr-reg = <0x0d0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC2: interrupt-controller2 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <2>;
+		dcr-reg = <0x0e0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC3: interrupt-controller3 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <3>;
+		dcr-reg = <0x0f0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	SDR0: sdr {
+		compatible = "ibm,sdr-460gt";
+		dcr-reg = <0x00e 0x002>;
+	};
+
+	CPR0: cpr {
+		compatible = "ibm,cpr-460gt";
+		dcr-reg = <0x00c 0x002>;
+	};
+
+	L2C0: l2c {
+		compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
+		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
+			   0x030 0x008>;	/* L2 cache DCR's */
+		cache-line-size = <32>;		/* 32 bytes */
+		cache-size = <262144>;		/* L2, 256K */
+		interrupt-parent = <&UIC1>;
+		interrupts = <11 1>;
+	};
+
+	plb {
+		compatible = "ibm,plb-460gt", "ibm,plb4";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+		clock-frequency = <0>; /* Filled in by U-Boot */
+
+		SDRAM0: sdram {
+			compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
+			dcr-reg = <0x010 0x002>;
+		};
+
+		CRYPTO: crypto@180000 {
+			compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
+			reg = <4 0x00180000 0x80400>;
+			interrupt-parent = <&UIC0>;
+			interrupts = <0x1d 0x4>;
+		};
+
+		MAL0: mcmal {
+			compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
+			dcr-reg = <0x180 0x062>;
+			num-tx-chans = <3>;
+			num-rx-chans = <24>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-parent = <&UIC2>;
+			interrupts = <	/*TXEOB*/ 0x6 0x4
+					/*RXEOB*/ 0x7 0x4
+					/*SERR*/  0x3 0x4
+					/*TXDE*/  0x4 0x4
+					/*RXDE*/  0x5 0x4>;
+			desc-base-addr-high = <0x8>;
+		};
+
+		POB0: opb {
+			compatible = "ibm,opb-460gt", "ibm,opb";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+
+			EBC0: ebc {
+				compatible = "ibm,ebc-460gt", "ibm,ebc";
+				dcr-reg = <0x012 0x002>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				/* ranges property is supplied by U-Boot */
+				interrupts = <0x6 0x4>;
+				interrupt-parent = <&UIC1>;
+
+				nor_flash@0,0 {
+					compatible = "amd,s29gl256n", "cfi-flash";
+					bank-width = <2>;
+					reg = <0x00000000 0x00000000 0x02000000>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					partition@0 {
+						label = "kernel";
+						reg = <0x00000000 0x001e0000>;
+					};
+					partition@1e0000 {
+						label = "dtb";
+						reg = <0x001e0000 0x00020000>;
+					};
+					partition@200000 {
+						label = "root";
+						reg = <0x00200000 0x00200000>;
+					};
+					partition@400000 {
+						label = "user";
+						reg = <0x00400000 0x01b60000>;
+					};
+					partition@1f60000 {
+						label = "env";
+						reg = <0x01f60000 0x00040000>;
+					};
+					partition@1fa0000 {
+						label = "u-boot";
+						reg = <0x01fa0000 0x00060000>;
+					};
+				};
+			};
+
+			UART0: serial@ef600300 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <0xef600300 0x00000008>;
+				virtual-reg = <0xef600300>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <0x1 0x4>;
+			};
+
+			IIC0: i2c@ef600700 {
+				compatible = "ibm,iic-460gt", "ibm,iic";
+				reg = <0xef600700 0x00000014>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x2 0x4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				sttm@4a {
+					compatible = "ad,ad7414";
+					reg = <0x4a>;
+					interrupt-parent = <&UIC1>;
+					interrupts = <0x0 0x8>;
+				};
+			};
+
+			IIC1: i2c@ef600800 {
+				compatible = "ibm,iic-460gt", "ibm,iic";
+				reg = <0xef600800 0x00000014>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x3 0x4>;
+			};
+
+			TAH0: emac-tah@ef601350 {
+				compatible = "ibm,tah-460gt", "ibm,tah";
+				reg = <0xef601350 0x00000030>;
+			};
+
+			TAH1: emac-tah@ef601450 {
+				compatible = "ibm,tah-460gt", "ibm,tah";
+				reg = <0xef601450 0x00000030>;
+			};
+
+			EMAC0: ethernet@ef600e00 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4sync";
+				interrupt-parent = <&EMAC0>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
+						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
+				reg = <0xef600e00 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <0>;
+				mal-rx-channel = <0>;
+				cell-index = <0>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				phy-mode = "sgmii";
+				phy-map = <0xffffffff>;
+				gpcs-address = <0x0000000a>;
+				tah-device = <&TAH0>;
+				tah-channel = <0>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+			};
+
+			EMAC1: ethernet@ef600f00 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4sync";
+				interrupt-parent = <&EMAC1>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
+						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
+				reg = <0xef600f00 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <1>;
+				mal-rx-channel = <8>;
+				cell-index = <1>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				phy-mode = "sgmii";
+				phy-map = <0x00000000>;
+				gpcs-address = <0x0000000b>;
+				tah-device = <&TAH1>;
+				tah-channel = <1>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+
+			EMAC2: ethernet@ef601100 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4sync";
+				interrupt-parent = <&EMAC2>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
+						 /*Wake*/   0x1 &UIC2 0x16 0x4>;
+				reg = <0xef601100 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <2>;
+				mal-rx-channel = <16>;
+				cell-index = <2>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				tx-fifo-size-gige = <16384>; /* emac2&3 only */
+				phy-mode = "sgmii";
+				phy-map = <0x00000001>;
+				gpcs-address = <0x0000000C>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+		};
+	};
+};
diff --git a/arch/powerpc/dts/canyonlands.dts b/arch/powerpc/dts/canyonlands.dts
new file mode 100644
index 0000000..0a2f5d7
--- /dev/null
+++ b/arch/powerpc/dts/canyonlands.dts
@@ -0,0 +1,561 @@
+/*
+ * Device Tree Source for AMCC Canyonlands (460EX)
+ *
+ * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "amcc,canyonlands";
+	compatible = "amcc,canyonlands";
+	dcr-parent = <&{/cpus/cpu@0}>;
+
+	aliases {
+		ethernet0 = &EMAC0;
+		ethernet1 = &EMAC1;
+		serial0 = &UART0;
+		serial1 = &UART1;
+	};
+
+	chosen {
+		stdout-path = &UART0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			model = "PowerPC,460EX";
+			reg = <0x00000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+			timebase-frequency = <0>; /* Filled in by U-Boot */
+			i-cache-line-size = <32>;
+			d-cache-line-size = <32>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+			dcr-controller;
+			dcr-access-method = "native";
+			next-level-cache = <&L2C0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+	};
+
+	UIC0: interrupt-controller0 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <0>;
+		dcr-reg = <0x0c0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+
+	UIC1: interrupt-controller1 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <1>;
+		dcr-reg = <0x0d0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC2: interrupt-controller2 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <2>;
+		dcr-reg = <0x0e0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC3: interrupt-controller3 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <3>;
+		dcr-reg = <0x0f0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	SDR0: sdr {
+		compatible = "ibm,sdr-460ex";
+		dcr-reg = <0x00e 0x002>;
+	};
+
+	CPR0: cpr {
+		compatible = "ibm,cpr-460ex";
+		dcr-reg = <0x00c 0x002>;
+	};
+
+	CPM0: cpm {
+		compatible = "ibm,cpm";
+		dcr-access-method = "native";
+		dcr-reg = <0x160 0x003>;
+		unused-units = <0x00000100>;
+		idle-doze = <0x02000000>;
+		standby = <0xfeff791d>;
+	};
+
+	L2C0: l2c {
+		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
+		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
+			   0x030 0x008>;	/* L2 cache DCR's */
+		cache-line-size = <32>;		/* 32 bytes */
+		cache-size = <262144>;		/* L2, 256K */
+		interrupt-parent = <&UIC1>;
+		interrupts = <11 1>;
+	};
+
+	plb {
+		compatible = "ibm,plb-460ex", "ibm,plb4";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+		clock-frequency = <0>; /* Filled in by U-Boot */
+
+		SDRAM0: sdram {
+			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
+			dcr-reg = <0x010 0x002>;
+		};
+
+		CRYPTO: crypto@180000 {
+			compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
+			reg = <4 0x00180000 0x80400>;
+			interrupt-parent = <&UIC0>;
+			interrupts = <0x1d 0x4>;
+		};
+
+		HWRNG: hwrng@110000 {
+			compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
+			reg = <4 0x00110000 0x50>;
+		};
+
+		MAL0: mcmal {
+			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
+			dcr-reg = <0x180 0x062>;
+			num-tx-chans = <2>;
+			num-rx-chans = <16>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-parent = <&UIC2>;
+			interrupts = <	/*TXEOB*/ 0x6 0x4
+					/*RXEOB*/ 0x7 0x4
+					/*SERR*/  0x3 0x4
+					/*TXDE*/  0x4 0x4
+					/*RXDE*/  0x5 0x4>;
+		};
+
+		USB0: ehci@bffd0400 {
+			compatible = "ibm,usb-ehci-460ex", "usb-ehci";
+			interrupt-parent = <&UIC2>;
+			interrupts = <0x1d 4>;
+			reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
+		};
+
+		USB1: usb@bffd0000 {
+			compatible = "ohci-le";
+			reg = <4 0xbffd0000 0x60>;
+			interrupt-parent = <&UIC2>;
+			interrupts = <0x1e 4>;
+		};
+
+		USBOTG0: usbotg@bff80000 {
+			compatible = "amcc,dwc-otg";
+			reg = <0x4 0xbff80000 0x10000>;
+			interrupt-parent = <&USBOTG0>;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x1 0x2>;
+			interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
+					 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
+					 /* DMA */ 0x2 &UIC0 0xc 0x4>;
+		};
+
+		SATA0: sata@bffd1000 {
+			compatible = "amcc,sata-460ex";
+			reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
+			interrupt-parent = <&UIC3>;
+			interrupts = <0x0 0x4       /* SATA */
+				      0x5 0x4>;     /* AHBDMA */
+		};
+
+		POB0: opb {
+			compatible = "ibm,opb-460ex", "ibm,opb";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+
+			EBC0: ebc {
+				compatible = "ibm,ebc-460ex", "ibm,ebc";
+				dcr-reg = <0x012 0x002>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				/* ranges property is supplied by U-Boot */
+				interrupts = <0x6 0x4>;
+				interrupt-parent = <&UIC1>;
+
+				nor_flash@0,0 {
+					compatible = "amd,s29gl512n", "cfi-flash";
+					bank-width = <2>;
+					reg = <0x00000000 0x00000000 0x04000000>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					partition@0 {
+						label = "kernel";
+						reg = <0x00000000 0x001e0000>;
+					};
+					partition@1e0000 {
+						label = "dtb";
+						reg = <0x001e0000 0x00020000>;
+					};
+					partition@200000 {
+						label = "ramdisk";
+						reg = <0x00200000 0x01400000>;
+					};
+					partition@1600000 {
+						label = "jffs2";
+						reg = <0x01600000 0x00400000>;
+					};
+					partition@1a00000 {
+						label = "user";
+						reg = <0x01a00000 0x02560000>;
+					};
+					partition@3f60000 {
+						label = "env";
+						reg = <0x03f60000 0x00040000>;
+					};
+					partition@3fa0000 {
+						label = "u-boot";
+						reg = <0x03fa0000 0x00060000>;
+					};
+				};
+
+				cpld@2,0 {
+					compatible = "amcc,ppc460ex-bcsr";
+					reg = <2 0x0 0x9>;
+				};
+
+				ndfc@3,0 {
+					compatible = "ibm,ndfc";
+					reg = <0x00000003 0x00000000 0x00002000>;
+					ccr = <0x00001000>;
+					bank-settings = <0x80002222>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					nand {
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						partition@0 {
+							label = "u-boot";
+							reg = <0x00000000 0x00100000>;
+						};
+						partition@100000 {
+							label = "user";
+							reg = <0x00000000 0x03f00000>;
+						};
+					};
+				};
+			};
+
+			UART0: serial@ef600300 {
+				device_type = "serial";
+				reg-shift = <0>;
+				compatible = "ns16550";
+				reg = <0xef600300 0x00000008>;
+				virtual-reg = <0xef600300>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <0x1 0x4>;
+			};
+
+			UART1: serial@ef600400 {
+				device_type = "serial";
+				reg-shift = <0>;
+				compatible = "ns16550";
+				reg = <0xef600400 0x00000008>;
+				virtual-reg = <0xef600400>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x1 0x4>;
+			};
+
+			IIC0: i2c@ef600700 {
+				compatible = "ibm,iic-460ex", "ibm,iic";
+				reg = <0xef600700 0x00000014>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x2 0x4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+                                rtc@68 {
+                                        compatible = "stm,m41t80";
+                                        reg = <0x68>;
+					interrupt-parent = <&UIC2>;
+					interrupts = <0x19 0x8>;
+                                };
+                                sttm@48 {
+                                        compatible = "ad,ad7414";
+                                        reg = <0x48>;
+					interrupt-parent = <&UIC1>;
+					interrupts = <0x14 0x8>;
+                                };
+			};
+
+			IIC1: i2c@ef600800 {
+				compatible = "ibm,iic-460ex", "ibm,iic";
+				reg = <0xef600800 0x00000014>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x3 0x4>;
+			};
+
+			GPIO0: gpio@ef600b00 {
+				compatible = "ibm,ppc4xx-gpio";
+				reg = <0xef600b00 0x00000048>;
+				gpio-controller;
+			};
+
+			ZMII0: emac-zmii@ef600d00 {
+				compatible = "ibm,zmii-460ex", "ibm,zmii";
+				reg = <0xef600d00 0x0000000c>;
+			};
+
+			RGMII0: emac-rgmii@ef601500 {
+				compatible = "ibm,rgmii-460ex", "ibm,rgmii";
+				reg = <0xef601500 0x00000008>;
+				has-mdio;
+			};
+
+			TAH0: emac-tah@ef601350 {
+				compatible = "ibm,tah-460ex", "ibm,tah";
+				reg = <0xef601350 0x00000030>;
+			};
+
+			TAH1: emac-tah@ef601450 {
+				compatible = "ibm,tah-460ex", "ibm,tah";
+				reg = <0xef601450 0x00000030>;
+			};
+
+			EMAC0: ethernet@ef600e00 {
+				device_type = "network";
+				compatible = "ibm,emac-460ex", "ibm,emac4sync";
+				interrupt-parent = <&EMAC0>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
+						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
+				reg = <0xef600e00 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <0>;
+				mal-rx-channel = <0>;
+				cell-index = <0>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				phy-mode = "rgmii";
+				phy-map = <0x00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <0>;
+				tah-device = <&TAH0>;
+				tah-channel = <0>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+			};
+
+			EMAC1: ethernet@ef600f00 {
+				device_type = "network";
+				compatible = "ibm,emac-460ex", "ibm,emac4sync";
+				interrupt-parent = <&EMAC1>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
+						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
+				reg = <0xef600f00 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <1>;
+				mal-rx-channel = <8>;
+				cell-index = <1>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				phy-mode = "rgmii";
+				phy-map = <0x00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <1>;
+				tah-device = <&TAH1>;
+				tah-channel = <1>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+		};
+
+		PCIX0: pci@c0ec00000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
+			primary;
+			large-inbound-windows;
+			enable-msi-hole;
+			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
+			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
+			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
+			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
+			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
+				  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
+				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+			/* This drives busses 0 to 0x3f */
+			bus-range = <0x0 0x3f>;
+
+			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
+		};
+
+		PCIE0: pciex@d00000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <0x0>; /* port number */
+			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
+			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
+			dcr-reg = <0x100 0x020>;
+			sdr-base = <0x300>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
+				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+			/* This drives busses 40 to 0x7f */
+			bus-range = <0x40 0x7f>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <
+				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
+				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
+				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
+				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
+		};
+
+		PCIE1: pciex@d20000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <0x1>; /* port number */
+			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
+			       0x0000000c 0x08011000 0x00001000>;	/* Registers */
+			dcr-reg = <0x120 0x020>;
+			sdr-base = <0x340>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
+				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
+				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+			/* This drives busses 80 to 0xbf */
+			bus-range = <0x80 0xbf>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <
+				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
+				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
+				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
+				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
+		};
+
+		MSI: ppc4xx-msi@C10000000 {
+			compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+			reg = < 0xC 0x10000000 0x100>;
+			sdr-base = <0x36C>;
+			msi-data = <0x00000000>;
+			msi-mask = <0x44440000>;
+			interrupt-count = <3>;
+			interrupts = <0 1 2 3>;
+			interrupt-parent = <&UIC3>;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-map = <0 &UIC3 0x18 1
+					1 &UIC3 0x19 1
+					2 &UIC3 0x1A 1
+					3 &UIC3 0x1B 1>;
+		};
+	};
+};
diff --git a/arch/powerpc/dts/glacier.dts b/arch/powerpc/dts/glacier.dts
new file mode 100644
index 0000000..bb4e819
--- /dev/null
+++ b/arch/powerpc/dts/glacier.dts
@@ -0,0 +1,582 @@
+/*
+ * Device Tree Source for AMCC Glacier (460GT)
+ *
+ * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "amcc,glacier";
+	compatible = "amcc,glacier";
+	dcr-parent = <&{/cpus/cpu@0}>;
+
+	aliases {
+		ethernet0 = &EMAC0;
+		ethernet1 = &EMAC1;
+		ethernet2 = &EMAC2;
+		ethernet3 = &EMAC3;
+		serial0 = &UART0;
+		serial1 = &UART1;
+	};
+
+	chosen {
+		stdout-path = &UART0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			model = "PowerPC,460GT";
+			reg = <0x00000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+			timebase-frequency = <0>; /* Filled in by U-Boot */
+			i-cache-line-size = <32>;
+			d-cache-line-size = <32>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+			dcr-controller;
+			dcr-access-method = "native";
+			next-level-cache = <&L2C0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+	};
+
+	UIC0: interrupt-controller0 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <0>;
+		dcr-reg = <0x0c0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+
+	UIC1: interrupt-controller1 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <1>;
+		dcr-reg = <0x0d0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC2: interrupt-controller2 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <2>;
+		dcr-reg = <0x0e0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC3: interrupt-controller3 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <3>;
+		dcr-reg = <0x0f0 0x009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	SDR0: sdr {
+		compatible = "ibm,sdr-460gt";
+		dcr-reg = <0x00e 0x002>;
+	};
+
+	CPR0: cpr {
+		compatible = "ibm,cpr-460gt";
+		dcr-reg = <0x00c 0x002>;
+	};
+
+	L2C0: l2c {
+		compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
+		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
+			   0x030 0x008>;	/* L2 cache DCR's */
+		cache-line-size = <32>;		/* 32 bytes */
+		cache-size = <262144>;		/* L2, 256K */
+		interrupt-parent = <&UIC1>;
+		interrupts = <11 1>;
+	};
+
+	plb {
+		compatible = "ibm,plb-460gt", "ibm,plb4";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+		clock-frequency = <0>; /* Filled in by U-Boot */
+
+		SDRAM0: sdram {
+			compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
+			dcr-reg = <0x010 0x002>;
+		};
+
+		CRYPTO: crypto@180000 {
+			compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
+				"amcc,ppc4xx-crypto";
+			reg = <4 0x00180000 0x80400>;
+			interrupt-parent = <&UIC0>;
+			interrupts = <0x1d 0x4>;
+		};
+
+		HWRNG: hwrng@110000 {
+			compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
+			reg = <4 0x00110000 0x50>;
+		};
+
+		MAL0: mcmal {
+			compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
+			dcr-reg = <0x180 0x062>;
+			num-tx-chans = <4>;
+			num-rx-chans = <32>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-parent = <&UIC2>;
+			interrupts = <	/*TXEOB*/ 0x6 0x4
+					/*RXEOB*/ 0x7 0x4
+					/*SERR*/  0x3 0x4
+					/*TXDE*/  0x4 0x4
+					/*RXDE*/  0x5 0x4>;
+			desc-base-addr-high = <0x8>;
+		};
+
+		POB0: opb {
+			compatible = "ibm,opb-460gt", "ibm,opb";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+
+			EBC0: ebc {
+				compatible = "ibm,ebc-460gt", "ibm,ebc";
+				dcr-reg = <0x012 0x002>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				/* ranges property is supplied by U-Boot */
+				interrupts = <0x6 0x4>;
+				interrupt-parent = <&UIC1>;
+
+				nor_flash@0,0 {
+					compatible = "amd,s29gl512n", "cfi-flash";
+					bank-width = <2>;
+					reg = <0x00000000 0x00000000 0x04000000>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					partition@0 {
+						label = "kernel";
+						reg = <0x00000000 0x001e0000>;
+					};
+					partition@1e0000 {
+						label = "dtb";
+						reg = <0x001e0000 0x00020000>;
+					};
+					partition@200000 {
+						label = "ramdisk";
+						reg = <0x00200000 0x01400000>;
+					};
+					partition@1600000 {
+						label = "jffs2";
+						reg = <0x01600000 0x00400000>;
+					};
+					partition@1a00000 {
+						label = "user";
+						reg = <0x01a00000 0x02560000>;
+					};
+					partition@3f60000 {
+						label = "env";
+						reg = <0x03f60000 0x00040000>;
+					};
+					partition@3fa0000 {
+						label = "u-boot";
+						reg = <0x03fa0000 0x00060000>;
+					};
+				};
+
+				ndfc@3,0 {
+					compatible = "ibm,ndfc";
+					reg = <0x00000003 0x00000000 0x00002000>;
+					ccr = <0x00001000>;
+					bank-settings = <0x80002222>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					nand {
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						partition@0 {
+							label = "u-boot";
+							reg = <0x00000000 0x00100000>;
+						};
+						partition@100000 {
+							label = "user";
+							reg = <0x00000000 0x03f00000>;
+						};
+					};
+				};
+			};
+
+			UART0: serial@ef600300 {
+				device_type = "serial";
+				reg-shift = <0>;
+				compatible = "ns16550";
+				reg = <0xef600300 0x00000008>;
+				virtual-reg = <0xef600300>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <0x1 0x4>;
+			};
+
+			UART1: serial@ef600400 {
+				device_type = "serial";
+				reg-shift = <0>;
+				compatible = "ns16550";
+				reg = <0xef600400 0x00000008>;
+				virtual-reg = <0xef600400>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x1 0x4>;
+			};
+
+			UART2: serial@ef600500 {
+				device_type = "serial";
+				reg-shift = <0>;
+				compatible = "ns16550";
+				reg = <0xef600500 0x00000008>;
+				virtual-reg = <0xef600500>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <28 0x4>;
+			};
+
+			UART3: serial@ef600600 {
+				device_type = "serial";
+				reg-shift = <0>;
+				compatible = "ns16550";
+				reg = <0xef600600 0x00000008>;
+				virtual-reg = <0xef600600>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <29 0x4>;
+			};
+
+			IIC0: i2c@ef600700 {
+				compatible = "ibm,iic-460gt", "ibm,iic";
+				reg = <0xef600700 0x00000014>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x2 0x4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				rtc@68 {
+					compatible = "stm,m41t80";
+					reg = <0x68>;
+					interrupt-parent = <&UIC2>;
+					interrupts = <0x19 0x8>;
+				};
+				sttm@48 {
+					compatible = "ad,ad7414";
+					reg = <0x48>;
+					interrupt-parent = <&UIC1>;
+					interrupts = <0x14 0x8>;
+				};
+			};
+
+			IIC1: i2c@ef600800 {
+				compatible = "ibm,iic-460gt", "ibm,iic";
+				reg = <0xef600800 0x00000014>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <0x3 0x4>;
+			};
+
+			ZMII0: emac-zmii@ef600d00 {
+				compatible = "ibm,zmii-460gt", "ibm,zmii";
+				reg = <0xef600d00 0x0000000c>;
+			};
+
+			RGMII0: emac-rgmii@ef601500 {
+				compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+				reg = <0xef601500 0x00000008>;
+				has-mdio;
+			};
+
+			RGMII1: emac-rgmii@ef601600 {
+				compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+				reg = <0xef601600 0x00000008>;
+				has-mdio;
+			};
+
+			TAH0: emac-tah@ef601350 {
+				compatible = "ibm,tah-460gt", "ibm,tah";
+				reg = <0xef601350 0x00000030>;
+			};
+
+			TAH1: emac-tah@ef601450 {
+				compatible = "ibm,tah-460gt", "ibm,tah";
+				reg = <0xef601450 0x00000030>;
+			};
+
+			EMAC0: ethernet@ef600e00 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4sync";
+				interrupt-parent = <&EMAC0>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
+						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
+				reg = <0xef600e00 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <0>;
+				mal-rx-channel = <0>;
+				cell-index = <0>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				phy-mode = "rgmii";
+				phy-map = <0x00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <0>;
+				tah-device = <&TAH0>;
+				tah-channel = <0>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+			};
+
+			EMAC1: ethernet@ef600f00 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4sync";
+				interrupt-parent = <&EMAC1>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
+						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
+				reg = <0xef600f00 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <1>;
+				mal-rx-channel = <8>;
+				cell-index = <1>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				phy-mode = "rgmii";
+				phy-map = <0x00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <1>;
+				tah-device = <&TAH1>;
+				tah-channel = <1>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+
+			EMAC2: ethernet@ef601100 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4sync";
+				interrupt-parent = <&EMAC2>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
+						 /*Wake*/   0x1 &UIC2 0x16 0x4>;
+				reg = <0xef601100 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <2>;
+				mal-rx-channel = <16>;
+				cell-index = <2>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				tx-fifo-size-gige = <16384>; /* emac2&3 only */
+				phy-mode = "rgmii";
+				phy-map = <0x00000000>;
+				rgmii-device = <&RGMII1>;
+				rgmii-channel = <0>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+
+			EMAC3: ethernet@ef601200 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4sync";
+				interrupt-parent = <&EMAC3>;
+				interrupts = <0x0 0x1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
+						 /*Wake*/   0x1 &UIC2 0x17 0x4>;
+				reg = <0xef601200 0x000000c4>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <3>;
+				mal-rx-channel = <24>;
+				cell-index = <3>;
+				max-frame-size = <9000>;
+				rx-fifo-size = <4096>;
+				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				tx-fifo-size-gige = <16384>; /* emac2&3 only */
+				phy-mode = "rgmii";
+				phy-map = <0x00000000>;
+				rgmii-device = <&RGMII1>;
+				rgmii-channel = <1>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+		};
+
+		PCIX0: pci@c0ec00000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
+			primary;
+			large-inbound-windows;
+			enable-msi-hole;
+			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
+			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
+			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
+			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
+			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
+				  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
+				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+			/* This drives busses 0 to 0x3f */
+			bus-range = <0x0 0x3f>;
+
+			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
+		};
+
+		PCIE0: pciex@d00000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <0x0>; /* port number */
+			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
+			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
+			dcr-reg = <0x100 0x020>;
+			sdr-base = <0x300>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
+				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+			/* This drives busses 40 to 0x7f */
+			bus-range = <0x40 0x7f>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <
+				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
+				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
+				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
+				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
+		};
+
+		PCIE1: pciex@d20000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <0x1>; /* port number */
+			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
+			       0x0000000c 0x08011000 0x00001000>;	/* Registers */
+			dcr-reg = <0x120 0x020>;
+			sdr-base = <0x340>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
+				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
+				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+			/* This drives busses 80 to 0xbf */
+			bus-range = <0x80 0xbf>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <
+				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
+				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
+				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
+				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
+		};
+	};
+};
diff --git a/arch/powerpc/include/asm/arch-ppc4xx/gpio.h b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
new file mode 100644
index 0000000..3d960c3
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
@@ -0,0 +1,7 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* This is empty for now as we don't support the generic GPIO interface */
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
new file mode 100644
index 0000000..559b42e
--- /dev/null
+++ b/arch/powerpc/include/asm/linkage.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* We don't need anything here at present */
diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h
index f41df0d..ea019aa 100644
--- a/arch/powerpc/include/asm/ppc460ex_gt.h
+++ b/arch/powerpc/include/asm/ppc460ex_gt.h
@@ -19,10 +19,12 @@
 /* Memory mapped registers */
 #define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
 
+#ifndef CONFIG_DM_SERIAL
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
+#endif
 
 #define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
 #define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 3057325..2098b9c 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -10,4 +10,28 @@
 config SYS_CONFIG_NAME
 	default "sandbox"
 
+config DM
+	default y
+
+config DM_GPIO
+	default y
+
+config DM_SERIAL
+	default y
+
+config DM_CROS_EC
+	default y
+
+config DM_SPI
+	default y
+
+config DM_SPI_FLASH
+	default y
+
+config DM_I2C
+	default y
+
+config DM_TEST
+	default y
+
 endmenu
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index fef11f3..35d24e4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -67,6 +67,21 @@
 
 endchoice
 
+config DM
+	default y
+
+config DM_GPIO
+	default y
+
+config DM_SERIAL
+	default y
+
+config SYS_MALLOC_F
+	default y
+
+config SYS_MALLOC_F_LEN
+	default 0x800
+
 config RAMBASE
 	hex
 	default 0x100000
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig
index 530a6ef..848e08f 100644
--- a/board/amcc/canyonlands/Kconfig
+++ b/board/amcc/canyonlands/Kconfig
@@ -9,4 +9,42 @@
 config SYS_CONFIG_NAME
 	default "canyonlands"
 
+choice BOARD_TYPE
+	prompt "Select which board to build for"
+
+config CANYONLANDS
+	bool "Glacier"
+	help
+	  Select this to build for the Canyonlands 460EX board.
+
+config GLACIER
+	bool "Glacier"
+	help
+	  Select this to build for the Glacier 460GT board.
+
+config ARCHES
+	bool "Arches"
+	help
+	  Select this to build for the Arches dual 460GT board.
+
+endchoice
+
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
+config DM
+	default y
+
+config DM_SERIAL
+	default y
+
+config SYS_MALLOC_F
+	bool
+	default y
+
+config SYS_MALLOC_F_LEN
+	hex
+	default 0x400
+
 endif
diff --git a/board/amcc/canyonlands/MAINTAINERS b/board/amcc/canyonlands/MAINTAINERS
index 52bf004..8be8a52 100644
--- a/board/amcc/canyonlands/MAINTAINERS
+++ b/board/amcc/canyonlands/MAINTAINERS
@@ -6,3 +6,4 @@
 F:	configs/arches_defconfig
 F:	configs/canyonlands_defconfig
 F:	configs/glacier_defconfig
+F:	configs/glacier_ramboot_defconfig
diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk
index 63b8973..5cc90d2 100644
--- a/board/amcc/canyonlands/config.mk
+++ b/board/amcc/canyonlands/config.mk
@@ -8,8 +8,6 @@
 # AMCC 460EX/460GT Evaluation Board (Canyonlands) board
 #
 
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
 endif
diff --git a/board/amcc/canyonlands/u-boot-ram.lds b/board/amcc/canyonlands/u-boot-ram.lds
new file mode 100644
index 0000000..1750c74
--- /dev/null
+++ b/board/amcc/canyonlands/u-boot-ram.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text      :
+  {
+    _image_copy_start = .;
+    arch/powerpc/cpu/ppc4xx/start.o	(.text*)
+    board/amcc/canyonlands/init.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : {
+	*(.data.init)
+	. = ALIGN(256);
+	LONG(0) LONG(0)		/* Extend u-boot.bin to here */
+  }
+  __init_end = .;
+  _end = .;
+  _image_binary_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig
index 683efde..aadbfbc 100644
--- a/board/compulab/cm_t335/Kconfig
+++ b/board/compulab/cm_t335/Kconfig
@@ -12,4 +12,13 @@
 config SYS_CONFIG_NAME
 	default "cm_t335"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
 endif
diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig
index 6f94612..3099a9e 100644
--- a/board/gumstix/pepper/Kconfig
+++ b/board/gumstix/pepper/Kconfig
@@ -12,4 +12,13 @@
 config SYS_CONFIG_NAME
 	default "pepper"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
 endif
diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig
index e989e4b..2fe2ef1 100644
--- a/board/isee/igep0033/Kconfig
+++ b/board/isee/igep0033/Kconfig
@@ -12,4 +12,13 @@
 config SYS_CONFIG_NAME
 	default "am335x_igep0033"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
 endif
diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig
index 2cc0d88..65094cf 100644
--- a/board/phytec/pcm051/Kconfig
+++ b/board/phytec/pcm051/Kconfig
@@ -12,4 +12,13 @@
 config SYS_CONFIG_NAME
 	default "pcm051"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
 endif
diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig
new file mode 100644
index 0000000..07aee0e
--- /dev/null
+++ b/board/renesas/silk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SILK
+
+config SYS_BOARD
+	default "silk"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "silk"
+
+endif
diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS
new file mode 100644
index 0000000..b566ccf
--- /dev/null
+++ b/board/renesas/silk/MAINTAINERS
@@ -0,0 +1,6 @@
+SILK BOARD
+M:	Cogent Embedded, Inc. <source@cogentembedded.com>
+S:	Maintained
+F:	board/renesas/silk/
+F:	include/configs/silk.h
+F:	configs/silk_defconfig
diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile
new file mode 100644
index 0000000..e6eea61
--- /dev/null
+++ b/board/renesas/silk/Makefile
@@ -0,0 +1,10 @@
+#
+# board/renesas/silk/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+# Copyright (C) 2015 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= silk.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c
new file mode 100644
index 0000000..4f6e46c
--- /dev/null
+++ b/board/renesas/silk/qos.c
@@ -0,0 +1,951 @@
+/*
+ * board/renesas/silk/qos.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.11 */
+
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x1F0D0B0A, &s3c->s3crorr);
+	writel(0x1F0D0B09, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80928092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x0000202A, &qos_addr->dbtmval2);
+		writel(0x00001FBD, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x00002043, &qos_addr->dbtmval2);
+		writel(0x00002030, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002031, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20000800, CCI_400_MAXOT_1);
+	writel(0x20000800, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000E, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/silk/qos.h b/board/renesas/silk/qos.h
new file mode 100644
index 0000000..75a20bb
--- /dev/null
+++ b/board/renesas/silk/qos.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
new file mode 100644
index 0000000..dfd9a9d
--- /dev/null
+++ b/board/renesas/silk/silk.c
@@ -0,0 +1,163 @@
+/*
+ * board/renesas/silk/silk.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS */
+	qos_init();
+}
+
+#define TMU0_MSTP125	(1 << 25)
+#define SCIF2_MSTP719	(1 << 19)
+#define ETHER_MSTP813	(1 << 13)
+#define IIC1_MSTP323	(1 << 23)
+#define MMC0_MSTP315	(1 << 15)
+
+int board_early_init_f(void)
+{
+	/* TMU */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/* SCIF2 */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+	/* ETHER */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+	/* IIC1 / sh-i2c ch1 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
+
+#ifdef CONFIG_SH_MMCIF
+	/* MMC */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7794_pinmux_init();
+
+	/* Ether Enable */
+	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+	gpio_request(GPIO_FN_ETH_RXD0, NULL);
+	gpio_request(GPIO_FN_ETH_RXD1, NULL);
+	gpio_request(GPIO_FN_ETH_LINK, NULL);
+	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+	gpio_request(GPIO_FN_ETH_MDIO, NULL);
+	gpio_request(GPIO_FN_ETH_TXD1, NULL);
+	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+	gpio_request(GPIO_FN_ETH_TXD0, NULL);
+	gpio_request(GPIO_FN_ETH_MDC, NULL);
+	gpio_request(GPIO_FN_IRQ8, NULL);
+
+	/* PHY reset */
+	gpio_request(GPIO_GP_1_24, NULL);
+	gpio_direction_output(GPIO_GP_1_24, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_1_24, 1);
+	udelay(1);
+
+	return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+	int ret = -ENODEV;
+	u32 val;
+	unsigned char enetaddr[6];
+
+	ret = sh_eth_initialize(bis);
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		return ret;
+
+	/* Set Mac address */
+	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+		enetaddr[2] << 8 | enetaddr[3];
+	writel(val, CXR24);
+
+	val = enetaddr[4] << 8 | enetaddr[5];
+	writel(val, CXR25);
+
+	return ret;
+#else
+	return 0;
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+	/* MMC0 */
+	gpio_request(GPIO_GP_4_31, NULL);
+	gpio_set_value(GPIO_GP_4_31, 1);
+
+	ret = mmcif_mmc_init();
+#endif
+	return ret;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+	u8 val;
+
+	i2c_set_bus_num(1); /* PowerIC connected to ch1 */
+	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	val |= 0x02;
+	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig
index cbbf5a9..2c5d3fc 100644
--- a/board/samsung/goni/Kconfig
+++ b/board/samsung/goni/Kconfig
@@ -12,4 +12,13 @@
 config SYS_CONFIG_NAME
 	default "s5p_goni"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
 endif
diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig
index a9d62ff..576abae 100644
--- a/board/samsung/smdk5420/Kconfig
+++ b/board/samsung/smdk5420/Kconfig
@@ -22,6 +22,9 @@
 config SYS_CONFIG_NAME
 	default "peach-pi"
 
+config DM_CROS_EC
+	default y
+
 endif
 
 if TARGET_PEACH_PIT
@@ -35,6 +38,9 @@
 config SYS_CONFIG_NAME
 	default "peach-pit"
 
+config DM_CROS_EC
+	default y
+
 endif
 
 if TARGET_SMDK5420
diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig
index d2157b4..996fe3c 100644
--- a/board/samsung/smdkc100/Kconfig
+++ b/board/samsung/smdkc100/Kconfig
@@ -12,4 +12,13 @@
 config SYS_CONFIG_NAME
 	default "smdkc100"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
 endif
diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig
index f2e1098..6ecda80 100644
--- a/board/silica/pengwyn/Kconfig
+++ b/board/silica/pengwyn/Kconfig
@@ -12,4 +12,13 @@
 config SYS_CONFIG_NAME
 	default "pengwyn"
 
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if !SPL_BUILD
+
+config DM_SERIAL
+	default y if !SPL_BUILD
+
 endif
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 1ddbb2c..a20e0c1 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -37,4 +37,20 @@
 	  booted via NOR.  In this case we will enable certain pinmux early
 	  as the ROM only partially sets up pinmux.  We also default to using
 	  NOR for environment.
+
+config DM
+	default y if !SPL_BUILD
+
+config DM_GPIO
+	default y if DM && !SPL_BUILD
+
+config DM_SERIAL
+	default y if DM && !SPL_BUILD
+
+config SYS_MALLOC_F
+	default y if DM && !SPL_BUILD
+
+config SYS_MALLOC_F_LEN
+	default 0x400 if DM && !SPL_BUILD
+
 endif
diff --git a/common/Kconfig b/common/Kconfig
index fd84fa0..2ca002d 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -153,6 +153,29 @@
 
 menu "Device access commands"
 
+config CMD_DM
+	bool "dm - Access to driver model information"
+	depends on DM
+	default y
+	help
+	  Provides access to driver model data structures and information,
+	  such as a list of devices, list of uclasses and the state of each
+	  device (e.g. activated). This is not required for operation, but
+	  can be useful to see the state of driver model for debugging or
+	  interest.
+
+config CMD_DEMO
+	bool "demo - Demonstration commands for driver model"
+	depends on DM
+	help
+	  Provides a 'demo' command which can be used to play around with
+	  driver model. To use this properly you will need to enable one or
+	  both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE).
+	  Otherwise you will always get an empty list of devices. The demo
+	  devices are defined in the sandbox device tree, so the easiest
+	  option is to use sandbox and pass the -d point to sandbox's
+	  u-boot.dtb file.
+
 config CMD_LOADB
 	bool "loadb"
 	help
diff --git a/common/board_f.c b/common/board_f.c
index bdad36b..2c10215 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1075,4 +1075,22 @@
 	/* NOTREACHED - board_init_r() does not return */
 	hang();
 }
+#else
+ulong board_init_f_mem(ulong top)
+{
+	/* Leave space for the stack we are running with now */
+	top -= 0x40;
+
+	top -= sizeof(struct global_data);
+	top = ALIGN(top, 16);
+	gd = (struct global_data *)top;
+	memset((void *)gd, '\0', sizeof(*gd));
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	top -= CONFIG_SYS_MALLOC_F_LEN;
+	gd->malloc_base = top;
+#endif
+
+	return top;
+}
 #endif /* CONFIG_X86 */
diff --git a/common/cmd_demo.c b/common/cmd_demo.c
index bcb34d9..8a10bdf 100644
--- a/common/cmd_demo.c
+++ b/common/cmd_demo.c
@@ -97,7 +97,9 @@
 				ARRAY_SIZE(demo_commands));
 	argc -= 2;
 	argv += 2;
-	if (!demo_cmd || argc > demo_cmd->maxargs)
+
+	if ((!demo_cmd || argc > demo_cmd->maxargs) ||
+	    ((demo_cmd->name[0] != 'l') && (argc < 1)))
 		return CMD_RET_USAGE;
 
 	if (argc) {
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 7c3ad00..fe8f77a 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -1730,7 +1730,7 @@
 #endif
 	if (argc == 1) {
 #ifdef CONFIG_DM_I2C
-		speed = i2c_get_bus_speed(bus);
+		speed = dm_i2c_get_bus_speed(bus);
 #else
 		speed = i2c_get_bus_speed();
 #endif
@@ -1740,7 +1740,7 @@
 		speed = simple_strtoul(argv[1], NULL, 10);
 		printf("Setting bus speed to %d Hz\n", speed);
 #ifdef CONFIG_DM_I2C
-		ret = i2c_set_bus_speed(bus, speed);
+		ret = dm_i2c_set_bus_speed(bus, speed);
 #else
 		ret = i2c_set_bus_speed(speed);
 #endif
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index afdacff..64ae036 100644
--- a/common/malloc_simple.c
+++ b/common/malloc_simple.c
@@ -19,7 +19,7 @@
 
 	new_ptr = gd->malloc_ptr + bytes;
 	if (new_ptr > gd->malloc_limit)
-		panic("Out of pre-reloc memory");
+		return NULL;
 	ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
 	gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
 	return ptr;
diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
index 3b6dfa6..1e749cd 100644
--- a/configs/Linksprite_pcDuino3_fdt_defconfig
+++ b/configs/Linksprite_pcDuino3_fdt_defconfig
@@ -2,6 +2,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
 CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
 CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 CONFIG_OF_CONTROL=y
 CONFIG_OF_SEPARATE=y
@@ -11,3 +13,5 @@
 +S:CONFIG_DRAM_CLK=480
 +S:CONFIG_DRAM_ZQ=122
 +S:CONFIG_DRAM_EMR1=4
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index 23f0a32..f3544b5 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_IGEP0033=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index cf9d8c7..33b63c7 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_AM3517_CRANE=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 2336f1e..7558b89 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_AM3517_EVM=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index 18d0a14..30c6932 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -1,4 +1,7 @@
-CONFIG_SYS_EXTRA_OPTIONS="ARCHES"
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CANYONLANDS=y
+CONFIG_ARCHES=y
+CONFIG_DEFAULT_DEVICE_TREE="arches"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
new file mode 100644
index 0000000..c63dd4a
--- /dev/null
+++ b/configs/axs103_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=50000000
+CONFIG_ARC=y
+CONFIG_ISA_ARCV2=y
+CONFIG_TARGET_AXS101=y
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index 09b9ab9..44d4fbd 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -1,4 +1,7 @@
-CONFIG_SYS_EXTRA_OPTIONS="CANYONLANDS"
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CANYONLANDS=y
+CONFIG_CANYONLANDS=y
+CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 3c0d64f..631698c 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -2,3 +2,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_CM_FX6=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 5ff4f9c..5c1d3cf 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_CM_T335=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 4000d2c..6eb37c0 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_CM_T3517=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 2bb616f..84a6fb0 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_CM_T35=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index 578ae74..05a8700 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_DEVKIT8000=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
diff --git a/configs/dig297_defconfig b/configs/dig297_defconfig
index 95bc353..0d18290 100644
--- a/configs/dig297_defconfig
+++ b/configs/dig297_defconfig
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_DIG297=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index e45bdad..e07df8b 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_ECO5PK=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 2a66bfb..d318f82 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -1,4 +1,7 @@
-CONFIG_SYS_EXTRA_OPTIONS="GLACIER"
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CANYONLANDS=y
+CONFIG_GLACIER=y
+CONFIG_DEFAULT_DEVICE_TREE="glacier"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
new file mode 100644
index 0000000..f8363b2
--- /dev/null
+++ b/configs/glacier_ramboot_defconfig
@@ -0,0 +1,8 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
+CONFIG_PPC=y
+CONFIG_4xx=y
+CONFIG_TARGET_CANYONLANDS=y
+CONFIG_GLACIER=y
+CONFIG_DEFAULT_DEVICE_TREE="glacier"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 4cddbdd..5b1a4c4 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -2,3 +2,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_GW_VENTANA=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index c2031f8..6566d40 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_MCX=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index a0678bb..a4747c6 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_MT_VENTOUX=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index b649935..47f3f87 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -1,3 +1,7 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 7f6cdff..6adfd55 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SABRESD=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 7d86700..ab72942 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -1,3 +1,7 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index dfa9c2e..50b75ae 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
 CONFIG_ARM=y
 CONFIG_TARGET_NITROGEN6X=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 67c1b77..112918b 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -1,3 +1,7 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SABRESD=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 12e7844..67079ba 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -2,4 +2,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_MX6SABRESD=y
-
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index f23d48f..72e0f10 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index e03f586..1bb7664 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -1,3 +1,8 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index a3e4c2c..5a2d20b 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -3,3 +3,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index c749aa7..3bb1911 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_OMAP3_EVM=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig
index e89bb82..4e1471b 100644
--- a/configs/omap3_evm_quick_mmc_defconfig
+++ b/configs/omap3_evm_quick_mmc_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig
index e70fddd..f98672f 100644
--- a/configs/omap3_evm_quick_nand_defconfig
+++ b/configs/omap3_evm_quick_nand_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 50bffa9..1a8b1b4 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -3,3 +3,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_TAO3530=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 5f2c063..790ccba 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig
index fb6edc2..b75f513 100644
--- a/configs/omap3_mvblx_defconfig
+++ b/configs/omap3_mvblx_defconfig
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_MVBLX=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index bf28537..dd0f17c 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_PANDORA=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/omap3_sdp3430_defconfig b/configs/omap3_sdp3430_defconfig
index 1172c2a..b3a8745 100644
--- a/configs/omap3_sdp3430_defconfig
+++ b/configs/omap3_sdp3430_defconfig
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_SDP3430=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 8b27682..baa2b23 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -2,3 +2,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="REV1"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_PCM051=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 27ad6ff..b5c62a6 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -2,3 +2,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="REV3"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_PCM051=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 1b9aa68..cbdd404 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_PENGWYN=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index 22c7bb4..14266ef 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_PEPPER=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 9379cf0..98d3199 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -1,2 +1,4 @@
 CONFIG_ARM=y
 CONFIG_TARGET_RPI=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 618e590..33e6fb8 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -2,3 +2,5 @@
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_TARGET_S5P_GONI=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 660063e..0bf5ea3 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -5,3 +5,5 @@
 CONFIG_FIT_SIGNATURE=y
 CONFIG_DM=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
new file mode 100644
index 0000000..515ee33
--- /dev/null
+++ b/configs/silk_defconfig
@@ -0,0 +1,3 @@
+CONFIG_ARM=y
+CONFIG_RMOBILE=y
+CONFIG_TARGET_SILK=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 041030f..e933a32 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -2,3 +2,5 @@
 CONFIG_TARGET_SMDKC100=y
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 7055e2a..97c49f3 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -1,3 +1,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
 CONFIG_ARM=y
 CONFIG_TARGET_SNAPPER9260=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 2faae15..d5f1d9f 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -1,3 +1,8 @@
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
 CONFIG_ARM=y
 CONFIG_TARGET_SNAPPER9260=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 0f3896d..888bbb6 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -3,3 +3,6 @@
 +S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index a05e991..1c9ba88 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -1,3 +1,7 @@
 CONFIG_SYS_EXTRA_OPTIONS="stv0991"
 CONFIG_ARM=y
 CONFIG_TARGET_STV0991=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index a511389..39ed872 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_TAO3530=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index 7ea5e02..3efe829 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_TRICORDER=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index f6e1c46..8f999ff 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -3,3 +3,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_TRICORDER=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 9023736..d21a551 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -2,3 +2,6 @@
 +S:CONFIG_ARM=y
 +S:CONFIG_OMAP34XX=y
 +S:CONFIG_TARGET_TWISTER=y
+CONFIG_DM=n
+CONFIG_DM_SERIAL=n
+CONFIG_DM_GPIO=n
diff --git a/doc/driver-model/spi-howto.txt b/doc/driver-model/spi-howto.txt
index 5bc29ad..ee4abf4 100644
--- a/doc/driver-model/spi-howto.txt
+++ b/doc/driver-model/spi-howto.txt
@@ -40,8 +40,8 @@
 
 Add these to your board config:
 
-#define CONFIG_DM_SPI
-#define CONFIG_DM_SPI_FLASH
+CONFIG_DM_SPI
+CONFIG_DM_SPI_FLASH
 
 
 2. Add the skeleton
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 128736d..dcce532 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -2,6 +2,8 @@
 
 source "drivers/core/Kconfig"
 
+source "drivers/demo/Kconfig"
+
 source "drivers/pci/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
@@ -48,4 +50,6 @@
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/thermal/Kconfig"
+
 endmenu
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index d2799dc..f0d6110 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -2,5 +2,51 @@
 	bool "Enable Driver Model"
 	depends on !SPL_BUILD
 	help
-	  This config option enables Driver Model.
-	  To use legacy drivers, say N.
+	  This config option enables Driver Model. This brings in the core
+	  support, including scanning of platform data on start-up. If
+	  CONFIG_OF_CONTROL is enabled, the device tree will be scanned also
+	  when available.
+
+config SPL_DM
+	bool "Enable Driver Model for SPL"
+	depends on DM && SPL
+	help
+	  Enable driver model in SPL. You will need to provide a
+	  suitable malloc() implementation. If you are not using the
+	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+	  consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
+	  must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+	  In most cases driver model will only allocate a few uclasses
+	  and devices in SPL, so 1KB should be enable. See
+	  CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it.
+
+config DM_WARN
+	bool "Enable warnings in driver model"
+	help
+	  The dm_warn() function can use up quite a bit of space for its
+	  strings. By default this is disabled for SPL builds to save space.
+	  This will cause dm_warn() to be compiled out - it will do nothing
+	  when called.
+	depends on DM
+	default y if !SPL_BUILD
+	default n if SPL_BUILD
+
+config DM_DEVICE_REMOVE
+	bool "Support device removal"
+	help
+	  We can save some code space by dropping support for removing a
+	  device. This is not normally required in SPL, so by default this
+	  option is disabled for SPL.
+	depends on DM
+	default y if !SPL_BUILD
+	default n if SPL_BUILD
+
+config DM_STDIO
+	bool "Support stdio registration"
+	help
+	  Normally serial drivers register with stdio so that they can be used
+	  as normal output devices. In SPL we don't normally use stdio, so
+	  we can omit this feature.
+	depends on DM
+	default y if !SPL_BUILD
+	default n if SPL_BUILD
diff --git a/drivers/core/device.c b/drivers/core/device.c
index b73d3b8..73c3e07 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -449,3 +449,15 @@
 {
 	return dev->uclass->uc_drv->id;
 }
+
+#ifdef CONFIG_OF_CONTROL
+fdt_addr_t dev_get_addr(struct udevice *dev)
+{
+	return fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+}
+#else
+fdt_addr_t dev_get_addr(struct udevice *dev)
+{
+	return FDT_ADDR_T_NONE;
+}
+#endif
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 73e3c72..9b5c6bb 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -37,6 +37,65 @@
 	return gd->dm_root;
 }
 
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+void fix_drivers(void)
+{
+	struct driver *drv =
+		ll_entry_start(struct driver, driver);
+	const int n_ents = ll_entry_count(struct driver, driver);
+	struct driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (entry->of_match)
+			entry->of_match = (const struct udevice_id *)
+				((u32)entry->of_match + gd->reloc_off);
+		if (entry->bind)
+			entry->bind += gd->reloc_off;
+		if (entry->probe)
+			entry->probe += gd->reloc_off;
+		if (entry->remove)
+			entry->remove += gd->reloc_off;
+		if (entry->unbind)
+			entry->unbind += gd->reloc_off;
+		if (entry->ofdata_to_platdata)
+			entry->ofdata_to_platdata += gd->reloc_off;
+		if (entry->child_pre_probe)
+			entry->child_pre_probe += gd->reloc_off;
+		if (entry->child_post_remove)
+			entry->child_post_remove += gd->reloc_off;
+		/* OPS are fixed in every uclass post_probe function */
+		if (entry->ops)
+			entry->ops += gd->reloc_off;
+	}
+}
+
+void fix_uclass(void)
+{
+	struct uclass_driver *uclass =
+		ll_entry_start(struct uclass_driver, uclass);
+	const int n_ents = ll_entry_count(struct uclass_driver, uclass);
+	struct uclass_driver *entry;
+
+	for (entry = uclass; entry != uclass + n_ents; entry++) {
+		if (entry->post_bind)
+			entry->post_bind += gd->reloc_off;
+		if (entry->pre_unbind)
+			entry->pre_unbind += gd->reloc_off;
+		if (entry->post_probe)
+			entry->post_probe += gd->reloc_off;
+		if (entry->pre_remove)
+			entry->pre_remove += gd->reloc_off;
+		if (entry->init)
+			entry->init += gd->reloc_off;
+		if (entry->destroy)
+			entry->destroy += gd->reloc_off;
+		/* FIXME maybe also need to fix these ops */
+		if (entry->ops)
+			entry->ops += gd->reloc_off;
+	}
+}
+#endif
+
 int dm_init(void)
 {
 	int ret;
@@ -47,6 +106,11 @@
 	}
 	INIT_LIST_HEAD(&DM_UCLASS_ROOT_NON_CONST);
 
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	fix_drivers();
+	fix_uclass();
+#endif
+
 	ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST);
 	if (ret)
 		return ret;
diff --git a/drivers/demo/Kconfig b/drivers/demo/Kconfig
new file mode 100644
index 0000000..7a8ce18
--- /dev/null
+++ b/drivers/demo/Kconfig
@@ -0,0 +1,26 @@
+config DM_DEMO
+	bool "Enable demo uclass support"
+	depends on DM
+	help
+	  This uclass allows you to play around with driver model. It provides
+	  an interface to a couple of demo devices. You can access it using
+	  the 'demo' command or by calling the uclass functions from your
+	  own code.
+
+config DM_DEMO_SIMPLE
+	bool "Enable simple demo device for driver model"
+	depends on DM_DEMO
+	help
+	  This device allows you to play around with driver model. It prints
+	  a message when the 'demo hello' command is executed which targets
+	  this device. It can be used to help understand how driver model
+	  works.
+
+config DM_DEMO_SHAPE
+	bool "Enable shape demo device for driver model"
+	depends on DM_DEMO
+	help
+	  This device allows you to play around with driver model. It prints
+	  a shape when the 'demo hello' command is executed which targets
+	  this device. It can be used to help understand how driver model
+	  works.
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d21302f..b609e73 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -2,5 +2,8 @@
 	bool "Enable Driver Model for GPIO drivers"
 	depends on DM
 	help
-	  If you want to use driver model for GPIO drivers, say Y.
-	  To use legacy GPIO drivers, say N.
+	  Enable driver model for GPIO access. The standard GPIO
+	  interface (gpio_get_value(), etc.) is then implemented by
+	  the GPIO uclass. Drivers provide methods to query the
+	  particular GPIOs that they provide. The uclass interface
+	  is defined in include/asm-generic/gpio.h.
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 6129c02..22fbd63 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -451,7 +451,7 @@
 /* set GPIO pin 'gpio' as an input */
 static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
-	struct at91_port_priv *port = dev_get_platdata(dev);
+	struct at91_port_priv *port = dev_get_priv(dev);
 
 	at91_set_port_input(port->regs, offset, 0);
 
@@ -462,7 +462,7 @@
 static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
 				       int value)
 {
-	struct at91_port_priv *port = dev_get_platdata(dev);
+	struct at91_port_priv *port = dev_get_priv(dev);
 
 	at91_set_port_output(port->regs, offset, value);
 
@@ -472,7 +472,7 @@
 /* read GPIO IN value of pin 'gpio' */
 static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
 {
-	struct at91_port_priv *port = dev_get_platdata(dev);
+	struct at91_port_priv *port = dev_get_priv(dev);
 
 	return at91_get_port_value(port->regs, offset);
 }
@@ -481,7 +481,7 @@
 static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
 			       int value)
 {
-	struct at91_port_priv *port = dev_get_platdata(dev);
+	struct at91_port_priv *port = dev_get_priv(dev);
 
 	at91_set_port_value(port->regs, offset, value);
 
@@ -490,7 +490,7 @@
 
 static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
 {
-	struct at91_port_priv *port = dev_get_platdata(dev);
+	struct at91_port_priv *port = dev_get_priv(dev);
 
 	/* GPIOF_FUNC is not implemented yet */
 	if (at91_get_port_output(port->regs, offset))
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 8bb9e39..815407b 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -23,6 +23,7 @@
 #define GPIO_PER_BANK			32
 
 struct mxc_gpio_plat {
+	int bank_index;
 	struct gpio_regs *regs;
 };
 
@@ -150,6 +151,9 @@
 #endif
 
 #ifdef CONFIG_DM_GPIO
+#include <fdtdec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
 static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
 {
 	u32 val;
@@ -258,23 +262,6 @@
 	.get_function		= mxc_gpio_get_function,
 };
 
-static const struct mxc_gpio_plat mxc_plat[] = {
-	{ (struct gpio_regs *)GPIO1_BASE_ADDR },
-	{ (struct gpio_regs *)GPIO2_BASE_ADDR },
-	{ (struct gpio_regs *)GPIO3_BASE_ADDR },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-		defined(CONFIG_MX53) || defined(CONFIG_MX6)
-	{ (struct gpio_regs *)GPIO4_BASE_ADDR },
-#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
-	{ (struct gpio_regs *)GPIO5_BASE_ADDR },
-	{ (struct gpio_regs *)GPIO6_BASE_ADDR },
-#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
-	{ (struct gpio_regs *)GPIO7_BASE_ADDR },
-#endif
-};
-
 static int mxc_gpio_probe(struct udevice *dev)
 {
 	struct mxc_bank_info *bank = dev_get_priv(dev);
@@ -283,7 +270,7 @@
 	int banknum;
 	char name[18], *str;
 
-	banknum = plat - mxc_plat;
+	banknum = plat->bank_index;
 	sprintf(name, "GPIO%d_", banknum + 1);
 	str = strdup(name);
 	if (!str)
@@ -295,14 +282,74 @@
 	return 0;
 }
 
+static int mxc_gpio_bind(struct udevice *dev)
+{
+	struct mxc_gpio_plat *plat = dev->platdata;
+	fdt_addr_t addr;
+
+	/*
+	 * If platdata already exsits, directly return.
+	 * Actually only when DT is not supported, platdata
+	 * is statically initialized in U_BOOT_DEVICES.Here
+	 * will return.
+	 */
+	if (plat)
+		return 0;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	/*
+	 * TODO:
+	 * When every board is converted to driver model and DT is supported,
+	 * this can be done by auto-alloc feature, but not using calloc
+	 * to alloc memory for platdata.
+	 */
+	plat = calloc(1, sizeof(*plat));
+	if (!plat)
+		return -ENOMEM;
+
+	plat->regs = (struct gpio_regs *)addr;
+	plat->bank_index = dev->req_seq;
+	dev->platdata = plat;
+
+	return 0;
+}
+
+static const struct udevice_id mxc_gpio_ids[] = {
+	{ .compatible = "fsl,imx35-gpio" },
+	{ }
+};
+
 U_BOOT_DRIVER(gpio_mxc) = {
 	.name	= "gpio_mxc",
 	.id	= UCLASS_GPIO,
 	.ops	= &gpio_mxc_ops,
 	.probe	= mxc_gpio_probe,
 	.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+	.of_match = mxc_gpio_ids,
+	.bind	= mxc_gpio_bind,
 };
 
+#ifndef CONFIG_OF_CONTROL
+static const struct mxc_gpio_plat mxc_plat[] = {
+	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
+	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
+	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+		defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
+	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+	{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
+#endif
+};
+
 U_BOOT_DEVICES(mxc_gpios) = {
 	{ "gpio_mxc", &mxc_plat[0] },
 	{ "gpio_mxc", &mxc_plat[1] },
@@ -320,3 +367,4 @@
 #endif
 };
 #endif
+#endif
diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index f3a7ccb..19fc451 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -291,7 +291,7 @@
 	struct gpio_bank *bank = dev_get_priv(dev);
 
 	/* GPIOF_FUNC is not implemented yet */
-	if (_get_gpio_direction(bank->base, offset) == OMAP_GPIO_DIR_OUT)
+	if (_get_gpio_direction(bank, offset) == OMAP_GPIO_DIR_OUT)
 		return GPIOF_OUTPUT;
 	else
 		return GPIOF_INPUT;
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 202ea5d..2cc776c 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -2,8 +2,16 @@
 	bool "Enable Driver Model for I2C drivers"
 	depends on DM
 	help
-	  If you want to use driver model for I2C drivers, say Y.
-	  To use legacy I2C drivers, say N.
+	  Enable driver model for I2C. This SPI flash interface
+	  (spi_flash_probe(), spi_flash_write(), etc.) is then
+	  implemented by the SPI flash uclass. There is one standard
+	  SPI flash driver which knows how to probe most chips
+	  supported by U-Boot. The uclass interface is defined in
+	  include/spi_flash.h, but is currently fully compatible
+	  with the old interface to avoid confusion and duplication
+	  during the transition parent. SPI and SPI flash must be
+	  enabled together (it is not possible to use driver model
+	  for one and not the other).
 
 config SYS_I2C_UNIPHIER
 	bool "UniPhier I2C driver"
diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c
index 20495b1..c58f14a 100644
--- a/drivers/i2c/adi_i2c.c
+++ b/drivers/i2c/adi_i2c.c
@@ -63,7 +63,7 @@
 #endif
 
 /* All transfers are described by this data structure */
-struct i2c_msg {
+struct adi_i2c_msg {
 	u8 flags;
 #define I2C_M_COMBO		0x4
 #define I2C_M_STOP		0x2
@@ -81,7 +81,7 @@
  * wait_for_completion - manage the actual i2c transfer
  *	@msg: the i2c msg
  */
-static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg)
+static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
 {
 	u16 int_stat, ctl;
 	ulong timebase = get_timer(0);
@@ -151,7 +151,7 @@
 		(addr >>  8),
 		(addr >> 16),
 	};
-	struct i2c_msg msg = {
+	struct adi_i2c_msg msg = {
 		.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
 		.buf   = buffer,
 		.len   = len,
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index eafa457..a6991bf 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -325,7 +325,7 @@
 	return ret;
 }
 
-int i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 {
 	struct dm_i2c_ops *ops = i2c_get_ops(bus);
 	struct dm_i2c_bus *i2c = bus->uclass_priv;
@@ -346,12 +346,7 @@
 	return 0;
 }
 
-/*
- * i2c_get_bus_speed:
- *
- *  Returns speed of selected I2C bus in Hz
- */
-int i2c_get_bus_speed(struct udevice *bus)
+int dm_i2c_get_bus_speed(struct udevice *bus)
 {
 	struct dm_i2c_ops *ops = i2c_get_ops(bus);
 	struct dm_i2c_bus *i2c = bus->uclass_priv;
@@ -440,7 +435,7 @@
 	i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 				     "clock-frequency", 100000);
 
-	return i2c_set_bus_speed(dev, i2c->speed_hz);
+	return dm_i2c_set_bus_speed(dev, i2c->speed_hz);
 }
 
 static int i2c_post_bind(struct udevice *dev)
diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c
index 5eab338..9af496b 100644
--- a/drivers/i2c/kona_i2c.c
+++ b/drivers/i2c/kona_i2c.c
@@ -156,7 +156,7 @@
 #define I2C_M_RD	0x0001	/* read data */
 #define I2C_M_NOSTART	0x4000	/* no restart between msgs */
 
-struct i2c_msg {
+struct kona_i2c_msg {
 	uint16_t addr;
 	uint16_t flags;
 	uint16_t len;
@@ -297,7 +297,7 @@
 
 /* Read any amount of data using the RX FIFO from the i2c bus */
 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
-				  struct i2c_msg *msg)
+				  struct kona_i2c_msg *msg)
 {
 	unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
 	unsigned int last_byte_nak = 0;
@@ -392,7 +392,7 @@
 
 /* Write any amount of data using TX FIFO to the i2c bus */
 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
-				   struct i2c_msg *msg)
+				   struct kona_i2c_msg *msg)
 {
 	unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
 	unsigned int bytes_written = 0;
@@ -418,7 +418,7 @@
 
 /* Send i2c address */
 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
-				struct i2c_msg *msg)
+				struct kona_i2c_msg *msg)
 {
 	unsigned char addr;
 
@@ -480,9 +480,9 @@
 
 /* Master transfer function */
 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
-			     struct i2c_msg msgs[], int num)
+			     struct kona_i2c_msg msgs[], int num)
 {
-	struct i2c_msg *pmsg;
+	struct kona_i2c_msg *pmsg;
 	int rc = 0;
 	int i;
 
@@ -635,7 +635,7 @@
 			 int alen, uchar *buffer, int len)
 {
 	/* msg[0] writes the addr, msg[1] reads the data */
-	struct i2c_msg msg[2];
+	struct kona_i2c_msg msg[2];
 	unsigned char msgbuf0[64];
 	struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 
@@ -663,7 +663,7 @@
 static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 			  int alen, uchar *buffer, int len)
 {
-	struct i2c_msg msg[1];
+	struct kona_i2c_msg msg[1];
 	unsigned char msgbuf0[64];
 	unsigned int i;
 	struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index dac3463..e65cce0 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -31,7 +31,7 @@
 #endif
 
 /* All transfers are described by this data structure */
-struct i2c_msg {
+struct mv_i2c_msg {
 	u8 condition;
 	u8 acknack;
 	u8 direction;
@@ -157,7 +157,7 @@
  *          -5: illegal parameters
  *          -6: bus is busy and couldn't be aquired
  */
-int i2c_transfer(struct i2c_msg *msg)
+int i2c_transfer(struct mv_i2c_msg *msg)
 {
 	int ret;
 
@@ -286,7 +286,7 @@
  */
 int i2c_probe(uchar chip)
 {
-	struct i2c_msg msg;
+	struct mv_i2c_msg msg;
 
 	i2c_reset();
 
@@ -322,7 +322,7 @@
  */
 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
-	struct i2c_msg msg;
+	struct mv_i2c_msg msg;
 	u8 addr_bytes[3]; /* lowest...highest byte of data address */
 
 	PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
@@ -410,7 +410,7 @@
  */
 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
-	struct i2c_msg msg;
+	struct mv_i2c_msg msg;
 	u8 addr_bytes[3]; /* lowest...highest byte of data address */
 
 	PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 0dd1abc..b4ee33f 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -112,9 +112,9 @@
 #define I2C_START_STOP	0x20	/* START / STOP */
 #define I2C_TXRX_ENA	0x10	/* I2C Tx/Rx enable */
 
-#define I2C_TIMEOUT_MS 1000		/* 1 second */
+#define I2C_TIMEOUT_MS 10		/* 10 ms */
 
-#define	HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */
+#define	HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
 
 
 /* To support VCMA9 boards and other who dont define max_i2c_num */
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index e69de29..813d1c2 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -0,0 +1,9 @@
+config DM_CROS_EC
+	bool "Enable Driver Model for Chrome OS EC"
+	depends on DM
+	help
+	  Enable driver model for the Chrome OS EC interface. This
+	  allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
+	  but otherwise makes few changes. Since cros_ec also supports
+	  I2C and LPC (which don't support driver model yet), a full
+	  conversion is not yet possible.
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 415ab4e..59278d1 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -1 +1,3 @@
 source "drivers/mtd/nand/Kconfig"
+
+source "drivers/mtd/spi/Kconfig"
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
new file mode 100644
index 0000000..2dc46b4
--- /dev/null
+++ b/drivers/mtd/spi/Kconfig
@@ -0,0 +1,14 @@
+config DM_SPI_FLASH
+	bool "Enable Driver Model for SPI flash"
+	depends on DM && SPI
+	help
+	  Enable driver model for SPI flash. This SPI flash interface
+	  (spi_flash_probe(), spi_flash_write(), etc.) is then
+	  implemented by the SPI flash uclass. There is one standard
+	  SPI flash driver which knows how to probe most chips
+	  supported by U-Boot. The uclass interface is defined in
+	  include/spi_flash.h, but is currently fully compatible
+	  with the old interface to avoid confusion and duplication
+	  during the transition parent. SPI and SPI flash must be
+	  enabled together (it is not possible to use driver model
+	  for one and not the other).
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a0b6e02..c94353b 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -2,8 +2,10 @@
 	bool "Enable Driver Model for serial drivers"
 	depends on DM
 	help
-	  If you want to use driver model for serial drivers, say Y.
-	  To use legacy serial drivers, say N.
+	  Enable driver model for serial. This replaces
+	  drivers/serial/serial.c with the serial uclass, which
+	  implements serial_putc() etc. The uclass interface is
+	  defined in include/serial.h.
 
 config UNIPHIER_SERIAL
 	bool "UniPhier on-chip UART support"
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4cc00cd..63b0cbf 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -8,6 +8,7 @@
 ifdef CONFIG_DM_SERIAL
 obj-y += serial-uclass.o
 obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
+obj-$(CONFIG_PPC) += serial_ppc.o
 else
 obj-y += serial.o
 obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 9131a8f..3fc7104 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -258,6 +258,22 @@
 #endif
 	int ret;
 
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	if (ops->setbrg)
+		ops->setbrg += gd->reloc_off;
+	if (ops->getc)
+		ops->getc += gd->reloc_off;
+	if (ops->putc)
+		ops->putc += gd->reloc_off;
+	if (ops->pending)
+		ops->pending += gd->reloc_off;
+	if (ops->clear)
+		ops->clear += gd->reloc_off;
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+	if (ops->loop)
+		ops->loop += gd->reloc_off
+#endif
+#endif
 	/* Set the baud rate */
 	if (ops->setbrg) {
 		ret = ops->setbrg(dev, gd->baudrate);
diff --git a/drivers/serial/serial_ppc.c b/drivers/serial/serial_ppc.c
new file mode 100644
index 0000000..47141c6
--- /dev/null
+++ b/drivers/serial/serial_ppc.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id ppc_serial_ids[] = {
+	{ .compatible = "ns16550" },
+	{ }
+};
+
+static int ppc_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = ns16550_serial_ofdata_to_platdata(dev);
+	if (ret)
+		return ret;
+	plat->clock = get_serial_clock();
+
+	return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+	.name	= "serial_ppc",
+	.id	= UCLASS_SERIAL,
+	.of_match = ppc_serial_ids,
+	.ofdata_to_platdata = ppc_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe = ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 7c1f271..3641c9f 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -1,78 +1,21 @@
 /*
  * SuperH SCIF device driver.
  * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
+ * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
  * Copyright (C) 2002 - 2008  Paul Mundt
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <errno.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/processor.h>
-#include "serial_sh.h"
 #include <serial.h>
 #include <linux/compiler.h>
-
-#if defined(CONFIG_CONS_SCIF0)
-# define SCIF_BASE	SCIF0_BASE
-#elif defined(CONFIG_CONS_SCIF1)
-# define SCIF_BASE	SCIF1_BASE
-#elif defined(CONFIG_CONS_SCIF2)
-# define SCIF_BASE	SCIF2_BASE
-#elif defined(CONFIG_CONS_SCIF3)
-# define SCIF_BASE	SCIF3_BASE
-#elif defined(CONFIG_CONS_SCIF4)
-# define SCIF_BASE	SCIF4_BASE
-#elif defined(CONFIG_CONS_SCIF5)
-# define SCIF_BASE	SCIF5_BASE
-#elif defined(CONFIG_CONS_SCIF6)
-# define SCIF_BASE	SCIF6_BASE
-#elif defined(CONFIG_CONS_SCIF7)
-# define SCIF_BASE	SCIF7_BASE
-#else
-# error "Default SCIF doesn't set....."
-#endif
-
-#if defined(CONFIG_SCIF_A)
-	#define SCIF_BASE_PORT	PORT_SCIFA
-#else
-	#define SCIF_BASE_PORT	PORT_SCIF
-#endif
-
-static struct uart_port sh_sci = {
-	.membase	= (unsigned char*)SCIF_BASE,
-	.mapbase	= SCIF_BASE,
-	.type		= SCIF_BASE_PORT,
-};
-
-static void sh_serial_setbrg(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SCIF_USE_EXT_CLK
-	unsigned short dl = DL_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ);
-	sci_out(&sh_sci, DL, dl);
-	/* Need wait: Clock * 1/dl $B!_(B 1/16 */
-	udelay((1000000 * dl * 16 / CONFIG_SYS_CLK_FREQ) * 1000 + 1);
-#else
-	sci_out(&sh_sci, SCBRR,
-		SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ));
-#endif
-}
-
-static int sh_serial_init(void)
-{
-	sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
-	sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
-	sci_out(&sh_sci, SCSMR, 0);
-	sci_out(&sh_sci, SCSMR, 0);
-	sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
-	sci_in(&sh_sci, SCFCR);
-	sci_out(&sh_sci, SCFCR, 0);
-
-	serial_setbrg();
-	return 0;
-}
+#include <dm/platform_data/serial_sh.h>
+#include "serial_sh.h"
 
 #if defined(CONFIG_CPU_SH7760) || \
 	defined(CONFIG_CPU_SH7780) || \
@@ -86,7 +29,7 @@
 static int scif_rxfill(struct uart_port *port)
 {
 	if ((port->mapbase == 0xffe00000) ||
-		(port->mapbase == 0xffe08000)) {
+	    (port->mapbase == 0xffe08000)) {
 		/* SCIF0/1*/
 		return sci_in(port, SCRFDR) & 0xff;
 	} else {
@@ -109,80 +52,253 @@
 }
 #endif
 
-static int serial_rx_fifo_level(void)
+static void sh_serial_init_generic(struct uart_port *port)
 {
-	return scif_rxfill(&sh_sci);
+	sci_out(port, SCSCR , SCSCR_INIT(port));
+	sci_out(port, SCSCR , SCSCR_INIT(port));
+	sci_out(port, SCSMR, 0);
+	sci_out(port, SCSMR, 0);
+	sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
+	sci_in(port, SCFCR);
+	sci_out(port, SCFCR, 0);
 }
 
-static void handle_error(void)
+static void
+sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
 {
-	sci_in(&sh_sci, SCxSR);
-	sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci));
-	sci_in(&sh_sci, SCLSR);
-	sci_out(&sh_sci, SCLSR, 0x00);
+	if (port->clk_mode == EXT_CLK) {
+		unsigned short dl = DL_VALUE(baudrate, clk);
+		sci_out(port, DL, dl);
+		/* Need wait: Clock * 1/dl $B!_(B 1/16 */
+		udelay((1000000 * dl * 16 / clk) * 1000 + 1);
+	} else {
+		sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
+	}
 }
 
-static void serial_raw_putc(const char c)
+static void handle_error(struct uart_port *port)
 {
-	while (1) {
-		/* Tx fifo is empty */
-		if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci))
-			break;
-	}
+	sci_in(port, SCxSR);
+	sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
+	sci_in(port, SCLSR);
+	sci_out(port, SCLSR, 0x00);
+}
+
+static int serial_raw_putc(struct uart_port *port, const char c)
+{
+	/* Tx fifo is empty */
+	if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
+		return -EAGAIN;
 
-	sci_out(&sh_sci, SCxTDR, c);
-	sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
+	sci_out(port, SCxTDR, c);
+	sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
+
+	return 0;
 }
 
-static void sh_serial_putc(const char c)
+static int serial_rx_fifo_level(struct uart_port *port)
 {
-	if (c == '\n')
-		serial_raw_putc('\r');
-	serial_raw_putc(c);
+	return scif_rxfill(port);
 }
 
-static int sh_serial_tstc(void)
+static int sh_serial_tstc_generic(struct uart_port *port)
 {
-	if (sci_in(&sh_sci, SCxSR) & SCIF_ERRORS) {
-		handle_error();
+	if (sci_in(port, SCxSR) & SCIF_ERRORS) {
+		handle_error(port);
 		return 0;
 	}
 
-	return serial_rx_fifo_level() ? 1 : 0;
+	return serial_rx_fifo_level(port) ? 1 : 0;
 }
 
-
-static int serial_getc_check(void)
+static int serial_getc_check(struct uart_port *port)
 {
 	unsigned short status;
 
-	status = sci_in(&sh_sci, SCxSR);
+	status = sci_in(port, SCxSR);
 
 	if (status & SCIF_ERRORS)
-		handle_error();
-	if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
-		handle_error();
-	return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
+		handle_error(port);
+	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
+		handle_error(port);
+	return status & (SCIF_DR | SCxSR_RDxF(port));
 }
 
-static int sh_serial_getc(void)
+static int sh_serial_getc_generic(struct uart_port *port)
 {
 	unsigned short status;
 	char ch;
 
-	while (!serial_getc_check())
-		;
+	if (!serial_getc_check(port))
+		return -EAGAIN;
 
-	ch = sci_in(&sh_sci, SCxRDR);
-	status = sci_in(&sh_sci, SCxSR);
+	ch = sci_in(port, SCxRDR);
+	status = sci_in(port, SCxSR);
 
-	sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci));
+	sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 
 	if (status & SCIF_ERRORS)
-			handle_error();
+		handle_error(port);
+
+	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
+		handle_error(port);
+
+	return ch;
+}
+
+#ifdef CONFIG_DM_SERIAL
+
+static int sh_serial_pending(struct udevice *dev, bool input)
+{
+	struct uart_port *priv = dev_get_priv(dev);
+
+	return sh_serial_tstc_generic(priv);
+}
+
+static int sh_serial_putc(struct udevice *dev, const char ch)
+{
+	struct uart_port *priv = dev_get_priv(dev);
+
+	return serial_raw_putc(priv, ch);
+}
+
+static int sh_serial_getc(struct udevice *dev)
+{
+	struct uart_port *priv = dev_get_priv(dev);
+
+	return sh_serial_getc_generic(priv);
+}
+
+static int sh_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct sh_serial_platdata *plat = dev_get_platdata(dev);
+	struct uart_port *priv = dev_get_priv(dev);
+
+	sh_serial_setbrg_generic(priv, plat->clk, baudrate);
+
+	return 0;
+}
+
+static int sh_serial_probe(struct udevice *dev)
+{
+	struct sh_serial_platdata *plat = dev_get_platdata(dev);
+	struct uart_port *priv = dev_get_priv(dev);
+
+	priv->membase	= (unsigned char *)plat->base;
+	priv->mapbase	= plat->base;
+	priv->type	= plat->type;
+	priv->clk_mode	= plat->clk_mode;
+
+	sh_serial_init_generic(priv);
+
+	return 0;
+}
+
+static const struct dm_serial_ops sh_serial_ops = {
+	.putc = sh_serial_putc,
+	.pending = sh_serial_pending,
+	.getc = sh_serial_getc,
+	.setbrg = sh_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_sh) = {
+	.name	= "serial_sh",
+	.id	= UCLASS_SERIAL,
+	.probe	= sh_serial_probe,
+	.ops	= &sh_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+	.priv_auto_alloc_size = sizeof(struct uart_port),
+};
+
+#else /* CONFIG_DM_SERIAL */
+
+#if defined(CONFIG_CONS_SCIF0)
+# define SCIF_BASE	SCIF0_BASE
+#elif defined(CONFIG_CONS_SCIF1)
+# define SCIF_BASE	SCIF1_BASE
+#elif defined(CONFIG_CONS_SCIF2)
+# define SCIF_BASE	SCIF2_BASE
+#elif defined(CONFIG_CONS_SCIF3)
+# define SCIF_BASE	SCIF3_BASE
+#elif defined(CONFIG_CONS_SCIF4)
+# define SCIF_BASE	SCIF4_BASE
+#elif defined(CONFIG_CONS_SCIF5)
+# define SCIF_BASE	SCIF5_BASE
+#elif defined(CONFIG_CONS_SCIF6)
+# define SCIF_BASE	SCIF6_BASE
+#elif defined(CONFIG_CONS_SCIF7)
+# define SCIF_BASE	SCIF7_BASE
+#else
+# error "Default SCIF doesn't set....."
+#endif
+
+#if defined(CONFIG_SCIF_A)
+	#define SCIF_BASE_PORT	PORT_SCIFA
+#else
+	#define SCIF_BASE_PORT	PORT_SCIF
+#endif
+
+static struct uart_port sh_sci = {
+	.membase	= (unsigned char *)SCIF_BASE,
+	.mapbase	= SCIF_BASE,
+	.type		= SCIF_BASE_PORT,
+#ifdef CONFIG_SCIF_USE_EXT_CLK
+	.clk_mode =	EXT_CLK,
+#endif
+};
+
+static void sh_serial_setbrg(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	struct uart_port *port = &sh_sci;
+
+	sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
+}
+
+static int sh_serial_init(void)
+{
+	struct uart_port *port = &sh_sci;
+
+	sh_serial_init_generic(port);
+	serial_setbrg();
+
+	return 0;
+}
+
+static void sh_serial_putc(const char c)
+{
+	struct uart_port *port = &sh_sci;
+
+	if (c == '\n') {
+		while (1) {
+			if  (serial_raw_putc(port, '\r') != -EAGAIN)
+				break;
+		}
+	}
+	while (1) {
+		if  (serial_raw_putc(port, c) != -EAGAIN)
+			break;
+	}
+}
+
+static int sh_serial_tstc(void)
+{
+	struct uart_port *port = &sh_sci;
+
+	return sh_serial_tstc_generic(port);
+}
+
+static int sh_serial_getc(void)
+{
+	struct uart_port *port = &sh_sci;
+	int ch;
+
+	while (1) {
+		ch = sh_serial_getc_generic(port);
+		if (ch != -EAGAIN)
+			break;
+	}
 
-	if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
-		handle_error();
 	return ch;
 }
 
@@ -206,3 +322,4 @@
 {
 	return &sh_serial_drv;
 }
+#endif /* CONFIG_DM_SERIAL */
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index ef88c8f..528aa73 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -2,18 +2,16 @@
  * Copy and modify from linux/drivers/serial/sh-sci.h
  */
 
+#include <dm/platform_data/serial_sh.h>
+
 struct uart_port {
 	unsigned long	iobase;		/* in/out[bwl] */
 	unsigned char	*membase;	/* read/write[bwl] */
 	unsigned long	mapbase;	/* for ioremap */
-	unsigned int	type;		/* port type */
+	enum sh_serial_type type;	/* port type */
+	enum sh_clk_mode clk_mode;	/* clock mode */
 };
 
-#define PORT_SCI	52
-#define PORT_SCIF	53
-#define PORT_SCIFA	83
-#define PORT_SCIFB	93
-
 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 #include <asm/regs306x.h>
 #endif
@@ -526,6 +524,7 @@
 SCIF_FNS(SCxTDR, 0x20,  8)
 SCIF_FNS(SCxRDR, 0x24,  8)
 SCIF_FNS(SCLSR,  0x00,  0)
+SCIF_FNS(DL,	 0x00,  0) /* dummy */
 #elif defined(CONFIG_ARCH_SH7372) || \
 	defined(CONFIG_R8A7740)
 SCIF_FNS(SCSMR,  0x00, 16)
@@ -541,6 +540,7 @@
 SCIx_FNS(SCxTDR, 0x20,  8, 0x40,  8)
 SCIx_FNS(SCxRDR, 0x24,  8, 0x60,  8)
 SCIF_FNS(SCLSR,  0x00,  0)
+SCIF_FNS(DL,	 0x00,  0) /* dummy */
 #elif defined(CONFIG_CPU_SH7723) ||\
 	defined(CONFIG_CPU_SH7724)
 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
@@ -555,6 +555,7 @@
 SCIF_FNS(SCFCR,  0x18, 16)
 SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCLSR,  0x24, 16)
+SCIF_FNS(DL,	 0x00,  0) /* dummy */
 #else
 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
@@ -583,18 +584,21 @@
 SCIF_FNS(SCSPTR,			0,  0, 0x24, 16)
 SCIF_FNS(SCLSR,				0,  0, 0x28, 16)
 #else
+
 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 #if defined(CONFIG_CPU_SH7722)
 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 #else
 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 #endif
+SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
+#endif
 #if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 SCIF_FNS(DL,				0,  0, 0x30, 16)
 SCIF_FNS(CKS,				0,  0, 0x34, 16)
-#endif
-SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
+#else
+SCIF_FNS(DL,				0,  0, 0x0,  0) /* dummy */
 #endif
 #endif
 #define sci_in(port, reg) sci_##reg##_in(port)
@@ -725,14 +729,14 @@
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #elif defined(CONFIG_CPU_SH7723) ||\
 	defined(CONFIG_CPU_SH7724)
-static inline int scbrr_calc(struct uart_port port, int bps, int clk)
+static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 {
-	if (port.type == PORT_SCIF)
+	if (port->type == PORT_SCIF)
 		return (clk+16*bps)/(32*bps)-1;
 	else
 		return ((clk*2)+16*bps)/(16*bps)-1;
 }
-#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
+#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
@@ -742,3 +746,7 @@
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif
+
+#ifndef DL_VALUE
+#define DL_VALUE(bps, clk) 0
+#endif
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e1678e6..7ae2727 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -2,5 +2,11 @@
 	bool "Enable Driver Model for SPI drivers"
 	depends on DM
 	help
-	  If you want to use driver model for SPI drivers, say Y.
-	  To use legacy SPI drivers, say N.
+	  Enable driver model for SPI. The SPI slave interface
+	  (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
+	  the SPI uclass. Drivers provide methods to access the SPI
+	  buses that they control. The uclass interface is defined in
+	  include/spi.h. The existing spi_slave structure is attached
+	  as 'parent data' to every slave on each bus. Slaves
+	  typically use driver-private data instead of extending the
+	  spi_slave structure.
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
new file mode 100644
index 0000000..3c6b36d
--- /dev/null
+++ b/drivers/thermal/Kconfig
@@ -0,0 +1,7 @@
+config DM_THERMAL
+	bool "Driver support for thermal devices"
+	help
+	  Enable support for temporary-sensing devices. Some SoCs have on-chip
+	  temperature sensors to permit warnings, speed throttling or even
+	  automatic power-off when the temperature gets too high or low. Other
+	  devices may be discrete but connected on a suitable bus.
diff --git a/include/config_defaults.h b/include/config_defaults.h
index 4d49315..ad08c1d 100644
--- a/include/config_defaults.h
+++ b/include/config_defaults.h
@@ -20,10 +20,4 @@
 #define CONFIG_ZLIB 1
 #define CONFIG_PARTITIONS 1
 
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM_WARN
-#define CONFIG_DM_DEVICE_REMOVE
-#define CONFIG_DM_STDIO
-#endif
-
 #endif
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 2aea899..73e1b0a 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -20,8 +20,10 @@
  */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#endif
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 8eeb15c..7a1499d 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -11,6 +11,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <linux/kconfig.h>
+
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
@@ -19,10 +23,10 @@
  * and Arches dual (460GT)
  */
 #ifdef CONFIG_CANYONLANDS
-#define CONFIG_460EX		1	/* Specific PPC460EX		*/
+#define CONFIG_460EX			/* Specific PPC460EX		*/
 #define CONFIG_HOSTNAME		canyonlands
 #else
-#define CONFIG_460GT		1	/* Specific PPC460GT		*/
+#define CONFIG_460GT			/* Specific PPC460GT		*/
 #ifdef CONFIG_GLACIER
 #define CONFIG_HOSTNAME		glacier
 #else
@@ -32,7 +36,7 @@
 #endif
 #endif
 
-#define CONFIG_440		1
+#define CONFIG_440
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -45,10 +49,10 @@
 
 #define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
 
-#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
-#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
-#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
-#define CONFIG_BOARD_TYPES		1	/* support board types */
+#define CONFIG_BOARD_EARLY_INIT_F		/* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R		/* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R			/* Call misc_init_r */
+#define CONFIG_BOARD_TYPES			/* support board types */
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -134,7 +138,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	/* Use AMD (Spansion) reset cmd */
 
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
@@ -172,9 +176,9 @@
  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
  * code.
  */
-#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
 #define SPD_EEPROM_ADDRESS	{0x50, 0x51}	/* SPD i2c spd addresses*/
-#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+#define CONFIG_DDR_ECC			/* with ECC support		*/
 #define CONFIG_DDR_RQDC_FIXED	0x80000038 /* fixed value for RQDC	*/
 
 #else /* defined(CONFIG_ARCHES) */
@@ -262,8 +266,8 @@
 #define CONFIG_4xx_CONFIG_BLOCKSIZE		16
 
 /* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
-#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
-#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_LM75				/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414			/* use AD7414		*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
 #define CONFIG_SYS_DTT_MAX_TEMP	70
 #define CONFIG_SYS_DTT_LOW_TEMP	-30
@@ -275,14 +279,14 @@
 
 #if !defined(CONFIG_ARCHES)
 /* RTC configuration */
-#define CONFIG_RTC_M41T62	1
+#define CONFIG_RTC_M41T62
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #endif
 
 /*-----------------------------------------------------------------------
  * Ethernet
  *----------------------------------------------------------------------*/
-#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_IBM_EMAC4_V4
 
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
@@ -322,9 +326,9 @@
 #define CONFIG_GPCS_PHY2_ADDR   0xC
 #endif	/* !defined(CONFIG_ARCHES) */
 
-#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_DYNAMIC_ANEG	1
+#define CONFIG_PHY_RESET		/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG
 
 /*-----------------------------------------------------------------------
  * USB-OHCI
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 1f64495..4207504 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -21,14 +21,7 @@
 #define CONFIG_MACH_TYPE		4273
 
 #ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-
-#define CONFIG_DM_GPIO
 #define CONFIG_CMD_GPIO
-
-#define CONFIG_DM_SERIAL
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 #endif
 
 /* Display information on boot */
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 1f3ee55..59676ae 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -17,12 +17,6 @@
 #include <linux/sizes.h>
 
 #define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
-#define CONFIG_DM_SPI
-#define CONFIG_DM_SPI_FLASH
 
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
@@ -42,7 +36,6 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* Size of malloc() pool before and after relocation */
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
 
 /* select serial console configuration */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 4f137fc..620f950 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -39,7 +39,6 @@
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 
 /* Init Functions */
 #define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index f0f721e..4aa8101 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -25,9 +25,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_DM
-#define CONFIG_DM_THERMAL
-#define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
 #define CONFIG_IMX6_THERMAL
 
 #define CONFIG_SYS_GENERIC_BOARD
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 404b922..1005b9e 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -229,7 +229,6 @@
 
 #define CONFIG_DM
 #define CONFIG_DM_THERMAL
-#define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
 #define CONFIG_IMX6_THERMAL
 
 #define CONFIG_CMD_FUSE
diff --git a/include/configs/novena.h b/include/configs/novena.h
index ea75d2c..074110c 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -116,7 +116,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 
 #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 
 /* SPL */
 #define CONFIG_SPL_FAT_SUPPORT
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
index a1c980d..f724164 100644
--- a/include/configs/peach-pi.h
+++ b/include/configs/peach-pi.h
@@ -44,7 +44,6 @@
 
 #define CONFIG_POWER_TPS65090_EC
 #define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
-#define CONFIG_DM_CROS_EC
 
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 6516a72..de12a9e 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -44,7 +44,6 @@
 
 #define CONFIG_POWER_TPS65090_EC
 #define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
-#define CONFIG_DM_CROS_EC
 
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index c94f411..7ad8d08 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -30,12 +30,6 @@
  */
 #define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
 
-/* Enable driver model */
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
-
 /* Memory layout */
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
@@ -52,7 +46,6 @@
 					 CONFIG_SYS_SDRAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_MALLOC_LEN		SZ_4M
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 #define CONFIG_SYS_MEMTEST_START	0x00100000
 #define CONFIG_SYS_MEMTEST_END		0x00200000
 #define CONFIG_LOADADDR			0x00200000
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index dfa2e07..8fadc68 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -40,7 +40,6 @@
 #define CONFIG_CMDLINE_EDITING
 
 /* Size of malloc() pool before and after relocation */
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
 
 /*
@@ -290,9 +289,5 @@
 #define CONFIG_OF_LIBFDT
 
 #define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index e9d3f32..5c11650 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -23,15 +23,6 @@
 
 #define CONFIG_BOOTSTAGE
 #define CONFIG_BOOTSTAGE_REPORT
-#define CONFIG_CMD_DEMO
-#define CONFIG_CMD_DM
-#define CONFIG_DM_DEMO
-#define CONFIG_DM_DEMO_SIMPLE
-#define CONFIG_DM_DEMO_SHAPE
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_TEST
-#define CONFIG_DM_SERIAL
-#define CONFIG_DM_CROS_EC
 
 #define CONFIG_SYS_STDIO_DEREGISTER
 
@@ -69,7 +60,6 @@
 /*
  * Size of malloc() pool, before and after relocation
  */
-#define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
 #define CONFIG_MALLOC_F_ADDR		0x0010000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)	/* 32MB  */
 
@@ -96,8 +86,6 @@
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH
-#define CONFIG_DM_SPI
-#define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH_ATMEL
 #define CONFIG_SPI_FLASH_EON
 #define CONFIG_SPI_FLASH_GIGADEVICE
@@ -108,7 +96,6 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_WINBOND
 
-#define CONFIG_DM_I2C
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C_SANDBOX
 #define CONFIG_I2C_EDID
diff --git a/include/configs/silk.h b/include/configs/silk.h
new file mode 100644
index 0000000..a4235e9
--- /dev/null
+++ b/include/configs/silk.h
@@ -0,0 +1,117 @@
+/*
+ * include/configs/silk.h
+ *     This file is silk board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SILK_H
+#define __SILK_H
+
+#undef DEBUG
+#define CONFIG_R8A7794
+#define CONFIG_RMOBILE_BOARD_STRING "Silk"
+
+#include "rcar-gen2-common.h"
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE	0x70000000
+#else
+#define CONFIG_SYS_TEXT_BASE	0xE6304000
+#endif
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
+#endif
+#define STACK_AREA_SIZE			0xC000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SCIF_USE_EXT_CLK
+
+/* FLASH */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_QUAD
+#define CONFIG_SYS_NO_FLASH
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
+#define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)
+#define CONFIG_SH_SCIF_CLK_FREQ	14745600 /* External Clock */
+
+#define CONFIG_SYS_TMU_CLK_DIV  4
+
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
+#define CONFIG_SYS_I2C_SH_SPEED0	400000
+#define CONFIG_SYS_I2C_SH_SPEED1	400000
+#define CONFIG_SYS_I2C_SH_SPEED2	400000
+#define CONFIG_SH_I2C_DATA_HIGH		4
+#define CONFIG_SH_I2C_DATA_LOW		5
+#define CONFIG_SH_I2C_CLOCK		10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR	0x58 /* da9063 */
+
+/* USB */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_RMOBILE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+/* MMCIF */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SH_MMCIF
+#define CONFIG_SH_MMCIF_ADDR	0xee200000
+#define CONFIG_SH_MMCIF_CLK	48000000
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA	0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA	0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA	0x00000180
+/* SCIF2 */
+#define CONFIG_SMSTP7_ENA	0x00080000
+
+#endif /* __SILK_H */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 982d0dc..080fc3a 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -48,9 +48,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
 
-/* Small malloc pool before relocation */
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
-
 /*
  * select serial console configuration
  */
@@ -224,9 +221,5 @@
 #define CONFIG_OF_LIBFDT
 
 #define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 9fa644f..6c68596 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -21,11 +21,6 @@
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* External Crystal, in Hz */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
 #define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 
 /* CPU */
 #define CONFIG_ARCH_CPU_INIT
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 6b1f967..ee227fe 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -190,10 +190,6 @@
  * QSPI support
  */
 #ifdef CONFIG_OF_CONTROL	/* QSPI is controlled via DT */
-#define CONFIG_CMD_DM
-#define CONFIG_DM
-#define CONFIG_DM_SPI
-#define CONFIG_DM_SPI_FLASH
 #define CONFIG_CADENCE_QSPI
 /* Enable multiple SPI NOR flash manufacturers */
 #define CONFIG_SPI_FLASH		/* SPI flash subsystem */
@@ -210,9 +206,6 @@
 #endif
 
 #ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
-#define CONFIG_CMD_DM
-#define CONFIG_DM
-#define CONFIG_DM_SPI
 #define CONFIG_DESIGNWARE_SPI
 #define CONFIG_CMD_SPI
 #endif
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index fd9bd63..156e0fa 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -28,21 +28,10 @@
 	(PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
 #define CONFIG_SYS_MAXARGS			16
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 16 * 1024)
-#define CONFIG_SYS_MALLOC_F_LEN			0x2000
 
-#define CONFIG_DM
 /* serial port (PL011) configuration */
 #define CONFIG_BAUDRATE				115200
-#ifdef CONFIG_DM
-#define CONFIG_DM_SERIAL
 #define CONFIG_PL01X_SERIAL
-#else
-#define CONFIG_SYS_SERIAL0                     0x80406000
-#define CONFIG_CONS_INDEX			0
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL01x_PORTS                     {(void *)CONFIG_SYS_SERIAL0}
-#define CONFIG_PL011_CLOCK                     (2700 * 1000)
-#endif
 
 /* user interface */
 #define CONFIG_SYS_PROMPT			"STV0991> "
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index cea52db..09889ee 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -28,11 +28,7 @@
 #define CONFIG_SYS_TEXT_BASE		0x4a000000
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
-# define CONFIG_CMD_DM
-# define CONFIG_DM_GPIO
-# define CONFIG_DM_SERIAL
 # define CONFIG_DW_SERIAL
-# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
 #endif
 
 /*
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 8f1e370..005fc6a 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -18,16 +18,6 @@
 
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM_SERIAL
-#endif
-#define CONFIG_DM_SPI
-#define CONFIG_DM_SPI_FLASH
-#define CONFIG_DM_I2C
-
 #define CONFIG_SYS_TIMER_RATE		1000000
 #define CONFIG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
 
@@ -47,7 +37,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 
 #define CONFIG_SYS_NONCACHED_MEMORY	(1 << 20)       /* 1 MiB */
 
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 598526b..20a55f4 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -20,14 +20,7 @@
 #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_DM
-# define CONFIG_DM
-#endif
-# define CONFIG_CMD_DM
-# define CONFIG_DM_GPIO
-# define CONFIG_DM_SERIAL
 # define CONFIG_OMAP_SERIAL
-# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
 #endif
 
 #include <asm/arch/omap.h>
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 3c634ee..840e108 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -19,12 +19,7 @@
 #include <asm/arch/omap3.h>
 
 #ifndef CONFIG_SPL_BUILD
-# define CONFIG_DM
-# define CONFIG_CMD_DM
-# define CONFIG_DM_GPIO
-# define CONFIG_DM_SERIAL
 # define CONFIG_OMAP_SERIAL
-# define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
 #endif
 
 /* The chip has SDRC controller */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 9420e6b..3f738fb 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -80,8 +80,6 @@
 #define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
 #define CONFIG_SMC911X_32_BIT
 
-#define CONFIG_SYS_MALLOC_F_LEN  0x2000
-
 /*-----------------------------------------------------------------------
  * MMU and Cache Setting
  *----------------------------------------------------------------------*/
@@ -192,8 +190,6 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_DM
-
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 062e6c2..994874c 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -22,11 +22,6 @@
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
-
 #define CONFIG_LMB
 #define CONFIG_OF_LIBFDT
 
@@ -192,7 +187,6 @@
 #define CONFIG_SYS_STACK_SIZE			(32 * 1024)
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_LEN			0x200000
-#define CONFIG_SYS_MALLOC_F_LEN			(2 << 10)
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/dm/device.h b/include/dm/device.h
index 81afa8c..7a48eb8 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -12,6 +12,7 @@
 #define _DM_DEVICE_H
 
 #include <dm/uclass-id.h>
+#include <fdtdec.h>
 #include <linker_lists.h>
 #include <linux/list.h>
 
@@ -351,4 +352,13 @@
  */
 int device_find_next_child(struct udevice **devp);
 
+/**
+ * dev_get_addr() - Get the reg property of a device
+ *
+ * @dev: Pointer to a device
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr(struct udevice *dev);
+
 #endif
diff --git a/include/dm/platform_data/serial_sh.h b/include/dm/platform_data/serial_sh.h
new file mode 100644
index 0000000..0271ad6
--- /dev/null
+++ b/include/dm/platform_data/serial_sh.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2014  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (c) 2014  Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __serial_sh_h
+#define __serial_sh_h
+
+enum sh_clk_mode {
+	INT_CLK,
+	EXT_CLK,
+};
+
+enum sh_serial_type {
+	PORT_SCI,
+	PORT_SCIF,
+	PORT_SCIFA,
+	PORT_SCIFB,
+};
+
+/*
+ * Information about SCIF port
+ *
+ * @base:	Register base address
+ * @clk:	Input clock rate, used for calculating the baud rate divisor
+ * @clk_mode:	Clock mode, set internal (INT) or external (EXT)
+ * @type:	Type of SCIF
+ */
+struct sh_serial_platdata {
+	unsigned long base;
+	unsigned int clk;
+	enum sh_clk_mode clk_mode;
+	enum sh_serial_type type;
+};
+#endif /* __serial_sh_h */
diff --git a/include/i2c.h b/include/i2c.h
index 27fe00f..31b0389 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -25,14 +25,13 @@
  * enough as to be incompatible for compilation purposes.
  */
 
-#ifdef CONFIG_DM_I2C
-
 enum dm_i2c_chip_flags {
 	DM_I2C_CHIP_10BIT	= 1 << 0, /* Use 10-bit addressing */
 	DM_I2C_CHIP_RD_ADDRESS	= 1 << 1, /* Send address for each read byte */
 	DM_I2C_CHIP_WR_ADDRESS	= 1 << 2, /* Send address for each write byte */
 };
 
+struct udevice;
 /**
  * struct dm_i2c_chip - information about an i2c chip
  *
@@ -125,21 +124,21 @@
 		 struct udevice **devp);
 
 /**
- * i2c_set_bus_speed() - set the speed of a bus
+ * dm_i2c_set_bus_speed() - set the speed of a bus
  *
  * @bus:	Bus to adjust
  * @speed:	Requested speed in Hz
  * @return 0 if OK, -EINVAL for invalid values
  */
-int i2c_set_bus_speed(struct udevice *bus, unsigned int speed);
+int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed);
 
 /**
- * i2c_get_bus_speed() - get the speed of a bus
+ * dm_i2c_get_bus_speed() - get the speed of a bus
  *
  * @bus:	Bus to check
  * @return speed of selected I2C bus in Hz, -ve on error
  */
-int i2c_get_bus_speed(struct udevice *bus);
+int dm_i2c_get_bus_speed(struct udevice *bus);
 
 /**
  * i2c_set_chip_flags() - set flags for a chip
@@ -439,8 +438,6 @@
 int i2c_chip_ofdata_to_platdata(const void *blob, int node,
 				struct dm_i2c_chip *chip);
 
-#endif
-
 #ifndef CONFIG_DM_I2C
 
 /*
diff --git a/include/net.h b/include/net.h
index 73ea88b..43e3d28 100644
--- a/include/net.h
+++ b/include/net.h
@@ -512,10 +512,6 @@
  */
 int ip_checksum_ok(const void *addr, unsigned nbytes);
 
-/* Checksum */
-extern int	NetCksumOk(uchar *, int);	/* Return true if cksum OK */
-extern uint	NetCksum(uchar *, int);		/* Calculate the checksum */
-
 /* Callbacks */
 extern rxhand_f *net_get_udp_handler(void);	/* Get UDP RX packet handler */
 extern void net_set_udp_handler(rxhand_f *);	/* Set UDP RX packet handler */
diff --git a/net/net.c b/net/net.c
index 2bea07b..b60ce62 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1086,7 +1086,7 @@
 		if ((ip->ip_hl_v & 0x0f) > 0x05)
 			return;
 		/* Check the Checksum of the header */
-		if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE / 2)) {
+		if (!ip_checksum_ok((uchar *)ip, IP_HDR_SIZE)) {
 			debug("checksum bad\n");
 			return;
 		}
@@ -1291,27 +1291,6 @@
 /**********************************************************************/
 
 int
-NetCksumOk(uchar *ptr, int len)
-{
-	return !((NetCksum(ptr, len) + 1) & 0xfffe);
-}
-
-
-unsigned
-NetCksum(uchar *ptr, int len)
-{
-	ulong	xsum;
-	ushort *p = (ushort *)ptr;
-
-	xsum = 0;
-	while (len-- > 0)
-		xsum += *p++;
-	xsum = (xsum & 0xffff) + (xsum >> 16);
-	xsum = (xsum & 0xffff) + (xsum >> 16);
-	return xsum & 0xffff;
-}
-
-int
 NetEthHdrSize(void)
 {
 	ushort myvlanid;
@@ -1410,7 +1389,7 @@
 	net_set_ip_header(pkt, dest, NetOurIP);
 	ip->ip_len   = htons(IP_UDP_HDR_SIZE + len);
 	ip->ip_p     = IPPROTO_UDP;
-	ip->ip_sum   = ~NetCksum((uchar *)ip, IP_HDR_SIZE >> 1);
+	ip->ip_sum   = compute_ip_checksum(ip, IP_HDR_SIZE);
 
 	ip->udp_src  = htons(sport);
 	ip->udp_dst  = htons(dport);
diff --git a/net/ping.c b/net/ping.c
index 2be56ed..366f518 100644
--- a/net/ping.c
+++ b/net/ping.c
@@ -29,14 +29,14 @@
 
 	ip->ip_len   = htons(IP_ICMP_HDR_SIZE);
 	ip->ip_p     = IPPROTO_ICMP;
-	ip->ip_sum   = ~NetCksum((uchar *)ip, IP_HDR_SIZE >> 1);
+	ip->ip_sum   = compute_ip_checksum(ip, IP_HDR_SIZE);
 
 	icmp->type = ICMP_ECHO_REQUEST;
 	icmp->code = 0;
 	icmp->checksum = 0;
 	icmp->un.echo.id = 0;
 	icmp->un.echo.sequence = htons(PingSeqNo++);
-	icmp->checksum = ~NetCksum((uchar *)icmp, ICMP_HDR_SIZE	>> 1);
+	icmp->checksum = compute_ip_checksum(icmp, ICMP_HDR_SIZE);
 }
 
 static int ping_send(void)
@@ -101,13 +101,11 @@
 		ip->ip_off = 0;
 		NetCopyIP((void *)&ip->ip_dst, &ip->ip_src);
 		NetCopyIP((void *)&ip->ip_src, &NetOurIP);
-		ip->ip_sum = ~NetCksum((uchar *)ip,
-				       IP_HDR_SIZE >> 1);
+		ip->ip_sum = compute_ip_checksum(ip, IP_HDR_SIZE);
 
 		icmph->type = ICMP_ECHO_REPLY;
 		icmph->checksum = 0;
-		icmph->checksum = ~NetCksum((uchar *)icmph,
-			(len - IP_HDR_SIZE) >> 1);
+		icmph->checksum = compute_ip_checksum(icmph, len - IP_HDR_SIZE);
 		NetSendPacket((uchar *)et, eth_hdr_size + len);
 		return;
 /*	default:
diff --git a/test/Kconfig b/test/Kconfig
new file mode 100644
index 0000000..1fb1716
--- /dev/null
+++ b/test/Kconfig
@@ -0,0 +1 @@
+source "test/dm/Kconfig"
diff --git a/test/dm/Kconfig b/test/dm/Kconfig
new file mode 100644
index 0000000..a9d0298
--- /dev/null
+++ b/test/dm/Kconfig
@@ -0,0 +1,8 @@
+config DM_TEST
+	bool "Enable driver model test command"
+	depends on SANDBOX && CMD_DM
+	help
+	  This enables the 'dm test' command which runs a series of unit
+	  tests on the driver model code. Each subsystem (uclass) is tested.
+	  If all is well then all tests pass although there will be a few
+	  messages printed along the way.
diff --git a/test/dm/i2c.c b/test/dm/i2c.c
index ef88372..541b73b 100644
--- a/test/dm/i2c.c
+++ b/test/dm/i2c.c
@@ -67,10 +67,10 @@
 
 	ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
 	ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
-	ut_assertok(i2c_set_bus_speed(bus, 100000));
+	ut_assertok(dm_i2c_set_bus_speed(bus, 100000));
 	ut_assertok(dm_i2c_read(dev, 0, buf, 5));
-	ut_assertok(i2c_set_bus_speed(bus, 400000));
-	ut_asserteq(400000, i2c_get_bus_speed(bus));
+	ut_assertok(dm_i2c_set_bus_speed(bus, 400000));
+	ut_asserteq(400000, dm_i2c_get_bus_speed(bus));
 	ut_assertok(dm_i2c_read(dev, 0, buf, 5));
 	ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5));