commit af32b89e4ff837f8b4038f8f2ea2a46e6b86734f
author Kongyang Liu <seashell11234455@gmail.com> Sat Apr 20 15:00:28 2024 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> Thu May 02 00:01:18 2024 +0800
tree e8112f263ba473459adcaa88d63ab242009675c3
parent 1fbf86c04efbb1bda8bf94cdd015029e4c366844

riscv: dts: sophgo: Add ethernet node

Add ethernet node for cv1800b SoC

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

arch/riscv/dts/cv18xx.dtsi

diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index ec99c4d..5e83ee1 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -52,6 +52,20 @@
 		#clock-cells = <0>;
 	};
 
+	eth_csrclk: eth-csrclk {
+		compatible = "fixed-clock";
+		clock-frequency = <250000000>;
+		clock-output-names = "eth_csrclk";
+		#clock-cells = <0x0>;
+	};
+
+	eth_ptpclk: eth-ptpclk {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "eth_ptpclk";
+		#clock-cells = <0x0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -138,6 +152,15 @@
 			};
 		};
 
+		ethernet0: ethernet@4070000 {
+			compatible = "sophgo,cv1800b-dwmac";
+			reg = <0x04070000 0x10000>;
+			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&eth_csrclk>, <&eth_ptpclk>;
+			clock-names = "stmmaceth", "ptp_ref";
+			status = "disabled";
+		};
+
 		uart0: serial@4140000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x04140000 0x100>;