tree a29aaf854053be0d81157e8ee1dc106cc9956b8d
parent f3f69a4e46f1b167813b39e2311a14e949e61d86
author Anthony Felice <tony.felice@timesys.com> 1410025626 +0200
committer Albert ARIBAUD <albert.u.boot@aribaud.net> 1412680111 +0200

vf610twr: Tune DDR initialization settings

Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.

Changed register settings to comply with JEDEC required values.

Changed timing parameters because they included full clock
periods that were doing nothing.

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>